CN114944425A - Power device and manufacturing method thereof - Google Patents

Abstract

The invention provides a power device and a manufacturing method thereof. The power device includes a semiconductor substrate and a field plate structure, the field plate structure is arranged on a first side of the semiconductor substrate, the first side of the semiconductor substrate has source/drain regions and a gate, and the field plate structure includes: an insulating layer, an insulating layer The layer is arranged on the first side, and the insulating layer is arranged in contact with the source/drain regions and the gate electrode; the first conductive layer covers the side of the insulating layer away from the semiconductor substrate. By arranging an insulating layer on the first side of the semiconductor substrate, the potential lines concentrated at the edge of the gate are reduced, thereby improving the breakdown voltage of the power device. The power device can be individually wired through the first conductive layer, so as to be designed to operate independently of voltage, thereby reducing the on-resistance of the power device.

Description

Power device and method of making the same

technical field

The present invention relates to a manufacturing method of a semiconductor device, in particular, to a power device and a manufacturing method thereof.

Background technique

In high-voltage integrated devices, the breakdown voltage (eg, drain junction breakdown voltage and gate dielectric breakdown voltage) of an LDMOS transistor is an important factor that directly affects the stable operation of the LDMOS transistor. In addition, the on-resistance (Ron) value of the LDMOS transistor is also an important factor affecting the electrical characteristics of the LDMOS transistor (eg, the current driving capability of the LDMOS transistor).

Field plate is a terminal technology often used in high-voltage LDMOS, which can optimize the electric field distribution, effectively suppress the surface electric field, and prevent the surface breakdown of the device. However, the BV improvement effect of the traditional _SiO2 -based field plate is limited, and the field plate technology often requires a separate process, increasing its manufacturing difficulty and cost.

SUMMARY OF THE INVENTION

The main purpose of the present invention is to provide a power device and a manufacturing method thereof to solve the problems of low breakdown voltage and high on-resistance in the prior art.

In order to achieve the above object, according to an aspect of the present invention, a power device is provided, the power device includes a semiconductor substrate and a field plate structure, the field plate structure is disposed on a first side of the semiconductor substrate, and the first side of the semiconductor substrate The side has source/drain regions and a gate, and the field plate structure includes: an insulating layer, the insulating layer is arranged on the first side, and the insulating layer is arranged in contact with the source/drain regions and the gate; a first conductive layer, the first conductive layer covers on the side of the insulating layer away from the semiconductor substrate.

Further, the insulating layer includes a high-k gate dielectric layer.

Further, the material of the first conductive layer includes metal and/or polysilicon.

Further, the material of the first conductive layer includes doped polysilicon.

Further, the power device includes: a first metal compound layer covering a side of the first conductive layer away from the semiconductor substrate.

Further, the power device further includes: a second metal compound layer, arranged in contact with the source/drain regions and the gate electrode; a plurality of conductive connection parts, each of which is arranged in contact with the second metal compound layer, and is arranged along a distance away from the semiconductor substrate extending in the direction of the bottom.

Further, the power device further includes: a second conductive layer, the second conductive layer is disposed on the side of the conductive connection portion away from the second metal compound layer, and the conductive connection portion connects the second metal compound layer and the second conductive layer.

According to another aspect of the present invention, a method for fabricating a power device is provided, the fabrication method comprising the steps of: providing a semiconductor substrate, the semiconductor substrate having a first side, and the first side having source/drain regions and a gate; A dielectric material is deposited on the first side to form an insulating layer, the insulating layer is arranged on the first side, and the insulating layer is arranged in contact with the source/drain regions and the gate electrode; a first conductive layer is formed on the side of the insulating layer away from the semiconductor substrate, The first conductive layer covers the insulating layer.

Further, after the step of forming the first conductive layer, the manufacturing method further includes: forming a first metal compound layer on the first side, the metal compound layer covering the side of the first conductive layer away from the semiconductor substrate.

Further, the material for forming the first conductive layer includes polysilicon, and the step of forming the first metal compound layer includes: depositing a metal layer on the first side, so that the metal layer is in contact with the source/drain regions and the first conductive layer; making the metal layer Reacts with polysilicon to form a first metal compound layer.

By applying the technical solutions of the present invention, a power device is provided, comprising a semiconductor substrate and a field plate structure, wherein the field plate structure is arranged on a first side of the semiconductor substrate, and the first side of the semiconductor substrate has source/drain regions and a gate , the field plate structure includes: an insulating layer, the insulating layer is arranged on the first side, and the insulating layer is arranged in contact with the source/drain regions and the gate; a first conductive layer, the first conductive layer covers the insulating layer away from the semiconductor substrate. side. By arranging an insulating layer on the first side of the semiconductor substrate, the potential lines concentrated at the gate edge are reduced, thereby increasing the breakdown voltage of the power device. By arranging the first conductive layer on the first side of the insulating layer away from the semiconductor substrate, So that the first conductive layer can be wired separately and designed to operate with independent voltage, thereby reducing the on-resistance of the power device.

Description of drawings

The accompanying drawings forming a part of the present invention are used to provide further understanding of the present invention, and the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, and do not constitute an improper limitation of the present invention. In the attached image:

FIG. 1 shows a schematic cross-sectional structure diagram of a power device according to an embodiment of the present invention;

FIG. 2 shows a schematic cross-sectional structure diagram of the provided semiconductor substrate in the manufacturing method of the power device shown in FIG. 1;

FIG. 3 shows a schematic cross-sectional structure diagram of forming an insulating layer and a first conductive layer on the first side of the semiconductor substrate shown in FIG. 2;

FIG. 4 shows a schematic cross-sectional structure diagram of forming a first metal compound layer and a second metal compound layer on the first side shown in FIG. 3;

FIG. 5 shows a schematic cross-sectional structure diagram after removing the redundant metal compound layer, the first conductive layer and the insulating layer on the first side shown in FIG. 4 .

Wherein, the above-mentioned drawings include the following reference signs:

10, semiconductor substrate; 20, insulating layer; 30, first conductive layer; 40, first metal compound layer; 50, second metal compound layer; 60, conductive connection part; 70, second conductive layer; 80, source 90, drain region; 100, gate; 110, body region; 120, body contact region; 130, drift region; 140, shallow trench isolation region.

Detailed ways

It should be noted that the embodiments of the present invention and the features of the embodiments may be combined with each other under the condition of no conflict. The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

In order to make those skilled in the art better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only Embodiments are part of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

It should be noted that the terms "first", "second" and the like in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and are not necessarily used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having" and any variations thereof, are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those expressly listed Rather, those steps or units may include other steps or units not expressly listed or inherent to these processes, methods, products or devices.

As mentioned in the background art, both breakdown voltage and on-resistance are important performance indicators of power devices. Because the use of the field plate structure can greatly improve the breakdown voltage of the device, it can further suppress the current collapse, thereby improving the device's performance. Reliability, and therefore, field plates are a termination technology that is often used in power devices. However, the improvement effect of the breakdown voltage of the traditional SiO ₂ based field plate is limited, and it is urgent to obtain a better power device to achieve the purpose of effectively improving the breakdown voltage of the device.

In order to solve the above-mentioned technical problem, the applicant of the present invention provides a power device, as shown in FIG. 1 , comprising a semiconductor substrate 10 and a field plate structure, and the above-mentioned field plate structure is arranged on the first side of the above-mentioned semiconductor substrate 10, The first side of the semiconductor substrate 10 has a source region 80 and a drain region 90 of source/drain regions and a gate electrode 100, and the field plate structure includes: an insulating layer 20, the insulating layer 20 is disposed on the first side, and the above The insulating layer 20 is arranged in contact with the source region 80 and the drain region 90 of the source/drain region and the gate electrode 100; the first conductive layer 30, the first conductive layer 30 covers the insulating layer 20 away from the semiconductor substrate 10. side.

In the above device, the insulating layer 20 in contact with the source region 80 and the drain region 90 of the source/drain region and the gate electrode 100 is provided on the first side, and then the insulating layer 20 is covered on the side away from the semiconductor substrate 10. The conductive layer 30, the above-mentioned insulating layer 20 and the first conductive layer 30 can be directly used as a barrier layer, and then the insulating layer 20 and the first conductive layer 30 can be selectively etched to form a field plate structure without consuming a photomask, thereby simplifying The preparation process reduces the difficulty of the process and saves the cost of the process.

In some optional embodiments, as shown in FIG. 1 , the above-mentioned semiconductor substrate 10 further includes a body region 110 , a drift region 130 , a body region contact region 120 and a shallow trench isolation region 140 . The technical solutions adopted for preparing the above structures all adopt the conventional process flow in the prior art, so the related structures are not described in detail here.

Wherein, the above-mentioned semiconductor substrate 10 may be an elemental semiconductor material substrate (eg, a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (eg, a germanium-silicon substrate, etc.), or a silicon-on-insulator substrate (SOI) substrate, germanium-on-insulator (GeOI) substrate, etc.

In some optional embodiments of the present application, regarding the field plate structure in the above-mentioned power device, the insulating layer 20 constituting the field plate structure includes a high-k gate dielectric layer. Since the higher the relative permittivity of the material of the high-k gate dielectric layer, the greater the strength of the electric displacement vector here, which means that more potential lines generated by space charges in the depletion layer enter the high-k gate dielectric layer, and then Reduce the potential line concentrated at the edge of the gate 100 in the depletion layer, thereby weakening the electric field generated by the space charge in the depletion layer, reducing the electric field peak value at the gate edge, so that under the same applied voltage, the gate of the power device can The fringe peak electric field decreases, and the electric field distribution has almost no peak value, so the coverage area of the electric field curve increases, and the corresponding depletion layer area increases, while the critical breakdown voltage is a fixed value, and the breakdown voltage is the critical breakdown electric field versus depletion. The integral of the layer area, so the breakdown voltage increases accordingly.

Since the above-mentioned semiconductor substrate 10 is provided with the insulating layer 20, the breakdown voltage increases accordingly, and the increase in the breakdown voltage will in turn lead to an increase in the on-resistance of the power device. Therefore, in some optional embodiments, about For the field plate structure in the above power device, the material constituting the first conductive layer 30 of the field plate structure includes metal and/or polysilicon. By setting the conductive metal and/or polysilicon, it satisfies that it can be individually wired and designed to operate at an independent voltage. conditions, and reduce the layer resistance of the power device, thereby reducing the on-resistance.

In some optional embodiments, the material of the first conductive layer 30 includes doped polysilicon. By further doping the polysilicon, in the process of forming the field plate structure, the material loss for forming the field plate structure in the step of cleaning the natural oxide layer can be prevented.

In some optional implementations, due to the metal and/or polysilicon material used in the first conductive layer 30, the conductive conditions for forming an electrical connection are satisfied, so that separate wiring can be designed to operate at an independent voltage, which can further reduce conduction. resistance.

In some optional embodiments, the power device further includes: a first metal compound layer 40 , wherein the first metal compound layer 40 covers a side of the first conductive layer 30 away from the semiconductor substrate 10 . By forming the first metal compound layer 40 on the side of the first conductive layer 30 away from the semiconductor substrate 10, good ohmic contact can be provided, thereby reducing the layer resistance of each layer structure in the power device and increasing the operation of the power device speed.

In some optional embodiments, the material of the above-mentioned first conductive layer 30 includes metal, and further optionally, the above-mentioned metal is metal cobalt, and the above-mentioned metal cobalt can be used as a precursor for forming the above-mentioned metal compound layer, thereby simplifying the process steps , reduce production costs.

Because in some optional embodiments, the above-mentioned power device further includes: a second metal compound layer 50, the metal compound layer is arranged in contact with the source region 80 and the drain region 90 of the source/drain region and the gate electrode 100; a plurality of conductive The connection parts 60 , each conductive connection part 60 is disposed in contact with the second metal compound layer 50 , and each conductive connection part 60 extends in a direction away from the semiconductor substrate 10 . The second metal compound layer 50 is interconnected with the source terminal and the conductive connection part 60, which can more effectively adjust the electric field of the drain terminal; the above-mentioned plurality of conductive connection parts 60 play the role of conductive connection to ensure the electrical connection of the power device.

The first metal compound layer 40 and the second metal compound layer 50 may be the same metal compound layer or different metal compound layers; both the first metal compound layer 40 and the second metal compound layer 50 may be It is one or more of cobalt silicide, titanium silicide or nickel silicide; the above-mentioned conductive connection part 60 can be metal copper, metal tungsten, metal nickel and so on. Regarding the above-mentioned materials of the first metal compound layer 40 , the second metal compound and the conductive connection portion 60 , those skilled in the art can reasonably select materials according to the prior art, which are not specifically limited in this application.

In some optional embodiments, the power device further includes: a second conductive layer 70, the second conductive layer 70 is disposed on the side of the conductive connection portion 60 away from the second metal compound layer 50, and each conductive connection portion 60 The second metal compound layer 50 and the second conductive layer 70 are connected. The above-mentioned conductive connection portion 60 serves as a conductive member, and interconnects the second metal compound layer 50 and the second conductive layer 70 .

According to another aspect of the present application, there is also provided a method for fabricating a power device, the fabrication method comprising the steps of: providing a semiconductor substrate, the semiconductor substrate having a first side, and the first side having a source of source/drain regions A dielectric material is deposited on the first side to form an insulating layer, the insulating layer is arranged on the first side, and the insulating layer and the source and drain regions of the source/drain regions and the gate Electrode contact arrangement; a first conductive layer is formed on the side of the insulating layer away from the semiconductor substrate, and the first conductive layer covers the insulating layer.

Exemplary embodiments of the method for fabricating a power device provided according to the present invention will be described in more detail below. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art.

As shown in FIG. 2 , a semiconductor substrate 10 is first provided, the semiconductor substrate 10 has a first side, and the first side has a source region 80 , a drain region 90 and a gate 100 , wherein the source region 80 and the drain region 90 are On both sides of the first side, the gate 100 is located on the first side surface of the semiconductor substrate 10 between the source region 80 and the drain region 90 , and the gate 100 is close to the source region 80 .

In some optional embodiments, as shown in FIG. 2 , the above-mentioned semiconductor substrate 10 further includes a body region 110 , a drift region 130 , a body region contact region 120 and a shallow trench isolation region 140 . The body region 110 is disposed on the first side of the semiconductor substrate 10 in contact with the drift region 130 , the source region 80 is disposed in the body region 110 , the drain region 90 is disposed in the drift region 130 , and a portion of the gate 100 Located on the body region 110, another part of the gate 100 is located on the drift region 130, the body region 110 is also provided with a body region contact region 120 to form an ohmic contact, and a side of the drift region 130 away from the gate 100 is also provided with Shallow trench isolation region 140 . The technical solutions adopted for preparing the above structures all adopt the conventional process flow in the prior art, so the related structures are not described in detail here.

As shown in FIG. 3, a dielectric material is deposited on the first side to form an insulating layer 20, the insulating layer 20 is disposed on the first side, and the insulating layer 20 and the source region 80 and the drain region 90 of the source/drain regions And the above-mentioned gate 100 is arranged in contact with each other. By adding the above-mentioned insulating layer 20, part of the electric field lines are directed from the barrier layer to the field plate, thereby weakening the electric field generated by the space charge in the depletion layer, reducing the peak value of the electric field at the gate edge, thereby increasing the breakdown voltage of a power device.

In some optional embodiments, the above-mentioned dielectric material includes a high-k material. Since the high-k material has a relatively high relative permittivity, the electric displacement vector strength of the insulating layer 20 formed of the above-mentioned high-k material is correspondingly large, This means that more potential lines generated by space charges in the depletion layer enter the insulating layer 20, thereby reducing the potential lines concentrated in the depletion layer toward the edge of the gate 100, thereby weakening the electric field generated by the space charges in the depletion layer. , which reduces the peak electric field at the gate edge, so that under the same applied voltage, the peak electric field at the gate edge of the power device decreases, and there is almost no peak in the electric field distribution, so the coverage area of the electric field curve increases, and the corresponding depletion layer area increases. The critical breakdown voltage is a constant value, and the breakdown voltage is the integral of the critical breakdown electric field to the depletion layer region, so the breakdown voltage increases accordingly.

In some optional embodiments, after the insulating layer 20 is formed, a first conductive layer 30 is formed on the side of the insulating layer 20 away from the semiconductor substrate 10, and the first conductive layer 30 covers the insulating layer 20, as shown in FIG. 3 shown.

Wherein, the above-mentioned insulating layer 20 and the above-mentioned first conductive layer 30 may both be formed by chemical deposition process, self-alignment process, or the like.

In some optional embodiments, a chemical deposition process is used to form the insulating layer 20 covering the source region 80 and the drain region 90 of the source/drain region, the gate electrode 100, the drift region 130 and the shallow trench isolation region 140, and then the insulating layer 20 is formed. A first conductive layer 30 covering the above-mentioned insulating layer 20 is formed by a chemical deposition process, and then a mask plate is set on the side of the above-mentioned first conductive connection portion 60 away from the semiconductor substrate 10, and the above-mentioned insulating layer 20 and the above-mentioned first conductive layer are etched according to the mask plate. A conductive layer 30 such that the insulating layer 20 and the first conductive layer 30 expose the gate electrode 100 and the source and drain regions 80 and 90 in the source/drain regions.

In some optional embodiments, a self-aligned process is used to form and deposit a layer of SAB layer to completely cover the first side of the above-mentioned semiconductor substrate 10, wherein the above-mentioned SAB layer is an oxide layer, and then a self-aligned process is used to deposit The first conductive layer 30 covers the above-mentioned SAB layer, and then coats a layer of photoresist on the upper surface of the SAB layer, and then performs exposure and development processes by means of a mask plate with an exposure pattern, and then forms an opening pattern in the photoresist , and then use the remaining photoresist as an etching mask to perform dry etching downward, remove the first conductive layer 30 and the SAB layer located under the photoresist opening, and finally remove the remaining photoresist, forming as shown in the figure 2 shows the structure. In the above embodiment, the field plate structure is fabricated by using the self-alignment process and the SAB material, thereby reducing the complexity of the process, simplifying the process flow, and saving the fabrication cost.

In some optional embodiments, as shown in FIG. 4 , after the step of forming the above-mentioned first conductive layer 30 , the above-mentioned manufacturing method further includes: firstly forming a first metal compound layer 40 on the first side of the semiconductor substrate 10 , The first metal compound layer 40 covers the side of the first conductive layer 30 away from the semiconductor substrate 10 . By forming the above-mentioned first metal compound layer 40, good ohmic contact can be provided, thereby reducing the layer resistance of each layer structure in the power device, thereby reducing the on-resistance of the device, and increasing the operating speed of the power device.

In some optional embodiments, the material for forming the above-mentioned first conductive layer 30 includes polysilicon, and the step of forming the above-mentioned first metal compound layer 40 includes: depositing a metal layer on the first side of the above-mentioned semiconductor substrate 10, so that the above-mentioned The metal layer is in contact with the source and drain regions 80 and 90 of the source/drain regions and with the first conductive layer 30; the metal layer is reacted with polysilicon to form the first metal compound layer 40, since the metal compound has a lower resistance than the metal , which further reduces the on-resistance of the device.

In some optional embodiments, a metal layer is first deposited to cover the first conductive layer 30 and the source regions 80 and 90 in the source/drain regions. Any suitable metal for silicidation, including but not limited to Co, Ni, Ti, and the like.

In some optional embodiments, after the metal layer is deposited, a layer of titanium nitride (TiN) may also be deposited on the metal layer to form a polymer of the metal layer and titanium nitride, thereby effectively preventing the metal layer from being exposed due to oxidized in the air.

In some optional implementations, the above-mentioned metal layer is annealed, so that the deposited metal layer reacts with the polysilicon in contact, so that the contact region 120 in the body region, the source region 80 and the drain region 90 in the source/drain region The second metal compound layer 50 is formed on the surface of the gate 100 and the first conductive layer 30, and the first metal compound layer 40 and the second metal compound layer 50 are formed on the upper surface of the shallow trench isolation region 140, so that the above field plate structure can be Separate wiring and design for independent voltage operation, thereby reducing the on-resistance of the device. Finally, photolithography and etching processes are used to remove the redundant first metal compound layer 40, the first conductive layer 30 and the insulating layer 20, and remove The remaining photoresist forms the structure shown in FIG. 5 .

In some optional embodiments, after removing the redundant first metal compound layer 40, the first conductive layer 30 and the insulating layer 20 by etching, a dielectric layer (not shown in the figure) is deposited on the first side of the semiconductor substrate. marked), so that the dielectric layer covers the first side of the semiconductor substrate, and then the dielectric layer is etched to form a plurality of contact holes, so that the contact holes expose the source region 80 and the drain region in the source/drain regions 90, the second metal compound layer 50 on the surface of the gate 100, and the first metal compound layer 40 and the second metal compound layer 50 on the shallow trench isolation layer, and then filling each contact hole with metal (eg, copper) to The conductive connection part 60 is formed, and then the second conductive layer 70 is prepared, so that the second conductive layer 70 and the conductive connection part 60 are interconnected, and the electrical connection between the first metal compound layer 40 and the second conductive layer 70 is realized, as shown in FIG. 1 . shown structure.

From the above description, it can be seen that the above-mentioned embodiments of the present invention achieve the following technical effects:

1. By forming an insulating layer on the first side of the semiconductor substrate, the potential lines concentrated at the edge of the gate are reduced, and the breakdown voltage of the device is effectively improved. By forming a first conductive layer on the side of the insulating layer away from the semiconductor substrate, So that the first conductive layer can be wired separately and designed to operate independently of voltage, thereby reducing the on-resistance and effectively improving the performance of the power device;

2. The manufacturing method of the power device provided by the present invention reduces the complexity of the process and saves the manufacturing cost of the process.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A power device, comprising a semiconductor substrate and a field plate structure, wherein the field plate structure is disposed on a first side of the semiconductor substrate, and the first side of the semiconductor substrate has source/drain region and gate, the field plate structure includes: an insulating layer, the insulating layer is arranged on the first side, and the insulating layer is arranged in contact with the source/drain regions and the gate; a first conductive layer, the first conductive layer covers the side of the insulating layer away from the semiconductor substrate. 2 . The power device according to claim 1 , wherein the insulating layer comprises a high-k gate dielectric layer. 3 . 3. The power device according to claim 1, wherein the material of the first conductive layer comprises metal and/or polysilicon. 4. The power device according to claim 3, wherein the material of the first conductive layer comprises doped polysilicon. 5. The power device according to any one of claims 1 to 4, wherein the power device comprises: a first metal compound layer covering the side of the first conductive layer away from the semiconductor substrate. 6. The power device according to any one of claims 1 to 4, wherein the power device further comprises: a second metal compound layer disposed in contact with the source/drain regions and the gate electrode; A plurality of conductive connection parts, each of which is arranged in contact with the second metal compound layer, and extends in a direction away from the semiconductor substrate. 7. The power device according to claim 6, wherein the power device further comprises: A second conductive layer, the second conductive layer is disposed on the side of the conductive connection portion away from the second metal compound layer, and the conductive connection portion connects the second metal compound layer and the second conductive layer . 8. A method of making a power device, comprising the following steps: providing a semiconductor substrate having a first side having source/drain regions and a gate; A dielectric material is deposited on the first side to form an insulating layer, the insulating layer is disposed on the first side, and the insulating layer is disposed in contact with the source/drain regions and the gate electrode; A first conductive layer is formed on a side of the insulating layer away from the semiconductor substrate, and the first conductive layer covers the insulating layer. 9. The manufacturing method according to claim 8, wherein after the step of forming the first conductive layer, the manufacturing method further comprises: A first metal compound layer is formed on the first side, and the metal compound layer covers the side of the first conductive layer away from the semiconductor substrate. 10 . The manufacturing method according to claim 9 , wherein the material for forming the first conductive layer comprises polysilicon, and the step of forming the first metal compound layer comprises: 10 . depositing a metal layer on the first side so that the metal layer is in contact with the source/drain regions and the first conductive layer; The metal layer is reacted with the polysilicon to form the first metal compound layer.

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