CN111223932A

CN111223932A - A semiconductor device and method of forming the same

Info

Publication number: CN111223932A
Application number: CN201811420138.1A
Authority: CN
Inventors: 伏广才; 叶星
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2018-11-26
Filing date: 2018-11-26
Publication date: 2020-06-02
Anticipated expiration: 2038-11-26
Also published as: CN111223932B

Abstract

Embodiments of the present invention provide a semiconductor device and a method for forming the same. In an embodiment of the present invention, a portion of the doped region and a portion of the body region below are etched to form discrete first and second source regions and to isolate the first and second source regions and forming a pick-up region opposite to the doping type of the first source region and the second source region at the bottom of the second groove; forming a metal silicide on the sidewall and bottom surface of the second groove, so that the first source region and the second source region are respectively electrically connected to the pickup region. Thereby, the pickup capability of the body region of the semiconductor device can be improved.

Description

Semiconductor device and forming method thereof

Technical Field

The present invention relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for forming the same.

Background

Semiconductor devices are electronic devices that have electrical conductivity between a good electrical conductor and an insulator, and that use the special electrical properties of semiconductor materials to perform specific functions, and can be used to generate, control, receive, convert, amplify signals, and perform energy conversion. The conventional semiconductor device includes: field effect transistors, bipolar transistors, and diodes, among others. Of these, LDMOS (Laterally Diffused Metal Oxide Semiconductor) is widely used in power integrated circuits because it is more compatible with CMOS (Complementary Metal Oxide Semiconductor) logic processes. However, the pick-up capability of the body region of the existing semiconductor device is yet to be improved.

Disclosure of Invention

Embodiments of the present invention provide a semiconductor device and a method for forming the same to improve the pick-up capability of the semiconductor device.

According to an aspect of an embodiment of the present invention, there is provided a method of forming a semiconductor device, the method including:

providing a semiconductor substrate, wherein a body region, a first drift region and a second drift region which are positioned at two sides of the body region, a gate structure layer positioned on the body region and a barrier layer covering the gate structure layer are formed in the semiconductor substrate, a first drain region is formed in the first drift region, and a second drain region is formed in the second drift region;

etching the barrier layer and the gate structure layer in a preset area to form a first groove exposing the body area and a first gate structure and a second gate structure which are separated by the first groove;

performing ion implantation on the body region exposed in the first groove, and forming a doped region in the body region, wherein the doped region has a first doping type;

etching part of the doped region and part of the body region below the doped region to form a first source region and a second source region which are separated and a second groove for isolating the first source region and the second source region;

performing ion implantation on the bottom of the second groove, and forming a pickup area with a second doping type at the bottom of the second groove;

patterning the barrier layer;

and forming a metal silicide through a self-alignment process, wherein the metal silicide at least covers the side wall and the bottom surface of the second groove so that the first source region and the second source region are respectively electrically connected with the pickup region.

Further, the patterning the barrier layer includes: etching the barrier layer above the first gate structure and the second gate structure to form a plurality of holes exposing the first gate structure and a plurality of holes exposing the second gate structure;

the metal silicide formed by the self-aligned process also covers the bottom of the hole.

Further, the patterning the barrier layer further comprises: etching the barrier layer above the first drain region and the second drain region to expose the first drain region and the second drain region;

and the metal silicide formed by the self-alignment process also covers the first drain region and the second drain region.

Further, the method further comprises:

and forming a floating gate on the barrier layer.

Further, the method further comprises:

forming contact holes respectively connecting the first drain region, the second drain region, the first gate structure, the second gate structure and the pickup region while forming the floating gate;

and forming an interconnection structure above the contact hole so that the first drain region and the second drain region form an electrical connection.

Further, the method further comprises: before forming the second groove, a first side wall covering the side wall of the first grid structure and part of the doped region and a second side wall covering the side wall of the second grid structure and part of the doped region are formed.

Further, the first source region is located below the first side wall, the second source region is located below the second side wall, and the second groove is located between the first side wall and the second side wall.

Further, the first drift region and the second drift region have a first doping type, and the body region has a second doping type.

According to another aspect of embodiments of the present invention, there is provided a semiconductor device including:

the semiconductor device comprises a semiconductor substrate, a first drift region and a second drift region, wherein the semiconductor substrate is provided with a body region, and the first drift region and the second drift region are positioned on two sides of the body region;

a first gate structure covering a portion of the first drift region;

a second gate structure covering a portion of the second drift region;

the semiconductor device comprises a body region, a first source region and a second source region, wherein the body region is provided with a first doping type;

and a recess is formed in the body region, the recess separates a first source region and a second source region, a pickup region is formed at the bottom of the recess, the pickup region has a second doping type, and metal silicide is formed on the side wall of the recess and the surface of the pickup region, so that the first source region and the second source region are respectively electrically connected with the pickup region.

Further, the semiconductor device further comprises a barrier layer;

the blocking layer covers the first gate structure and the first drift region, and covers the second gate structure and the second drift region;

and a plurality of holes exposing the first gate structure are formed in the barrier layer above the first gate structure, a plurality of holes exposing the second gate structure are formed in the barrier layer above the second gate structure, and metal silicide is formed in the holes.

Further, the semiconductor device further includes:

a floating gate formed over the barrier layer;

contact holes respectively connected with the first drain region, the second drain region, the first gate structure, the second gate structure and the pickup region;

an interconnection structure formed over the contact hole to electrically connect the first drain region and the second drain region.

Further, a metal silicide is formed on the first drain region and the second drain region.

Further, the semiconductor device further includes:

the first side wall covers the side wall of the first grid structure and the first source region;

and the second side wall covers the side wall of the second grid structure and the second source region.

Further, the recess is located between the first side wall and the second side wall.

In the embodiment of the invention, a part of the doped region and a part of the body region below the doped region are etched to form a first source region and a second source region which are separated and a second groove for isolating the first source region and the second source region; forming a pickup region with the doping type opposite to that of the first source region and the second source region at the bottom of the second groove; and forming metal silicide on the side wall and the bottom surface of the second groove so that the first source region and the second source region are respectively electrically connected with the pickup region. Thereby, the pick-up capability of the body region of the semiconductor device can be improved.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 is a schematic sectional view of a semiconductor device of a comparative example;

fig. 2 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention;

fig. 3-14 are schematic views of structures formed at various steps of a method of forming a semiconductor device according to an embodiment of the present invention;

fig. 15 is a schematic cross-sectional view of a semiconductor device of an embodiment of the present invention.

Detailed Description

The present invention will be described below based on examples, but the present invention is not limited to only these examples. In the following detailed description of the present invention, certain specific details are set forth. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. Well-known methods, procedures, components and circuits have not been described in detail so as not to obscure the present invention.

Further, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless the context clearly requires otherwise, throughout the description and the claims, the words "comprise", "comprising", and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense; that is, what is meant is "including, but not limited to". In the description of the present invention, "multi-layer" means two or more layers unless otherwise specified.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Spatial relationship terms such as "below …", "below", "lower", "above …", "above", and the like may be used herein for ease of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device may assume other orientations (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly.

The "sidewall" is a surface other than the top surface and the bottom surface, and for example, the "sidewall covering the gate structure layer" means a front surface, a back surface, a left side surface and a right side surface of the gate structure layer.

Fig. 1 is a schematic sectional view of a semiconductor device of a comparative example. As shown in fig. 1, the semiconductor device of the comparative example includes: the semiconductor substrate 100 ', the first gate structure 31 ', the second gate structure 32 ', the doping region 70 ', the first isolation wall 81 ', the second isolation wall 82 ', the barrier layer 40 ', the metal silicide 90 ' and the contact hole 120 '.

The semiconductor substrate 100 'has a body region 10', a first drift region 21 'and a second drift region 22' formed therein and located on both sides of the body region. Wherein, a first drain region 51 'is formed in the first drift region 21', and a second drain region 52 'is formed in the second drift region 22'. The first gate structure 31 'covers a portion of the first drift region 21'. The second gate structure 32 'covers a portion of the second drift region 22'.

The doped region 70 'is formed in the body region 10'. The first isolation wall 81 'covers sidewalls of the first gate structure 31'. The second isolation wall 82 'covers sidewalls of the second gate structure 32'.

The barrier layer 40 'covers a part of the first gate structure 31' and its sidewalls, and extends to the first drift region 21 'at one side of the first gate structure 31'; and a second drift region 22 ' covering a portion of the second gate structure 32 ' and its sidewalls and extending to one side of the second gate structure 32 '.

A metal silicide 90 ' and a contact hole 120 ' for connecting the first drain region 51 ', the second drain region 52 ', the first gate structure 31 ', the second gate structure 32 ' and the doped region 70 ' of the semiconductor device.

In the comparative example, the pick-up capability of the doped region 70 'in the body region 10' is not high. Meanwhile, defects are easily formed due to over-etching during the formation of the semiconductor device, and the defects are mainly formed on the side of the first gate structure 31 'close to the body region 10' and on the side of the second gate structure 32 'close to the body region 10', thereby causing the semiconductor device to fail.

Fig. 2 is a flowchart of a method of forming a semiconductor device of an embodiment of the present invention, and referring to fig. 2, the method of forming the embodiment of the present invention includes the steps of:

step S100, providing a semiconductor substrate. The semiconductor substrate is provided with a body region, a first drift region and a second drift region which are positioned on two sides of the body region, a gate structure layer positioned on the body region and a blocking layer covering the gate structure layer, wherein the first drift region is provided with a first drain region, and the second drift region is provided with a second drain region.

Step S200, etching the barrier layer and the gate structure layer in a preset area to form a first groove exposing the body area and a first gate structure and a second gate structure which are separated by the first groove.

Step 300, performing ion implantation on the body region exposed in the first groove, and forming a doped region in the body region. The doped region has a first doping type.

Step S400, etching part of the doped region and part of the body region to form a first source region and a second source region which are separated and a second groove for isolating the first source region and the second source region.

Step S500, performing ion implantation on the bottom of the second groove to form a pickup region having a second doping type at the bottom of the second groove.

And step S600, patterning the barrier layer.

Step S700, forming a metal silicide by a self-aligned process. The metal silicide at least covers the side wall and the bottom surface of the second groove so that the first source region and the second source region are respectively electrically connected with the pickup region.

Preferably, the forming method further includes:

step S800, Contact (CT) is formed.

And step S900, forming an interconnection structure on the upper layer of the contact hole.

Fig. 3-14 are schematic views of structures formed at various steps of a method of forming a semiconductor device according to an embodiment of the present invention. The formation of the LDMOS is illustrated in fig. 3-14 as an example. It should be understood that the formation steps of the embodiments of the present invention may also be used to form other semiconductor devices where a pick-up region is desired. Fig. 3 is a schematic view of a semiconductor substrate, and referring to fig. 3, in step S100, a semiconductor substrate 100 is provided, in which a body region 10 is formed in the semiconductor substrate 100, a first drift region 21 and a second drift region 22 located at two sides of the body region 10, a gate structure layer 30 located on the body region, and a barrier layer 40 covering the gate structure layer 30, wherein a first drain region 51 is formed in the first drift region 21, and a second drain region 52 is formed in the second drift region 22.

In an alternative implementation manner, when the LDMOS is formed as a P-type LDMOS, P-type impurity ions are doped in the first drift region 21 and the second drift region 22, P-type impurity ions are doped in the first drain region 51 and the second drain region 52, N-type impurity ions are doped in the body region 10, and P-type impurity ions are doped in the first source region 71 and the second source region 72. The pickup region 83 is doped with N-type impurity ions. In another alternative implementation manner, when the LDMOS is formed as an N-type LDMOS, the first drift region 21 and the second drift region 22 are doped with N-type impurity ions, the first drain region 51 and the second drain region 52 are doped with N-type impurity ions, the body region 10 is doped with P-type impurity ions, the pickup region 83 is doped with N-type impurity ions, and the first source region 71 and the second source region 72 are doped with N-type impurity ions. The N-type impurity ions are one or more of phosphorus (P) ions, arsenic (As) ions and antimony (Te) ions; the P-type impurity ions are one or more of boron (B) ions, indium (In) ions and gallium (Ga) ions.

The semiconductor substrate 100 provided in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 100 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-stacked-germanium (S-SiGeOI), a silicon-on-insulator-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. The semiconductor substrate may further include other materials, such as a multi-layer structure of epitaxial layers or buried layers, and several epitaxial interface layers or strained layers may be formed on the surface of the semiconductor substrate to improve the electrical performance of the semiconductor device.

The body region 10, the first drift region 21 and the second drift region 22 in the semiconductor 100 are formed by an ion implantation process. The first drift region 21 and the second drift region 22 have a low doping concentration and a high resistance, and can withstand a higher voltage. Meanwhile, the first drift region 21 and the second drift region 22 play a role in buffering between the gate and the drain region, and the short channel effect of the LDMOS is weakened.

More specifically, the process of forming the first drift region 21 and the second drift region 22 includes: before the first drift region 21 and the second drift region 22 are formed, a mask layer is formed on the semiconductor substrate 100, the mask layer exposes a region to be implanted, and corresponding ion implantation is performed on the region to be implanted.

The process of forming the body region 10 may include: before forming the body region 10, a mask layer is formed on the semiconductor substrate 100, the mask layer exposes a region to be implanted, and corresponding ion implantation is performed on the region to be implanted.

The gate structure layer 30 covers the body region 10 and the first drift region 21 and the second drift region 22 adjacent to the body region 10, and the gate structure layer 30 includes a gate dielectric layer 301 and a gate electrode layer 302 on the gate dielectric layer 301.

Alternatively, the material of the gate dielectric layer 301 may be silicon dioxide (SiO)₂) Or high-K dielectric materials, e.g. zirconium oxide (ZrO)₂)、Alumina (Al)₂O₃) Or hafnium oxide (HfO)₂) And the like. Preferably, the gate dielectric layer 21 may include a stacked silicon oxide layer and a high-K dielectric material layer. The material of the gate electrode layer 302 may be polysilicon or a metal such as tungsten (W), copper (Cu), aluminum (Al), or the like.

Preferably, a protection wall (not shown) is formed around the gate structure layer 30 to cover a sidewall of the gate structure layer 30. The protective wall can protect the side wall of the gate structure layer 30 from being damaged in the subsequent drain region ion implantation process, and can isolate the first gate structure and the first drain region formed in the subsequent process, and isolate the second gate structure and the second drain region, so as to avoid short circuit.

The first drain region 51 is formed in the first drift region 21 not covered by the gate structure layer, the second drain region 52 is formed in the second drift region 22 not covered by the gate structure layer, and the first drain region 51 and the second drain region 52 may be formed by ion implantation.

The barrier layer 40 covers the gate structure layer 30, and the material of the barrier layer 40 may be silicon dioxide (SiO)₂) Silicon nitride (Si)₃N₄) Silicon Rich Silicon Oxide (SRO), Silicon oxynitride (SiON), and the like, preferably Silicon Rich Silicon Oxide and Silicon nitride (Si) stacked in this order₃N₄). Since silicon-rich silicon dioxide is to silicon dioxide (SiO)₂) Has higher extinction coefficient, thereby avoiding the influence on other structures in the subsequent dry etching process, and the silicon nitride (Si)₃N₄) Has good compactness and can play an isolation role in the subsequent etching process.

As shown in fig. 4, in an alternative implementation, a Buried Layer (Buried Layer)101, a reverse ion implantation Layer 102, a first medium voltage well region 103, a second medium voltage well region 104, and a shallow trench isolation structure 107 are further formed in the semiconductor substrate 100.

The material of the buried layer 101 is typically silicon dioxide (SiO)₂) The thickness is about 100nm to 1 μm, and thus the Buried layer 101 is also called a Buried Oxide (BOX). Buried layer 101 can prevent unwanted electronsSeeps to the underlying semiconductor substrate 100.

The reverse ion implantation layer 102 is located below the body region 10, the first drift region 21, and the second drift region 22, and is connected to the body region 10, the first drift region 21, and the second drift region 22. The doping type of the reverse ion implantation layer 102 is opposite to the doping type of the first drift region 21 and the second drift region 22. Therefore, a PN junction is formed between the first drift region 21 and the second drift region 22 of the reverse ion implantation layer 102, and the PN junction can suppress leakage current.

The first intermediate voltage well region 103 is located on the side of the first drift region 21 and the reverse ion implantation layer 102, and on the side of the second drift region 22 and the reverse ion implantation layer 102. The doping type of the medium voltage well region 103 is the same as that of the reverse ion implantation layer 102. The middle voltage well region 103 can prevent a leakage current from entering the semiconductor substrate 100.

The first medium voltage well region 103 is used for connection of a control potential for controlling the potential of the medium voltage well region 103, thereby further enhancing the ability to prevent a current from flowing into the semiconductor substrate 100.

The second medium voltage well region 104 is located on the side of the first medium voltage well region 103, and a gap is formed between the first well region 103 and the second well region 104 to form a discontinuous well region, so that the source-drain breakdown voltage of the device is improved, and the performance of the device is further improved.

The second medium voltage well region 104 is used for connecting a control potential for controlling the potential of the medium voltage well region 104, thereby further enhancing the ability to prevent current from flowing into the semiconductor substrate 100.

A first ohmic contact region 105 is formed on the surface of the first medium voltage well region 103, and a second ohmic contact region 106 is formed on the surface of the second medium voltage well region 104. The first ohmic contact region 105 and the second ohmic contact region 106 may function to reduce contact resistance.

Shallow trench isolation structures 107 are formed in regions of the first medium voltage well region 103 adjacent to the first drift region 21, and shallow trench isolation structures 107 are formed in regions of the first medium voltage well region 103 adjacent to the second drift region 22. The shallow trench isolation structure 107 may enhance the insulating effect of the first medium voltage well region 103 and the adjacent region of the first drift region 21, and the insulating effect of the first medium voltage well region 103 and the adjacent region of the second drift region 22.

Referring to fig. 5, in step S200, the barrier layer 40 and the gate structure layer 30 are etched in a predetermined region. To form a first recess 60 exposing the body region 10 and a first gate structure 31 and a second gate structure 32 separated by the first recess 60. The first gate structure 31 includes a first gate dielectric layer 311 and a first gate electrode layer 312 on the first gate dielectric layer 311. The second gate structure 32 includes a second gate dielectric layer 321 and a second gate electrode layer 322 on the second gate dielectric layer 321.

Specifically, photoresist is uniformly coated on the surface of a semiconductor substrate, the photoresist is patterned to form a mask layer with an opening pattern in a predetermined area, the predetermined area which is not covered by the photoresist is etched to expose a body area, a first gate structure 31 and a second gate structure 32 which are separated are formed, and finally the photoresist is removed.

The etching process may be selected from etching methods known to those skilled in the art, such as dry etching, wet etching, and the like. Preferably, dry etching is used to etch the barrier layer 40 and the gate structure layer 30 in a predetermined region, the dry etching may select an etching gas according to a selected material, and CHF may be selected₃，SF₆，CF₄，CF₄/O₂And CF₄/H₂Etc. as an etching gas. In embodiments of the present invention, CHF is preferably used₃As the etching gas, the etching pressure can be 5-300 mTorr, and preferably 8-10 mTorr.

By etching the gate structure layer 30, the first gate structure 31 and the second gate structure 32 can be formed simultaneously in one step, so that the process flow can be saved, and the production efficiency can be improved.

Referring to fig. 6, in step S300, ion implantation is performed on the body region 10 exposed in the first recess 60, and a doped region 70 is formed in the body region 10. The doped region 70 has a first doping type.

In an alternative implementation, the implantation of the ion implantationWhen the impurity ions are one or more of phosphorus (P) ions, arsenic (As) ions and antimony (Te) ions, the implantation angle of the ion implantation is 0-5 DEG, and the implantation dosage is 5E13atom/cm²～5E15atom/cm²The implantation energy is 6Kev to 50 Kev. In another optional implementation manner, when the impurity ions implanted by the ion implantation are one or more of boron (B) ions, indium (In) ions and gallium (Ga) ions, the implantation angle of the ion implantation is 0-5 degrees, and the implantation dose is 5E13atom/cm²～5E15atom/cm²The implantation energy is 12Kev to 50 Kev.

It should be understood that the process parameters of the ion implantation are not limited to the above process parameters, and may be adjusted according to different equipment and different structure and performance requirements of the semiconductor device.

Referring to fig. 7, in step S400, a portion of the doped region 70 and a portion of the body region 10 are etched to form a first source region 71 and a second source region 72 which are separated and a second groove 80 which isolates the first source region from the second source region.

The doped regions 70 may be etched by applying a photoresist, then patterning the photoresist to form a mask layer having an opening pattern in a predetermined region, and then etching the predetermined region not covered by the photoresist to an etch depth extending into the body region 10, thereby etching a portion of the body region 10.

In a preferred implementation manner, referring to fig. 8 and 9, before etching the doped region 70, a first sidewall 81 and a second sidewall 82 covering an inner wall of the first groove may be formed in advance, where the forming process of the first sidewall 81 and the second sidewall 82 includes:

s410, as shown in FIG. 8, a side wall material layer (not marked in the figure) is deposited. The sidewall spacer material layer covers the barrier layer 40 and the sidewalls of the first recess 60.

S420, etching the predetermined region of the spacer material layer to form the first and

second sidewalls

81 and 82 as shown in fig. 9.

Specifically, the first side wall 81 covers a side surface of the first gate structure 31, and the second side wall 82 covers a side surface of the second gate structure 32. The first side wall 81 and the second side wall 82 may be made of materialsSelecting silicon nitride (Si)₃N₄). The first and

second sidewalls

81 and 82 protect the first and

second gate structures

31 and 32 in a subsequent ion implantation process.

Preferably, the first sidewall 81 covers the side of the first gate structure 31 and extends to the side of the barrier layer 40, and the second sidewall 82 covers the side of the second gate structure 32 and extends to the side of the barrier layer 40, so that the first gate structure 31 and the second gate structure 32 can be better protected in the subsequent patterning of the barrier layer 40.

Referring to fig. 10, in step S500, ion implantation is performed on the bottom of the second groove 80 to form a pickup region 83 having a second doping type at the bottom of the second groove 80. The pick-up region 83 has an opposite doping type to the first source region 71 and the second source region 72. The doping type of the pickup region 83 is the same as that of the body region 10, and the doping concentration of the pickup region 83 is greater than that of the body region 10.

Referring to fig. 11 and 12, fig. 12 is a top view of the semiconductor structure shown in fig. 11. In step S600, the barrier layer 40 is patterned. The first drain region 51 and the second drain region 52 are exposed. In an alternative implementation, the patterned barrier layer 40 covers a portion of the first gate structure 31 and extends to the first drift region 21, and covers a portion of the second gate structure 32 and extends to the second drift region 22.

Specifically, patterning the barrier layer 40 includes: the method comprises the steps of uniformly coating photoresist on the surface of a semiconductor substrate, patterning the photoresist to form a mask layer with an opening pattern in a preset area, etching the preset area which is not covered by the photoresist, and finally removing the photoresist. Preferably, the etched barrier layer exposes the first drain region 51 and the second drain region 52. Meanwhile, a hole 41 exposing the first and

second gate structures

31 and 32 is formed in the barrier layer 40 above the first and

second gate structures

31 and 32. It is further preferred that the etched barrier layer 40 also exposes the first and second

ohmic contact regions

105, 106.

The holes 41 allow the gate structure to be electrically connected to the contact holes during the subsequent formation of the contact holes. The hole 41 is formed above the gate structure instead of forming the groove structure, so that the problem that the edge of the gate structure is damaged by over-etching in the etching process, short circuit and the like are caused can be avoided, and the yield of the semiconductor device is reduced.

Referring to fig. 13, in step S700, a metal silicide 90 is formed by a self-aligned process. The metal silicide 90 covers at least the sidewalls and the bottom surface of the second recess 80 such that the first source region 71 and the second source region 72 are electrically connected to the pickup region 83, respectively. Preferably, the metal silicide 90 also covers the first source region 71, the first drain region 51, the first gate structure 31, the second source region 72, the second drain region 51, the second gate structure 32, the first well region 103, and the second well region 104.

The metal silicide 90 can reduce contact resistance between the contact holes formed subsequently and the first source region 71, the first drain region 51, the first gate structure 31, the second source region 72, the second drain region 51, the second gate structure 32, the first well 103 and the second well 104.

The Salicide formation process (Salicide) includes the following steps: first a metal layer, such as a material of nickel (Ni), cobalt (Co), titanium (Ti) and platinum (Pt) or a combination thereof, is deposited, preferably cobalt (Co). An Annealing process, preferably a Rapid Thermal Annealing (RTA) process, is performed to react the deposited metal layer with the silicon to form the metal silicide 90. Finally, removing the redundant metal. In the self-aligned process, the barrier Layer 40 may function as a metal silicide Block Layer (SAB) without forming a metal silicide.

A metal silicide is formed on the sidewalls and bottom of the second recess 80 so that the first and

second source regions

71 and 72 are electrically connected to the pickup region 83, respectively. Therefore, only a contact hole connected with the pickup region 83 needs to be formed, so that the drain regions of the two LDMOS transistors can be electrically connected with an external device through the contact hole, namely, the two LDMOS transistors share one drain electrode, and the size of the LDMOS transistors can be reduced. A PN junction is formed between the first source region 71 and the pickup region 83, and reverse breakdown is not formed, which can contribute to uniform current conduction and effectively achieve better performance.

In some comparative examples, the pickup region is located between the first source region and the second source region, adjacent to the first source region and the second source region, without forming the second recess, defects are easily formed during ion implantation, such as a problem that contact resistance between adjacent first source regions and pickup regions may be excessively large. In this embodiment, the pickup region is located at the bottom of the second groove and is lower than the first source region and the second source region, the pickup region is isolated from the first source region and the second source region in the forming process, a metal silicide is formed in the second groove, and the first source region, the second source region and the pickup region are electrically connected through the metal silicide, so that a good electrical contact between the pickup region and the first source region and the second source region can be ensured, and the problem of overlarge contact resistance can be avoided.

Referring to fig. 14, in step S800, the contact hole 120 is formed. The process of forming the contact hole 120 includes:

step S810, forming a dielectric layer 110 covering the semiconductor structure formed in step S700.

Step S820, patterning the dielectric layer 110, and forming through holes exposing the metal silicide on the surfaces of the pickup region 83, the first drain region 51, the first gate structure 31, the second drain region 51, the second gate structure 32, the first well region 103, and the second well region 104 in the dielectric layer 110.

Step S830, forming a conductive material in the via.

In an alternative implementation, a dielectric layer 110 is formed to cover the semiconductor substrate 100, the dielectric layer 110 is patterned, and a contact hole 120 is formed in the dielectric layer 110 to connect the pickup region 83, the first drain region 51, the first gate structure 31, the second drain region 51, the second gate structure 32, the first well region 103, and the second well region 104.

The contact hole 120 is used to connect a subsequently formed interconnection structure with the pickup region 83, the first drain region 51, the first gate structure 31, the second drain region 51, the second gate structure 32, the first well region 103 and the second well region 104, so that the interconnection structure is electrically connected with the first source region 71, the first drain region 51, the first gate structure 31, the second source region 72, the second drain region 51, the second gate structure 32, the first well region 103 and the second well region 104 through the contact hole 120.

Further preferably, at the same time of patterning the dielectric layer in step S820 of forming the contact hole 120, a hole exposing the barrier layer 40 is also formed in the dielectric layer 110; the step S830 of forming the contact hole 120 deposits a metal in the hole exposing the barrier layer 40 while depositing a conductive material in the hole to form the floating gate 130.

The floating gate 130 can make the electric field distribution uniform, adjust the transverse electric field of the LDMOS transistor device and improve the withstand voltage of the semiconductor device.

The material of dielectric layer 110 may be silicon oxide, silicon oxynitride, or silicon oxycarbide, preferably silicon oxide. The dielectric layer 110 may be formed by a Chemical Vapor Deposition (CVD) method commonly used in the art, such as Low Temperature Chemical Vapor Deposition (LTCVD), Plasma Chemical Vapor Deposition (PCVD), Low Pressure Chemical Vapor Deposition (LPCVD), Rapid Thermal Chemical Vapor Deposition (RTCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).

The patterned dielectric layer 110 may be formed by dry etching or wet etching, so as to form through holes exposing the metal silicide on the surfaces of the first source region 71, the first drain region 51, the first gate structure 31, the second source region 72, the second drain region 51, the second gate structure 32, the first well region 103, and the second well region 104.

The conductive material may be copper (Cu), aluminum (Al), or the like with high conductivity. The process for depositing metal in the through hole can be selected from chemical vapor deposition methods commonly used in the art, such as low temperature chemical vapor deposition, plasma chemical vapor deposition process, low pressure chemical vapor deposition, rapid thermal chemical vapor deposition, plasma enhanced chemical vapor deposition, and the like.

In step S900, an interconnect structure (not shown) of an upper layer of the contact hole 120 is formed. The forming process of the interconnection structure comprises the following steps:

and S910, forming an isolation layer covering the dielectric layer 110.

And S920, forming a patterned photoresist layer on the upper surface of the isolation layer. To expose the isolation layer of the portion to be etched.

S930, etching the isolation layer to form a patterned groove structure.

And S940, forming a conductive material in the groove structure. To form an interconnect structure connected to the contact hole 120.

The conductive material forming the interconnection structure may be a metal material such as copper (Cu) or aluminum (Al) with high conductivity.

The interconnection structure electrically connects the first drain region 51 and the second drain region 52, and electrically connects the first source region 71, the first drain region 51, the first gate structure 31, the second source region 72, the second drain region 51, the second gate structure 32, the floating gate 130, the first well region 103, the second well region 104, and the like, to an external device.

The embodiment of the present invention electrically connects the first drain region 51 and the second drain region 52 through an interconnection structure; meanwhile, the first gate structure 31 and the second gate structure 32 are electrically connected; in addition, the drain regions of the two LDMOS transistors are electrically connected to the pickup region at the same time, which corresponds to two LDMOS transistors sharing one drain. Therefore, two LDMOS transistors can be connected in parallel, and the breakdown voltage can be further improved.

According to another embodiment of the present invention, there is also provided a semiconductor device including: a semiconductor substrate 100, a first gate structure 31, a second gate structure 32, a first source region 71 and a second source region 72.

A body region 10a, a first drift region 21a and a second drift region 22a located at two sides of the body region 10a are formed in the semiconductor substrate 100a, wherein a first drain region 51a is formed in the first drift region 21a, and a second drain region 52a is formed in the second drift region 22 a.

The first gate structure 31a covers a part of the first drift region 21 a; the second gate structure 32a covers a portion of the second drift region 22 a.

The first source region 71a and the second source region 72a are formed in the body region 10a and are spaced apart from each other, and the first source region 71a and the second source region 72a have a first doping type. A recess 160a is formed in the body region 10a, the recess 160a separates the first source region 71a and the second source region 72a, a pickup region 83a is formed at the bottom of the recess, the pickup region 83a has the second doping type, and a metal silicide 90a is formed on the sidewall of the recess 160a and the surface of the pickup region 83a, so that the first source region 71a and the second source region 72a are electrically connected to the pickup region 83a, respectively.

As shown in fig. 15, in a preferred embodiment, the semiconductor device further includes: barrier layer 40a, floating gate 130a, contact hole 120a, interconnect structure (not shown), first sidewall 81a, and second sidewall 82 a.

A body region 10a, a first drift region 21a and a second drift region 22a located at two sides of the body region 10a are formed in the semiconductor substrate 100a, wherein a first drain region 51a is formed in the first drift region 21a, and a second drain region 52a is formed in the second drift region 22 a; wherein a recess 160a is formed in the body region 10a, the recess 160a separates the first source region 81a and the second source region 82a, a pickup region 83a is formed at the bottom of the recess 160a, the pickup region 83a has the second doping type, and a metal silicide is formed on the sidewall of the recess 160a and the surface of the pickup region 83a, so that the first source region 71a and the second source region 72a are electrically connected to the pickup region 83a, respectively.

The semiconductor substrate 100a may be a silicon single crystal substrate, a germanium single crystal substrate, or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 100a may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator-stacked-germanium (S-SiGeOI), a silicon-on-insulator-germanium (SiGeOI), a germanium-on-insulator (GeOI), a substrate of an epitaxial layer structure on silicon, or a compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. The semiconductor substrate may further include other materials, such as a multi-layer structure of epitaxial layers or buried layers, and several epitaxial interface layers or strained layers may be formed on the surface of the semiconductor substrate to improve the electrical performance of the semiconductor device.

Preferably, the semiconductor substrate 100a further has a buried layer 101a, an inverse ion implantation layer 102a, a first medium voltage well 103a, a second medium voltage well 104a, and a shallow trench isolation structure 107a formed therein.

The material of buried layer 101a is typically silicon oxide, with a thickness of about 100nm to 1 μm, and hence buried layer 101a is also referred to as a buried oxide layer. The buried layer 101a can prevent unwanted electrons from leaking onto the underlying semiconductor substrate 100 a.

The reverse ion implantation layer 102a is located below the body region 10a, the first drift region 21a, and the second drift region 22a, and is connected to the body region 10a, the first drift region 21a, and the second drift region 22 a. The doping type of the reverse ion implantation layer 102a is opposite to the doping type of the first drift region 21a and the second drift region 22 a. Therefore, a PN junction is formed between the first drift region 21a and the second drift region 22a of the reverse ion implantation layer 102a, and the PN junction can suppress leakage current.

The first medium voltage well region 103a is located at the side of the first drift region 21a and the reverse ion implantation layer 102a, and the side of the second drift region 22a and the reverse ion implantation layer 102 a. The doping type of the medium voltage well region 103 is the same as that of the reverse ion implantation layer 102 a. The middle voltage well region 103a can prevent a leakage current from entering the semiconductor substrate 100 a.

The first intermediate voltage well region 103a is used for connection of a control potential for controlling the potential of the intermediate voltage well region 103a, thereby further enhancing the ability to prevent a current from flowing into the semiconductor substrate 100 a.

The second medium voltage well region 104a is located on the side of the first medium voltage well region 103a, and a gap is provided between the first well region 103a and the second well region 104a to make them discontinuous, so as to improve the source-drain breakdown voltage of the device and further improve the performance of the device.

The second middle voltage well region 104a is used for connecting a control potential for controlling the potential of the middle voltage well region 104a, thereby further enhancing the ability to prevent a current from flowing into the semiconductor substrate 100 a.

A first ohmic contact region 105a is formed on a surface of the first intermediate voltage well region 103a, and a second ohmic contact region 106a is formed on a surface of the second intermediate voltage well region 104 a. The first ohmic contact region 105a and the second ohmic contact region 106a may function to reduce contact resistance.

Shallow trench isolation structures 107 are formed in regions of the first medium voltage well region 103a adjacent to the first drift region 21a, and shallow trench isolation structures 107 are formed in regions of the first medium voltage well region 103a adjacent to the second drift region 22 a. The shallow trench isolation structure 107 may enhance the insulating effect of the first medium voltage well region 103a and the adjacent region of the first drift region 21a, and the insulating effect of the first medium voltage well region 103a and the adjacent region of the second drift region 22 a.

The first gate structure 31a covers a portion of the first drift region 21 a. The first gate structure 31a includes a first gate dielectric layer 311a and a first gate electrode layer 312a on the first gate dielectric layer 311 a.

The second gate structure 32a covers a portion of the second drift region 22 a. The second gate structure 32a includes a second gate dielectric layer 321a and a first gate electrode layer 322a over the second gate dielectric layer 321 a.

The first source region 81a and the second source region 82a are formed in the body region 10a and are spaced apart from each other, and the first source region 81a and the second source region 82a have a first doping type.

A barrier layer 40a, said barrier layer 40a covering the first gate structure 31a and said first drift region 21a, and covering the second gate structure 32a and said second drift region 22 a. Preferably, a plurality of holes 41a exposing the first gate structure are formed in the barrier layer 40a above the first gate structure, a plurality of holes 41a exposing the second gate structure are formed in the barrier layer 40a above the second gate structure, and a metal silicide is formed in the holes 41 a.

The first side wall covers the first grid structure side wall and the first source region. The second side wall covers the second grid structure side wall and the second source region. The recess is located between the first side wall and the second side wall.

The material of the first sidewall 81a and the second sidewall 82a may be silicon nitride (Si)₃N₄). The first side wall 81a plays a role in protecting the first gate structure 31a during a process of forming a semiconductor substrate. The second side wall 82a plays a role in protecting the second gate structure 32a during a process of forming a semiconductor substrate.

The floating gate 130a is formed over the blocking layer 40a, and preferably, the floating gate 130a is formed over the blocking layer 40a covering the first drift region 21a or the second drift region 22 a. The floating gate can make the electric field distribution uniform, adjust the transverse electric field of the LDMOS transistor device and improve the withstand voltage of the device.

The contact holes 120a connect the first drain region 51a, the second drain region 52a, the first gate structure 31a, the second gate structure 32a, and the pickup region 83a, respectively. To electrically connect the first drain region 51a, the second drain region 52a, the first gate structure 31a, the second gate structure 32a, and the pickup region 83a with a subsequently formed interconnect structure.

And an interconnection structure (not shown) formed over the contact hole to electrically connect the first drain region 51a and the second drain region 52a, and to electrically connect the first gate structure 31a and the second gate structure 32 a. Preferably, the material of the interconnection structure may be a metal material with high conductivity, such as copper (Cu) or aluminum (Al).

Preferably, a metal silicide is formed on the first and

second drain regions

51a and 52 a. The metal silicide 90a is formed on the first and second

ohmic contact regions

105a and 106 a. The metal silicide 90a can function to reduce contact resistance and improve the performance of the semiconductor device.

It should be understood that the cross-sectional shapes of the respective regions in the embodiments of the present invention are merely exemplary descriptions, and may be irregular shapes or the like formed in an actual production process.

In the embodiment of the invention, the recess is arranged in the body region between the first source region and the second source region, the pick-up region with the doping type opposite to that of the first source region and the second source region is arranged at the bottom of the recess, and the metal silicide is formed on the surface of the recess and electrically connects the pick-up region with the first source region and the second source region. Thereby, the pick-up capability of the body region of the semiconductor device can be improved.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method of forming a semiconductor device, comprising:

patterning the barrier layer;

2. The method of claim 1, wherein the patterning the barrier layer comprises:

etching the barrier layer above the first gate structure and the second gate structure to form a plurality of holes exposing the first gate structure and a plurality of holes exposing the second gate structure;

wherein the metal silicide formed by the self-aligned process also covers the bottom of the hole.

3. The method of claim 1 or 2, wherein the patterning the barrier layer further comprises: etching the barrier layer above the first drain region and the second drain region to expose the first drain region and the second drain region;

the metal silicide formed through the self-alignment process also covers the first drain region and the second drain region.

4. The method of claim 1, further comprising:

and forming a floating gate on the barrier layer.

5. The method of claim 4, further comprising:

6. The method of claim 1, further comprising: before forming the second groove, a first side wall covering the side wall of the first grid structure and part of the doped region and a second side wall covering the side wall of the second grid structure and part of the doped region are formed.

7. The method of claim 6, wherein the first source region is below the first sidewall, the second source region is below the second sidewall, and the second recess is between the first sidewall and the second sidewall.

8. The method of claim 1, wherein the first drift region and the second drift region have a first doping type and the body region has a second doping type.

9. A semiconductor device, comprising:

a first gate structure covering a portion of the first drift region;

a second gate structure covering a portion of the second drift region;

10. The semiconductor device according to claim 9, further comprising a barrier layer;

11. The semiconductor device according to claim 9 or 10, characterized by further comprising:

a floating gate formed over the barrier layer;

12. The semiconductor device according to claim 9, wherein a metal silicide is formed over the first drain region and the second drain region.

13. The semiconductor device according to claim 9, further comprising:

14. The semiconductor device of claim 13, wherein the recess is located between the first sidewall and the second sidewall.