CN114927581A - Three-dimensional photosensitive pixel structure of silicon-based CMOS image sensor and preparation method thereof - Google Patents

Abstract

The invention belongs to the field of image sensors, and relates to a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor and a preparation method thereof. The invention can effectively improve the light incidence efficiency and enlarge the light space angle, thereby effectively improving the comprehensive photosensitive performance of the front-illuminated CMOS structure; due to the light trapping effect and the resonance absorption enhancement effect, the light absorption utilization rate of the light sensitive pixel structure with the nano-pillar structure can be effectively improved; because the silicon nano-pillar is of an inner and outer model PN junction structure, compared with a planar PN junction photosensitive pixel with the same cross section area, the silicon nano-pillar has a larger potential barrier region, and the full-well capacity of the silicon nano-pillar can be improved; therefore, other incident angles except the vertical angle exist in the actual incident light, so that the side wall barrier region can also respond to the incident light, and the comprehensive weak light response capability is effectively improved; the structure preparation method is low in difficulty and suitable for being integrated and applied to a mature IC industrial production line, so that the pixel photosensitive performance of the silicon-based CMOS image sensor is effectively improved.

Description

Three-dimensional photosensitive pixel structure of silicon-based CMOS image sensor and preparation method thereof

technical field

The invention belongs to the field of image sensors, and in particular, relates to a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor and a preparation method thereof.

Background technique

As a pixel matrix integrated chip that converts optical image information into electrical signals, image sensor plays a key role in photographic camera equipment. With the rapid development of silicon-based IC manufacturing process and the popularization of mobile terminals, image sensors based on CMOS technology have become the mainstream of current image sensors.

The CMOS image sensor uses a silicon-based photodiode (Photo-Diode, PD) as the basic photoelectric conversion unit, and is connected with the corresponding pixel control readout circuit to form a complete pixel structure. Among them, the photodiode module, as the photoelectric conversion part, plays a decisive role in the collection quality of optical information. At present, PDs in commercial CMOS currently use a planar PN structure. A thin N+ layer is generated by N-type implantation on the upper layer of P-silicon, and incident photons are captured by the barrier region formed at the PN junction interface to generate photo-induced carriers; then Build hierarchically connected control readout circuits around the PDs that ultimately conduct signals to external circuits. In order to effectively reduce the dark noise caused by the dark current on the PD surface, some companies propose to "bury" a thin P+ diffusion layer in the upper layer of the N-type doped region of the PD, and reduce the surface defects and dark current of the photodiode through surface modification. (US5567632A). This structure, also known as a buried photodiode, is currently the main form of PD in high-end CMOS image sensors.

The above-mentioned CMOS pixel photosensitive structure is also called a front-illuminated structure. Since the multi-layer conductive bus lines in the surrounding circuit form a metal "wall" with a height of tens of nanometers, the photodiode is deeply trapped in a "well"-shaped structure, and its light receiving space angle is small, which reduces the light incidence efficiency, resulting in weak response to dark light and sensitivity to light. Poor capability, low dynamic range, etc. In order to solve this problem, the researchers proposed a back-illuminated CMOS image sensor structure (US8378440B2, US7425460B2, US7750280B2), which replaces the photosensitive layer and the circuit layer and uses a thin silicon substrate to make the light incident from the back, which can effectively reduce the The "well" effect of front-illuminated CMOS pixels. However, in order to ensure that the light is transmitted through this process, the substrate thickness must be extremely thin (only 1/100 of the front-illuminated type), so the technical requirements are extremely high, and the yield rate is low, which can only be achieved by a few technology companies such as Sony.

SUMMARY OF THE INVENTION

In view of the above problems, the present invention proposes a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor and a preparation method thereof. The pixel structure maintains the overall layout of the PD and the metal circuit in the same direction in the front-illuminated type, and by constructing a three-dimensional photosensitive PD, Therefore, the light incident efficiency is improved, the light space angle is enlarged, and the light absorption efficiency is increased simultaneously, and the typical limitation problem of the basic front-illuminated structure is solved without significantly increasing the process complexity.

For achieving the above object, the technical scheme of the present invention is:

A three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor is composed of a P silicon substrate, a silicon nano-pillar above the substrate, a masking layer on the surface of the substrate, an annular electrode on the bottom sidewall of the silicon nano-pillar, and a connecting liner. bottom electrode.

The silicon nano-pillars above the substrate are made of a whole piece of P-silicon with the silicon substrate. The upper and side surfaces of the nano-pillars are N-type doped layers, and the interior is a P-silicon material with the same parameters as the substrate. .

The masking layer on the surface of the silicon substrate is a passivation layer on the upper surface of the P-silicon substrate, so as to achieve the effect of interference isolation. Its material is usually an oxidatively grown SiO ₂ layer, and when it is a SiO ₂ layer, its thickness is 20-50 nm.

The annular electrode on the bottom sidewall of the silicon nanopillar and the electrode connecting the substrate are located on the upper surface of the P-silicon substrate, and there is no masking layer at the corresponding position on the P-silicon substrate, and its materials include aluminum, aluminum-copper alloy, polysilicon, etc. IC electrode material.

A preparation method of a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor, comprising the following steps:

Step 1: Preprocess the surface of a P silicon wafer to remove surface impurities.

Step 2: etching the silicon nano-pillar array on the surface of the P-silicon substrate processed in step 1. In order to obtain a nano-pillar array with high consistency, a top-down photolithography process can be used, and the ICP-RIE process can be used.

Step 3: Prepare a masking layer on the surface of the P silicon substrate obtained in Step 2 (including the surface of the silicon nano-pillars), which is used for the subsequent doping process and the patterned isolation layer in the metal deposition; a layer can be grown by high-temperature oxidation dense masking layer.

Step 4: remove the attached masking layer from the surface of the silicon nanopillars on the P silicon substrate through an etching process, so that the silicon layer of the silicon nanopillars is exposed; this step can also be completed by a top-down ICP-RIE etching process.

Step 5: The N-type doping process is performed on the surface of the P silicon substrate (including the surface of the silicon nano-pillars), so that an N-type region is formed on the outer surface of the silicon nano-pillars; this step is mainly completed by a thermal diffusion process.

Step 6: According to the positions of the annular electrode on the bottom sidewall of the silicon nanopillar and the electrode connecting to the substrate, an etching process is used near the pixel of the silicon nanopillar to remove the masking layer corresponding to the surface of the P silicon substrate, so that the P silicon The substrate is exposed in this part, in preparation for connecting the metal layer in the subsequent step of metal layer deposition, and constructing the electrode.

Step 7: A deposition method such as magnetron sputtering and electroplating can be used to uniformly deposit a metal layer on the surface of the P silicon substrate.

Step 8: According to the position of the annular electrode on the bottom sidewall of the silicon nanopillar and the electrode connecting the substrate, etch away the excess metal on the upper surface of the silicon nanopillar and the surface of the P silicon substrate; on the bottom sidewall of the silicon nanopillar A ring-shaped electrode is formed for connecting the N-type doping region of the nano-pillars; the electrode connecting the substrate is directly connected to the P-silicon substrate.

Beneficial effects of the present invention:

(1) Compared with the planar PN junction photosensitive pixel in the typical front-illuminated CMOS, the present invention can effectively improve the light incidence efficiency and expand the light space angle due to the height advantage of the photosensitive pixel, thereby effectively improving the comprehensive structure of the front-illuminated CMOS structure. Photosensitive properties.

(2) The photosensitive pixel structure of the nano-column structure can effectively improve the light absorption utilization rate compared with the planar PN junction photosensitive pixel of the same cross-sectional area due to the light trapping effect and the resonance absorption enhancement effect.

(3) Since the silicon nanopillar is an inner and outer bulk PN junction structure, it has a larger area of the barrier region than a planar PN junction photosensitive pixel with the same cross-sectional area, which can improve its full well capacity; The incident light has other incident angles other than vertical, so that the sidewall barrier region can also respond to the incident light, thereby effectively improving the comprehensive weak light response capability.

(4) The preparation method of the structure is less difficult, and is suitable for integration and application to a mature IC industrial production line, thereby effectively improving the pixel photosensitive performance of the silicon-based CMOS image sensor.

Description of drawings

Figure 1 is a schematic structural diagram of the present invention (planed front view), in the figure, 1 is a P silicon substrate, 2 is an N-type doped region, 3 is a PN barrier region, 4 is a substrate electrode, and 5 is an N-type Doping layer electrode, 6 is a masking layer.

2 is a schematic structural diagram (top view) of the present invention. In the figure, 2 is the top N-type doped region corresponding to the nano-column, 4 is the substrate electrode, 5 is the N-type doped layer electrode, and 6 is the masking layer.

FIG. 3 is a schematic diagram of a pixel receiving light.

FIG. 4 is a schematic diagram of the preparation process of the present invention (taking two pixels as an example).

Detailed ways

The specific embodiments of the present invention will be further described below with reference to the accompanying drawings and technical solutions.

As shown in FIG. 1, a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor includes a P silicon substrate 1, a silicon nanopillar (an N-type doped region 2 on the outside, and a P-type doped region on the inside) structure, N A surrounding barrier region 3 is formed between the P-type region and the P-type region, a masking layer 6 is deposited on the substrate, the N-type doped layer electrode 5 surrounds the bottom of the N-type doped region, and the substrate electrode 4 is connected to the silicon substrate. It can be found that due to the role of the masking layer, the N-type doped layer electrode 5 is only connected to the N-type doped region, while the substrate electrode 4 is only connected to the P-silicon substrate 1, and the substrate electrode 4 and the N-type doped layer electrode 5 are respectively used as Connect to the electrode interface of the ICized circuit. At the same time, the distribution of the barrier region at the boundary between the N-type doped region and the P-type doped region can be seen.

FIG. 2 is a schematic top view of a single photosensitive pixel structure. It can be found that the N-type doped layer electrode 5 surrounding the nano-column 2 is annular. This structure helps to ensure the tight connection between the N-type doped region and the electrode, and prevents poor contact cause a bad spot.

The working principle of the three-dimensional photosensitive pixel structure of the silicon-based CMOS image sensor of the present invention: the pixel structure is connected with the pixel-level CMOS control readout circuit through two metal electrodes. Because the silicon-based pixel has a three-dimensional columnar structure, when it is not illuminated, a large number of internal carriers are depleted due to the clad PN junction barrier between the inner and outer layers, resulting in an ultra-low carrier concentration. state, so its impedance is high and dark current is low, resulting in low dark noise level.

When incident light shines from top to bottom, the nanopillars absorb the light and generate more carriers through the photoelectric effect. Because the pixel structure is nano-column: 1) according to the light trapping effect, after the semiconductor material is etched into a nano-structure, its reflectivity to incident light decreases; 2) according to the resonance absorption enhancement effect, the relationship between the three-dimensional semiconductor nano-column and the optical field The interaction between the two will produce leakage mode resonance phenomenon, which will increase its absorption level of light; 3) Since the actual incident light has an oblique incident angle, as shown in Figure 3, its sidewall can also absorb a certain amount of incident light . Therefore, compared with the planar PN junction photodiode with the same cross-sectional area, the structure has a higher light absorption level for light, thereby further improving the light utilization rate and effectively enhancing the responsiveness to weak light. In addition, compared with the planar PN junction barrier, because it is a PN junction barrier, the area of the potential barrier is larger than that of the planar structure when the cross-sectional area is to pass, which also increases its full well capacity, so that in strong light The saturation limit has risen in shooting.

In addition, its height characteristic makes the surrounding metal circuit significantly reduce the light blocking effect on it, which improves the light incident efficiency and expands the light space angle.

Example:

A preparation method of a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor according to the present invention is shown in FIG. 4, and the details are as follows:

In step a, a standard P silicon wafer (the diameter of the bottom surface can be 4, 6, 8, 12 inches, etc., and the thickness is generally 200 μm and above) is organically cleaned and ultrasonicated to remove the organic impurities adhered to the surface of the silicon wafer. Specific operations In order to sequentially use acetone, ethanol, and deionized water as cleaning agents, the silicon wafers were sonicated for 5-10 minutes respectively.

In step b, on the surface of the P silicon wafer, a silicon nano-pillar array of a fixed size is etched. In order to obtain a nanopillar array with high consistency, a standard photolithography process is used to lithography cylindrical holes of a certain size on the surface of the silicon wafer (the diameter is set according to the diameter of the nanopillars), and then thermal evaporation equipment is used. , an Al circular mask is formed on its surface, and the nano-pillar etching is completed by ICP-RIE process. In the etching, mixed gas (sulfur hexafluoride + high-purity oxygen + trifluoromethane) is used to etch the silicon material. The process of the etching reaction is as follows: the added sulfur hexafluoride and trifluoromethane gas will generate CFX and SFX , under the action of the surface electric field, the surface of the silicon material is bombarded, and the silicon material is physically etched. At the same time, the free fluorine atoms combine with the silicon atoms to form volatile SiF4, which realizes the chemical etching of the silicon material. The combination of etching and chemical etching improves the etching rate; and a passivation layer SiOxFy is formed on the sidewall of the silicon to protect the sidewall.

In step b, a dense SiO ₂ oxide layer is grown on the surface of the silicon wafer by high temperature thermal oxidation (temperature 900-1200° C.), with a growth thickness of about 20-50 nm, which is used for patterning isolation in the subsequent doping process and metal deposition Floor.

Step d, in this step, through the ICP-RIE etching process, the SiO ₂ masking layer deposited in the previous step on the upper surface and the side surfaces of the silicon nanopillars is etched to expose the P-silicon material inside. In this step, sulfur hexafluoride and difluoromethane are alternately used for etching to improve the etching efficiency, and high-purity oxygen is introduced at the same time. The shape remains cylindrical.

In step e, an N-type doping process is performed on the upper surface of the silicon wafer, so that an N-type region is formed on the outer surface of the silicon nanopillar. This step is mainly completed by a thermal diffusion process, the diffusion source is a phosphorus source, and the diffusion temperature is about 1000 ° C. First, the dopant is introduced into the wafer surface through a deposition process, and then the dopant is advanced to the desired surface depth through a push process. , the pn junction depth is about 100nm.

In step f, the part of the substrate surface near the nano-pillar pixel in the silicon wafer is etched, and the corresponding part of the oxide layer is removed to expose the P-silicon for subsequent connection of metal electrodes. The specification of the exposed part in this part of the process is determined by the size of the contact hole required in the IC process. Mixed gas (sulfur hexafluoride, difluoromethane, pure oxygen) is used for ICP-RIE etching in the etching.

In step g, the upper metal layer of silicon is deposited. In this step, a deposition method such as magnetron sputtering and evaporation coating can be used to uniformly deposit a metal layer on the surface of the silicon wafer to prepare for the construction of electrodes in subsequent steps. In this example, a layer of metal is deposited on the surface of the silicon wafer by means of magnetron sputtering, the sputtering target is a copper source, and the sputtering thickness is 100 nm. Collimated sputtering is used in the sputtering process, and a bias voltage is applied to the surface of the silicon wafer to attract metal ions directly into the plane around the nanopillars, providing more uniform coverage.

Step h, through ICP-RIE patterned etching, using mixed gas (sulfur hexafluoride, difluoromethane, pure oxygen), remove the metal layer on the upper surface of the silicon nanopillar in the previous step, leaving a ring-shaped The copper electrodes are used to connect the nanopillar sidewalls and leave the electrodes contacting the P-silicon substrate through the oxide layer to effectively connect the P-silicon substrate.

The application of this structure to the field of image sensors will effectively enhance the light perception capability of the photoelectric conversion structure and improve the detection level of weak light. When the structure is applied in a front-illuminated CMOS image sensor, the structure can effectively improve the light sensing performance, expand the light space angle, and enhance the product competitive advantage on the basis of the limited increase in technical difficulty of the front-illuminated structure.

Claims (10)

1. a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor, wherein the composition of the structure comprises a P silicon substrate, a silicon nano-pillar above the substrate, a masking layer on the surface of the substrate, a silicon nano-pillar bottom The annular electrode on the sidewall and the electrode connecting the substrate; The silicon nano-pillars above the substrate are made of a whole piece of P-silicon with the silicon substrate. The upper and side surfaces of the nano-pillars are N-type doped layers, and the interior is a P-silicon material with the same parameters as the substrate. ; The masking layer on the surface of the silicon substrate is a passivation layer on the upper surface of the P-silicon substrate; The annular electrode on the bottom sidewall of the silicon nanopillar and the electrode connecting to the substrate are located on the upper surface of the P-silicon substrate, and there is no masking layer at the corresponding position on the P-silicon substrate. 2 . The three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor according to claim 1 , wherein the masking layer is an oxidatively grown SiO ₂ layer with a thickness of 20-50 nm. 3 . 3. The three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor according to claim 1 or 2, wherein the silicon nano-pillar bottom sidewall annular electrode and the electrode connecting the substrate are made of aluminum , aluminum copper alloy or polysilicon. 4. The preparation method of the three-dimensional photosensitive pixel structure of the silicon-based CMOS image sensor according to any of claims 1-3, characterized in that, comprising the following steps: Step 1: Preprocess the surface of a P silicon wafer to remove surface impurities; Step 2: etching the silicon nano-pillar array on the surface of the P-silicon substrate processed in step 1; Step 3: prepare a masking layer on the surface of the P silicon substrate obtained in step 2; Step 4: removing the attached masking layer from the surface of the silicon nano-pillars on the P silicon substrate through an etching process, so that the silicon layer of the silicon nano-pillars is exposed; Step 5: performing an N-type doping process on the surface of the P silicon substrate, so that an N-type region is formed on the outer surface of the silicon nanopillar; Step 6: According to the positions of the annular electrode on the bottom sidewall of the silicon nanopillar and the electrode connecting to the substrate, an etching process is used near the pixel of the silicon nanopillar to remove the masking layer corresponding to the surface of the P silicon substrate, so that the P silicon The substrate is exposed in this part, in preparation for the metal layer deposition in the subsequent steps to connect the metal layer and construct the electrode; Step 7: uniformly deposit a layer of metal layer on the surface of the P silicon substrate; Step 8: According to the position of the annular electrode on the bottom sidewall of the silicon nanopillar and the electrode connecting the substrate, etch away the excess metal on the upper surface of the silicon nanopillar and the surface of the P silicon substrate; on the bottom sidewall of the silicon nanopillar A ring-shaped electrode is formed for connecting the N-type doping region of the nano-pillars; the electrode connecting the substrate is directly connected to the P-silicon substrate. 5 . The method for preparing a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor according to claim 4 , wherein the second and fourth steps are completed by a top-down ICP-RIE etching process. 6 . 6 . The method for preparing a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor according to claim 4 or 5 , wherein in the third step, a dense masking layer is grown by high temperature oxidation. 7 . 7 . The method for preparing a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor according to claim 4 or 5 , wherein the step 5 is completed by a thermal diffusion process. 8 . 8 . The method for preparing a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor according to claim 6 , wherein the fifth step is completed by a thermal diffusion process. 9 . 9 . The method for preparing a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor according to claim 4 , wherein in the seventh step, a deposition method of magnetron sputtering or electroplating is used. 10 . 10 . The method for preparing a three-dimensional photosensitive pixel structure of a silicon-based CMOS image sensor according to claim 6 , wherein, in the seventh step, a deposition method of magnetron sputtering or electroplating is adopted. 11 .

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