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CN114900182B - An adaptive background calibration method for all-digital phase-locked loop bandwidth - Google Patents

An adaptive background calibration method for all-digital phase-locked loop bandwidth Download PDF

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CN114900182B
CN114900182B CN202210425349.4A CN202210425349A CN114900182B CN 114900182 B CN114900182 B CN 114900182B CN 202210425349 A CN202210425349 A CN 202210425349A CN 114900182 B CN114900182 B CN 114900182B
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loop
phase
digital
bandwidth
controlled oscillator
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CN114900182A (en
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唐路
许书凝
唐旭升
张有明
杨天畅
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Southeast University
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Southeast University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H03L7/1075—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

本发明公开了一种针对全数字锁相环带宽的自适应后台校准方法，该方法使用两抽头的LMS算法，采用两条LMS算法的校准环路代替单条LMS算法的校准环路对环路带宽因子进行估计，两条校准环路均产生相应的环路增益估计值后，两者相加得到最终的环路增益估计值，并经过取反操作接入环路，避免了带宽估计结果受环路分频器延时等非理想因素影响而不准确的问题。为了避免外部输入的训练序列对环路的噪声性能和功耗造成影响，本发明使用环路中△‑∑调制器输出的伪随机序列来代替外部输入的训练序列。

The present invention discloses an adaptive background calibration method for the bandwidth of a fully digital phase-locked loop. The method uses a two-tap LMS algorithm, and adopts two LMS algorithm calibration loops to replace a single LMS algorithm calibration loop to estimate the loop bandwidth factor. After both calibration loops generate corresponding loop gain estimation values, the two are added to obtain the final loop gain estimation value, and the loop is connected through a negation operation, thereby avoiding the problem that the bandwidth estimation result is inaccurate due to the influence of non-ideal factors such as loop divider delay. In order to avoid the influence of an externally input training sequence on the noise performance and power consumption of the loop, the present invention uses a pseudo-random sequence output by a △-∑ modulator in the loop to replace the externally input training sequence.

Description

Self-adaptive background calibration method for bandwidth of all-digital phase-locked loop
Technical Field
The invention relates to integrated circuit design, in particular to a self-adaptive background calibration method aiming at the bandwidth of an all-digital phase-locked loop.
Background
All-digital phase-locked loops are used in a wide variety of fields, such as analog and digital communications, and radio electronics, and in particular, in modulation demodulation and phase synchronization in digital communications, a wide variety of phase-locked loops are commonly used. All-digital phase-locked loops have shown advantages of small area, low power consumption, good system integration, etc., which are particularly important for wireless communication devices. The bandwidth background calibration technology using the LMS algorithm enables the sensitivity of the loop bandwidth of the phase-locked loop to analog parameters in the loop to be greatly reduced by estimating the variable factor of the loop bandwidth of the all-digital phase-locked loop, thereby preventing the loop bandwidth from changing due to the influence of non-ideal factors such as process, voltage, temperature and the like and improving the loop performance.
In the prior art, a digital bandwidth background calibration technique for compensating gain variation of a digital oscillator in a phase domain digital phase locked loop is proposed by some technicians. This technique relies on mathematical approximations of the digitally controlled oscillator gain extracted from the digitally controlled oscillator control word and the phase locked loop frequency control word and requires the use of a look-up table to mitigate approximation errors. This technique relies on a look-up table, and the estimation results are not accurate enough and not convenient to use. Furthermore, this technique can only estimate the gain of the digitally controlled oscillator, but not the gain of the time-to-digital converter, and thus cannot be directly applied to a time-to-digital converter based phase-locked loop.
In the prior art, a method of correlating a band-band PLL loop with a random signal injected from outside the loop to estimate the bandwidth of the loop and adjusting the loop filter coefficients so that the loop bandwidth is constant has been proposed by still other technicians. The random signal used in this method is injected into the loop from outside the loop. The injection of random signals into the loop introduces additional noise into the loop, degrading the noise performance of the loop and increasing the total output noise power of the loop. Furthermore, analog delays in the loop can lead to inaccurate estimates of loop gain.
The patent CN113037280a,2021.04.08 proposes a bandwidth calibration method. Firstly, the phase-locked loop is in a closed loop state, and the first frequency output by the voltage-controlled oscillator and the corresponding input control voltage are obtained after the phase-locked loop is locked. And then the phase-locked loop is in a first mode, the output current of the charge pump is controlled, the input voltage of the voltage-controlled oscillator is a preset first input voltage, and the first period is obtained according to the second frequency output by the voltage-controlled oscillator in the preset time and the frequency division value of the first frequency divider. And then adjusting the phase-locked loop to a second mode, controlling the charge pump to enable the input voltage of the voltage-controlled oscillator to be a preset second input voltage, and obtaining a second period according to the third frequency output by the voltage-controlled oscillator in the preset time and the frequency division value of the first frequency divider. And finally, obtaining a control bit value according to the first period, the second period and the target gain bandwidth, and configuring the charge pump according to the control bit value so as to keep the gain bandwidth of the phase-locked loop constant. However, this method is too complicated and inconvenient to implement.
Disclosure of Invention
Therefore, the invention aims to provide a self-adaptive background calibration method for the bandwidth of an all-digital phase-locked loop, which calibrates the loop bandwidth of the all-digital phase-locked loop, and compared with the traditional phase-locked loop which does not calibrate the loop bandwidth, the sensitivity of the loop to analog parameters is greatly reduced, thereby preventing the loop bandwidth from changing due to the influence of non-ideal factors such as process, voltage, temperature and the like, and greatly improving the loop performance.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
an adaptive background calibration method for the bandwidth of an all-digital phase-locked loop comprises a variable phase accumulator VPA, a reference phase accumulator RPA, an automatic frequency calibration module AFC, a digital control oscillator DCO, a digital loop filter DLF, a time-to-digital converter TDC, a delta-sigma modulator DSM and a subtracter;
The calibration method comprises the following steps:
Firstly, determining the loop gain of the all-digital phase-locked loop, wherein the loop gain is expressed as follows:
In the formula, N is the frequency division ratio of a phase-locked loop, which means that the frequency divider accumulates N digital control oscillator DCO output signal periods in one reference clock period, K T and K TDC are the gains of the digital control oscillator DCO and the time-digital converter TDC respectively, and alpha and beta are loop filter parameters;
Then, the loop bandwidth is approximated using the normalized gain frequency of the loop bandwidth, and then the loop bandwidth is expressed as:
In this formula, f ref is the phase-locked loop reference frequency, loop gain factor g=nk TKTDC;
finally, by introducing two calibration loops based on an LMS algorithm, estimating a loop gain factor, and then accessing the loop gain factor g obtained through estimation into the loop through the negation operation, so that the loop bandwidth becomes:
At this point, the loop bandwidth is only related to the filter parameter β and the pll reference clock frequency f ref;
The method comprises the steps of adopting two calibration loops based on an LMS algorithm, wherein the input of one loop is a training sequence which is not subjected to delay processing, the input of the other loop is a training sequence which is subjected to delay processing of a reference clock period, after the two calibration loops generate corresponding loop gain factor estimated values, adding the two corresponding loop gain factor estimated values to obtain a final loop gain factor estimated value, and accessing the loop through inverting operation to finally obtain a bandwidth calibration loop with a bandwidth estimation result which is not influenced by non-ideal factors.
Further, the two calibration loops based on LMS algorithm are used, the training sequence used is a pseudo-random sequence, and the pseudo-random sequence is a pseudo-random sequence output by the delta-sigma modulator DSM between the digital loop filter DLF and the digitally controlled oscillator DCO.
Further, the gain of the DCO is specifically expressed as:
ΔC is the minimum variable capacitance of the switched capacitor array of the numerically controlled oscillator, C tot is the capacitance of the resonant cavity of the numerically controlled oscillator, and T out is the period of the DCO output signal.
Further, the gain of the time-to-digital converter TDC is specifically expressed as:
In this formula Δt TDC is the resolution of the time-to-digital converter.
Further, the non-ideal factors include process P, voltage V and temperature T.
Further, the variable phase accumulator VPA and the reference phase accumulator RPA are used for converting frequency information into phase information;
The automatic frequency calibration module AFC is used for comparing output values of the variable phase accumulator VPA and the reference clock period counter and judging the size relation of the variable phase accumulator VPA and the reference clock period counter, so as to change the rough adjustment and medium adjustment control words of the numerical control oscillator DCO;
The digital controlled oscillator DCO outputs signals with corresponding frequencies according to the input multi-bit control word.
Further, when the all-digital phase-locked loop starts to work, the method specifically comprises the following working procedures:
Firstly, locking the output signal frequency of a digital controlled oscillator DCO to a sub-band of a target frequency through an automatic frequency calibration module AFC, completing the calibration of a coarse tuning and a middle tuning control word of the digital controlled oscillator DCO, after completing the calibration, completing the locking of a coarse tuning and a middle tuning loop of an all-digital phase-locked loop again, and after completing the locking, adjusting a fine tuning part of the DCO control word by a phase discrimination loop to lock the fine tuning part to the target frequency, wherein the phase discrimination loop comprises a reference phase accumulator RPA, a variable phase accumulator VPA, a time-digital converter TDC, a digital loop filter DLF, a delta-sigma modulator DSM and a subtracter;
The fine tuning loop of the all-digital phase-locked loop starts to work, and the fine tuning loop comprises that an output signal CKV of the digital controlled oscillator DCO after being divided by a frequency divider N enters a time-digital converter TDC and a variable phase accumulator VPA respectively, the variable phase accumulator VPA counts the integer part of the period of the CKV of the DCO after being divided by the frequency divider N, the time-digital converter TDC carries out fractional part quantization on the CKV, and the output of the variable phase accumulator VPA and the output of the time-digital converter TDC are integrated, wherein the output obtained after integration is the phase value of the output frequency CKV;
Finally, the subtracter subtracts the reference phase from the output phase, the obtained phase error is sent to the digital loop filter DLF, the digital loop filter DLF calculates a new digital control oscillator DCO control word according to the phase error, wherein the new digital control oscillator DCO control word is sent to the input end of the digital control oscillator DCO after passing through the delta-sigma modulator DSM, and the full digital phase-locked loop is locked after the fine tuning part of the digital control oscillator DCO control word is calibrated.
The beneficial effects of the invention are as follows:
the invention uses the LMS algorithm with two taps, adopts the calibration loop of the two LMS algorithms to replace the calibration loop of the single LMS algorithm to estimate the loop bandwidth factor, and after the two calibration loops generate corresponding loop gain estimated values, the two calibration loops are increased to obtain final loop gain estimated values and are connected into the loop through the negation operation, thereby avoiding the problem that the bandwidth estimated result is affected by non-ideal factors such as delay of a loop frequency divider and the like and is inaccurate.
The invention uses the pseudo-random sequence output by the delta-sigma modulator in the loop to replace the random training sequence input externally, thereby avoiding the influence of the training sequence input externally on the noise performance and the power consumption of the loop.
Compared with the traditional fixed-point algorithm, the LMS algorithm provided by the invention has the advantages that the floating-point algorithm is used for representing the floating-point algorithm, the precision is higher, the representable range is also much larger, and the change of the loop bandwidth can be tracked more accurately.
Drawings
Fig. 1 is a schematic diagram of the ADPLL loop employed in embodiment 1;
Fig. 2 is a schematic diagram of loop bandwidth factor estimation in embodiment 1;
FIG. 3 is a schematic diagram of the structure of the loop of FIG. 1 mentioned in example 1, employing a conventional single tap LMS calibration loop;
FIG. 4 is a schematic diagram of non-ideal factors caused by the delay of the loop divider of FIG. 1 mentioned in embodiment 1;
fig. 5 is a schematic diagram of the structure of the LMS calibration loop using two taps for the loop shown in fig. 1 mentioned in example 1.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1-5, the present embodiment provides an adaptive background calibration method for the bandwidth of an All-digital phase-locked Loop, and the specific structure of the All-digital phase-locked Loop ADPLL (All-DIGITAL PHASE Lock Loop) is shown in fig. 1, and includes;
Variable phase Accumulator VPA (Variable Phase Accumulator), reference phase Accumulator RPA (REFERENCE PHASE Accumulator), automatic frequency calibration module AFC (Auto Frequency Calibrator), digitally controlled oscillator DCO, digital loop filter DLF (Digital Loop Filter), time-to-digital converter TDC (TIME DIGITAL converter), delta-Sigma Modulator DSM (Delta-Sigma Modulator) and subtractor.
Wherein the variable phase accumulator VPA and the reference phase accumulator RPA are used for converting frequency information into phase information;
The automatic frequency calibration module AFC is configured to compare output values of the variable phase accumulator VPA and the reference clock period counter, determine a magnitude relation between the variable phase accumulator VPA and the reference clock period counter, and further change a coarse adjustment control word and a medium adjustment control word of the numerically controlled oscillator DCO;
the digitally controlled oscillator DCO outputs a signal of a corresponding frequency according to the input multi-bit control word.
Specifically, when the all-digital phase-locked loop is started to work, the method specifically comprises the following working procedures:
Firstly, the frequency of the output signal of the numerically controlled oscillator DCO is quickly locked to the sub-band of the target frequency through the automatic frequency calibration module AFC, and the calibration of the coarse and medium control words of the numerically controlled oscillator DCO is completed. After the coarse tuning and the middle tuning of the DCO control word of the numerical control oscillator are calibrated, the coarse tuning and the middle tuning loops of the all-digital phase-locked loop are locked. After the locking is completed, the phase discrimination loop comprising the reference phase accumulator RPA, the variable phase accumulator VPA, the time-to-digital converter TDC, the digital loop filter DLF, the delta-sigma modulator DSM and the subtractor adjusts the fine tuning part of the DCO control word to lock to the target frequency.
Then, the fine tuning loop of the all-digital phase-locked loop starts to work, and the fine tuning loop comprises that the output signal CKV of the digital controlled oscillator DCO after being divided by the frequency divider N enters the time-digital converter TDC and the variable phase accumulator VPA respectively. The variable phase accumulator VPA counts the integer part of the period of the CKV after the DCO is divided by the frequency divider N, the time-digital converter TDC carries out fractional part quantization on the CKV, and the output of the variable phase accumulator VPA and the output of the time-digital converter TDC are integrated, wherein the integrated output is the phase value of the output frequency CKV.
Finally, the subtracter subtracts the reference phase from the output phase, the error of the obtained phase is sent to the digital loop filter DLF, and the digital loop filter DLF calculates a new DCO control word of the digitally controlled oscillator according to the phase error, wherein the new DCO control word of the digitally controlled oscillator is sent to the input end of the DCO of the digitally controlled oscillator after passing through the delta-sigma modulator DSM. After the fine tuning part of the control word of the numerically controlled oscillator DCO finishes calibration, the all-digital phase-locked loop finishes locking.
Specifically, in this embodiment, as shown in fig. 1, the output signal of the DCO is CKV multiplied by N, and the output frequency accuracy of the DCO is improved by using the delta-sigma modulator DSM in the DCO, and the quantization noise of the DCO can be shaped to shift the quantization noise from low frequency to high frequency.
The method specifically comprises the following steps:
step S1, calculating the bandwidth of the all-digital phase-locked loop;
specifically, in the present embodiment, the step S1 includes the steps of:
Step S101, determining loop gain of the loop, wherein the expression is as follows:
In the formula, N is a phase-locked loop frequency division ratio, which means that N digital control oscillator DCO output signal periods are accumulated by a frequency divider in one reference clock period, K T and K TDC are gains of a digital control oscillator DCO (s/bit) and a time-digital converter TDC (bit/s), and alpha and beta are loop filter parameters;
in step S102, in order to obtain a simplified formula of the loop bandwidth, the loop bandwidth may be approximated by using the normalized gain frequency of the loop bandwidth, and thus the loop bandwidth is obtained by the following formula:
In this formula, f ref is the phase-locked loop reference frequency, and the loop gain factor g=nk TKTDC, which is proportional to the DCO, TDC gain.
The DCO gain (s/bit) is specifically expressed as:
in the formula, deltaC is the minimum variable capacitance value of the switch capacitor array of the numerically controlled oscillator, C tot is the capacitance value of the resonant cavity of the numerically controlled oscillator, T out is the period of the DCO output signal, is determined by the resistance and the capacitance of the DCO, and is greatly influenced by the process.
The above-mentioned TDC gain (bit/s) is specifically expressed as:
In this formula Δt TDC is the resolution of the time to digital converter, which is proportional to the propagation delay of the digital logic gate, which is greatly affected by the process, voltage, temperature. Therefore, the loop bandwidth factor G is easily changed by non-ideal factors such as process, voltage, temperature, etc.
Step S103, estimating a loop gain factor through a self-adaptive calibration loop, and accessing the loop gain factor g obtained through estimation into the loop through inverting operation, so that the loop bandwidth becomes:
at this time, the loop bandwidth is only related to the filter parameter β and the pll reference clock frequency, and is not changed due to the influence of the loop non-ideal factors such as process, voltage, temperature, etc.
S2, estimating a loop bandwidth factor of the all-digital phase-locked loop;
specifically, in this embodiment, the step S2 specifically includes:
As can be seen from fig. 1, the ADPLL fine tuning loop is composed of an analog part and a digital part, wherein the analog part includes a signal transmission chain of DCO, a frequency divider, and a TDC, and the rest is the digital part.
The open loop transfer function of the loop simulation portion may be expressed asThe loop gain factor G can thus be estimated by injecting a training signal at the DCO input and calibrated at the TDC output.
The schematic diagram of loop bandwidth factor estimation is shown in fig. 2, and specifically includes:
x n is a training sequence, a pseudo-random sequence, and is injected into the ADPLL loop and the calibration loop to connect the two.
In the calibration loop, the integrating operation in the ADPLL open loop transfer function is replaced by a digital integrator, the result of x [ n ] passing through the integrator is multiplied by the loop gain factor estimated value g [ n ] and compared with the TDC output d [ n ], the difference e [ n ] between the two is fed back to the adaptive algorithm module, and then the latest estimated loop gain factor g [ n ] is output, and the steps are circulated until e [ n ] is zero.
S3, selecting a training sequence;
specifically, in this embodiment, the step S3 specifically includes:
for the training sequence x n an externally input pseudo random sequence may be used instead, but this introduces additional noise to the loop, deteriorating the noise performance of the loop.
In order to avoid the influence of the externally input training sequence on the noise performance and power consumption of the loop, it is preferable to use a signal originally existing in the loop instead.
The ADPLL loop in this embodiment uses DSM in the DCO to improve the output frequency accuracy of the DCO and shape the DCO quantization noise. The output of the DSM happens to be a random sequence. In the embodiment, the pseudo-random sequence output by DSM in the loop is used for replacing the training sequence input from outside, so that the noise performance of the loop is ensured.
Step S4, executing an adaptive LMS algorithm in a calibration loop:
specifically, the adaptive LMS algorithm in the calibration loop is divided into a single-tap LMS algorithm and a two-tap LMS algorithm proposed in this embodiment.
Single tap adaptive LMS algorithm:
ADPLL using a conventional single tap calibration loop is shown in fig. 3. The pseudo-random sequence output by DSM in the loop is used as an input training sequence of a calibration loop, and the loop gain factor estimated value obtained by the calibration loop is accessed into the loop through the negation operation, so that the loop bandwidth is not influenced by non-ideal factors.
The two-tap adaptive LMS algorithm employed in this embodiment:
Non-ideal factors such as a loop divider can lead to inaccurate loop gain factor estimation by a single-tap adaptive LMS algorithm. The non-idealities caused by the loop divider delay are shown in FIG. 4, assuming that the training signal x [ n ] injected into the DCO is a unit pulse, the periodic increment of the DCO output signal is a rectangular pulse of duration T ref, magnitude K T.
In the next reference period, x [ n ] becomes zero, and thus the phase jump variable remains to its final peak NK T. As shown in fig. 4 (a), assuming that the loop frequency divider has no delay, the sequence dn obtained by multiplying the output signal of the DCO by the TDC gain K TDC after sub-sampling by the frequency divider is a training signal x n delayed by one reference clock period and having an amplitude that is enlarged by a gain factor G, and at this time, the single-tap LMS algorithm can accurately predict the loop gain factor G.
As shown in fig. 4 (b), in the actual case, there is a delay in the loop divider, because the loop divider sub-samples the output signal of the DCO once every reference clock cycle, because there is a delay in the loop divider, the phase jump variable has not yet reached its peak value when sub-sampled by the divider after one reference clock cycle in which the value of the training sequence x n is changed, and thus the sequence d n is smaller than the loop gain factor G after one reference clock cycle in which the value of the training sequence x n is changed, and there is a large error in the loop gain factor G predicted by the LMS algorithm with a single tap. Due to the existence of loop divider delay, the output signal of DCO after two reference clock periods of x [ n ] change is subsampled by the divider again and multiplied by TDC gain K TDC, and the value of d [ n ] at the moment is not zero. Since the phase jump variable NK T is constant, the sum of the instantaneous d [ n ] values of these two reference clock cycles is exactly equal to the loop gain factor G.
The present embodiment uses two LMS algorithm calibration loops instead of a single LMS algorithm calibration loop to estimate the loop bandwidth as shown in fig. 5. The input of one loop is the original training sequence x [ n ] which is not subjected to delay treatment, the input of the other loop is the training sequence which is subjected to delay treatment in one reference clock period, the two calibration loops generate corresponding loop gain factor estimated values G [ k ], the two calibration loops are added to obtain accurate loop gain factor estimated values G, and the loop is accessed through the negation operation, so that the bandwidth calibration loop with the bandwidth estimation result not influenced by non-ideal factors such as delay of a loop frequency divider is finally obtained.
In summary, the present invention provides an adaptive background calibration method for the bandwidth of an all-digital phase-locked loop, which reduces the sensitivity of the loop bandwidth to analog parameters in the loop by using an all-digital automatic control loop, so that the bandwidth remains constant. Compared with a single-tap LMS algorithm, the calibration algorithm provided by the invention can eliminate the problem of inaccurate estimation results caused by non-ideal factors such as delay of a loop frequency divider. Meanwhile, the algorithm adopts floating point operation, compared with fixed point operation, the floating point operation has higher accuracy and a much larger representable range, and can track the change of loop bandwidth more accurately.
The present invention is not described in detail in the present application, and is well known to those skilled in the art.
The foregoing describes in detail preferred embodiments of the present invention. It should be understood that numerous modifications and variations can be made in accordance with the concepts of the invention by one of ordinary skill in the art without undue burden. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by the person skilled in the art according to the inventive concept shall be within the scope of protection defined by the claims.

Claims (7)

1.一种针对全数字锁相环带宽的自适应后台校准方法，其特征在于，所述的全数字锁相环包括：可变相位累加器VPA、参考相位累加器RPA、自动频率校准模块AFC、数控振荡器DCO、数字环路滤波器DLF、时间-数字转换器TDC、Δ-Σ调制器DSM以及减法器；1. An adaptive background calibration method for a full digital phase-locked loop bandwidth, characterized in that the full digital phase-locked loop comprises: a variable phase accumulator VPA, a reference phase accumulator RPA, an automatic frequency calibration module AFC, a digitally controlled oscillator DCO, a digital loop filter DLF, a time-to-digital converter TDC, a delta-sigma modulator DSM and a subtractor; 所述校准方法包括如下步骤：The calibration method comprises the following steps: 首先，针对该全数字锁相环，确定其环路增益，表达式为：First, for the fully digital phase-locked loop, determine its loop gain, the expression is: 在该表达式中，N为锁相环分频比，表示一个参考时钟周期内分频器累积了N个数控振荡器DCO输出信号的周期，KT和KTDC分别为数控振荡器DCO和时间-数字转换器TDC的增益，α和β为环路滤波器参数；In this expression, N is the phase-locked loop frequency division ratio, which means that the frequency divider accumulates N cycles of the digitally controlled oscillator DCO output signal in one reference clock cycle, K T and K TDC are the gains of the digitally controlled oscillator DCO and the time-to-digital converter TDC, respectively, and α and β are loop filter parameters; 然后，使用环路带宽的归一化增益频率来近似环路带宽，则环路带宽表示为：The loop bandwidth is then approximated using its normalized gain frequency, and the loop bandwidth is expressed as: 在该表达式中，fref为锁相环参考频率，环路增益因子G＝NKTKTDC；In this expression, f ref is the phase-locked loop reference frequency, and the loop gain factor G = NK T K TDC ; 最后，通过引入采用了两条基于LMS算法的校准环路，对环路增益因子进行预估，再将通过预估所获得的环路增益因子g经过取反操作接入环路，使得环路带宽变为：Finally, two calibration loops based on the LMS algorithm are introduced to estimate the loop gain factor, and then the loop gain factor g obtained by estimation is connected to the loop through an inversion operation, so that the loop bandwidth becomes: 此时，环路带宽仅仅只跟滤波器参数β和锁相环参考时钟频率fref相关；At this time, the loop bandwidth is only related to the filter parameter β and the phase-locked loop reference clock frequency f ref ; 其中，所述的采用了两条基于LMS算法的校准环路，一条环路的输入为未经延时处理的训练序列，另一条环路的输入为经过一个参考时钟周期延时处理的训练序列，在该两条校准环路均产生相应的环路增益因子估计值后，两者相加得到最终的环路增益因子估计值，并经过取反操作接入环路，最终得到带宽不受非理想因素影响的全数字锁相环环路。Among them, two calibration loops based on the LMS algorithm are used, the input of one loop is a training sequence that has not been delayed, and the input of the other loop is a training sequence that has been delayed by a reference clock cycle. After the two calibration loops generate corresponding loop gain factor estimates, the two are added to obtain the final loop gain factor estimate, and the loop is connected through an inversion operation, and finally a fully digital phase-locked loop loop whose bandwidth is not affected by non-ideal factors is obtained. 2.根据权利要求1所述的一种针对全数字锁相环带宽的自适应后台校准方法，其特征在于，所述的采用了两条基于LMS算法的校准环路，其使用的输入训练序列为伪随机序列，并且该伪随机序列为所述数字环路滤波器DLF和所述数控振荡器DCO之间的Δ-Σ调制器DSM输出的伪随机序列。2. According to claim 1, an adaptive background calibration method for the bandwidth of a fully digital phase-locked loop is characterized in that two calibration loops based on the LMS algorithm are used, and the input training sequence used is a pseudo-random sequence, and the pseudo-random sequence is a pseudo-random sequence output by the Δ-Σ modulator DSM between the digital loop filter DLF and the digitally controlled oscillator DCO. 3.根据权利要求1所述的一种针对全数字锁相环带宽的自适应后台校准方法，其特征在于，所述数控振荡器DCO的增益，其具体表示为：3. The adaptive background calibration method for the bandwidth of a fully digital phase-locked loop according to claim 1, wherein the gain of the digitally controlled oscillator DCO is specifically expressed as: △C为数控振荡器开关电容阵列的最小可变电容值，Ctot为数控振荡器谐振腔的容值，Tout为DCO输出信号的周期。△C is the minimum variable capacitance value of the digital controlled oscillator switch capacitor array, C tot is the capacitance value of the digital controlled oscillator resonant cavity, and T out is the period of the DCO output signal. 4.根据权利要求1所述的一种针对全数字锁相环带宽的自适应后台校准方法，其特征在于，所述时间-数字转换器TDC的增益，其具体表示为：4. The adaptive background calibration method for the bandwidth of a fully digital phase-locked loop according to claim 1, wherein the gain of the time-to-digital converter TDC is specifically expressed as: 在该表达式中，△tTDC是时间数字转换器的分辨率。In this expression, Δt TDC is the resolution of the time-to-digital converter. 5.根据权利要求1所述的一种针对全数字锁相环带宽的自适应后台校准方法，其特征在于，所述的非理想因素具体包括：工艺P、电压V、温度T。5. The adaptive background calibration method for the bandwidth of a fully digital phase-locked loop according to claim 1, wherein the non-ideal factors specifically include: process P, voltage V, and temperature T. 6.根据权利要求1所述的一种针对全数字锁相环带宽的自适应后台校准方法，其特征在于，所述的可变相位累加器VPA和参考相位累加器RPA，其用于将频率信息转换为相位信息；6. The adaptive background calibration method for the bandwidth of a fully digital phase-locked loop according to claim 1, characterized in that the variable phase accumulator VPA and the reference phase accumulator RPA are used to convert frequency information into phase information; 所述的自动频率校准模块AFC，其用于将可变相位累加器VPA和参考时钟周期计数器counter的输出数值进行比较，判断两者的大小关系，进而改变数控振荡器DCO的粗调、中调控制字；The automatic frequency calibration module AFC is used to compare the output values of the variable phase accumulator VPA and the reference clock cycle counter counter, determine the magnitude relationship between the two, and then change the coarse adjustment and medium adjustment control words of the digital control oscillator DCO; 所述的数控振荡器DCO，其根据输入的多位控制字输出对应频率的信号。The digitally controlled oscillator DCO outputs a signal of corresponding frequency according to an input multi-bit control word. 7.根据权利要求6所述的一种针对全数字锁相环带宽的自适应后台校准方法，其特征在于，所述的全数字锁相环环路在开始工作时，其具体包括如下的工作过程：7. The method for adaptive background calibration of full digital phase-locked loop bandwidth according to claim 6, characterized in that when the full digital phase-locked loop starts working, it specifically includes the following working process: 首先，通过所述自动频率校准模块AFC将数控振荡器DCO的输出信号频率锁定到目标频率的子频带，完成数控振荡器DCO粗调、中调控制字的校准；再完成校准之后，全数字锁相环的粗调、中调环路再完成锁定；完成锁定之后，鉴相环路对DCO控制字的精调部分进行调整，使其锁定到目标频率，其中，该鉴相环路包括：参考相位累加器RPA、可变相位累加器VPA、时间-数字转换器TDC、数字环路滤波器DLF、Δ-Σ调制器DSM和减法器；First, the output signal frequency of the digital controlled oscillator DCO is locked to the sub-band of the target frequency through the automatic frequency calibration module AFC, and the calibration of the coarse adjustment and intermediate adjustment control words of the digital controlled oscillator DCO is completed; after the calibration is completed, the coarse adjustment and intermediate adjustment loops of the full digital phase-locked loop are locked again; after the locking is completed, the phase detection loop adjusts the fine adjustment part of the DCO control word to make it locked to the target frequency, wherein the phase detection loop includes: a reference phase accumulator RPA, a variable phase accumulator VPA, a time-to-digital converter TDC, a digital loop filter DLF, a delta-sigma modulator DSM and a subtractor; 然后，全数字锁相环的精调环路开始工作，其包括：所述数控振荡器DCO经过分频器N分频后的输出信号CKV分别进入时间-数字转换器TDC和可变相位累加器VPA；可变相位累加器VPA对DCO经过分频器N分频后的CKV的周期进行整数部分计数，所述的时间-数字转换器TDC对CKV进行小数部分量化；再整合可变相位累加器VPA与时间-数字转换器TDC的输出，其中，整合之后得到的输出为输出频率CKV的相位数值；Then, the fine tuning loop of the all-digital phase-locked loop starts to work, which includes: the output signal CKV of the digitally controlled oscillator DCO after being divided by the frequency divider N enters the time-to-digital converter TDC and the variable phase accumulator VPA respectively; the variable phase accumulator VPA counts the integer part of the cycle of CKV of the DCO after being divided by the frequency divider N, and the time-to-digital converter TDC quantizes the decimal part of CKV; and then integrates the output of the variable phase accumulator VPA and the time-to-digital converter TDC, wherein the output obtained after the integration is the phase value of the output frequency CKV; 最后，减法器将参考相位与输出相位相减，得出相位的误差送入数字环路滤波器DLF中，该数字环路滤波器DLF根据相位误差计算出新的数控振荡器DCO控制字，其中，该新的数控振荡器DCO控制字经过Δ-Σ调制器DSM之后，被送入数控振荡器DCO的输入端；数控振荡器DCO控制字的精调部分完成校准之后，全数字锁相环完成锁定。Finally, the subtractor subtracts the reference phase from the output phase to obtain the phase error, which is sent to the digital loop filter DLF. The digital loop filter DLF calculates a new digital controlled oscillator DCO control word based on the phase error, wherein the new digital controlled oscillator DCO control word is sent to the input end of the digital controlled oscillator DCO after passing through the Δ-Σ modulator DSM; after the fine-tuning part of the digital controlled oscillator DCO control word is calibrated, the fully digital phase-locked loop is locked.
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