CN114900182A - Self-adaptive background calibration method for all-digital phase-locked loop bandwidth - Google Patents

Abstract

The invention discloses a self-adaptive background calibration method for the bandwidth of an all-digital phase-locked loop, which uses a two-tap LMS algorithm, adopts two calibration loops of the LMS algorithm to replace a single calibration loop of the LMS algorithm to estimate the loop bandwidth factor, and after the two calibration loops generate corresponding loop gain estimated values, the two calibration loops are added to obtain a final loop gain estimated value and are accessed into the loop through negation operation, thereby avoiding the problem that the bandwidth estimated result is influenced by non-ideal factors such as the delay of a loop frequency divider and the like and is inaccurate. In order to avoid the influence of the training sequence input from outside on the noise performance and power consumption of the loop, the invention uses the pseudo-random sequence output by the delta-sigma modulator in the loop to replace the training sequence input from outside.

Description

An adaptive background calibration method for all-digital phase-locked loop bandwidth

technical field

The invention relates to integrated circuit design, in particular to a self-adaptive background calibration method for the bandwidth of an all-digital phase-locked loop.

Background technique

All-digital phase-locked loops have been widely used in many fields, such as analog and digital communications and radio electronics, especially in the modulation and demodulation and phase synchronization in digital communications. Various phase locked loops. All-digital phase-locked loops have shown the advantages of small area, low power consumption, and good system integration, which are particularly important to wireless communication equipment. Bandwidth Background Calibration Technique Using LMS Algorithm By estimating the variable factor of the all-digital phase-locked loop loop bandwidth, the sensitivity of the phase-locked loop loop bandwidth to the analog parameters in the loop is greatly reduced, thereby preventing due to process, voltage, temperature The change of loop bandwidth caused by the influence of non-ideal factors such as, improves the loop performance.

In the prior art, some technicians have proposed a digital bandwidth background calibration technique for compensating the gain variation of a numerically controlled oscillator in a phase-domain digital phase-locked loop. This technique relies on a mathematical approximation of the numerically controlled oscillator gain extracted from the numerically controlled oscillator control word and the phase-locked loop frequency control word, and requires the use of look-up tables to mitigate approximation errors. This technique relies on look-up tables, the estimation results are not accurate enough, and it is not convenient to use. In addition, this technique can only estimate the gain of the numerically controlled oscillator, but not the gain of the time-to-digital converter, so it cannot be directly applied to the phase-locked loop based on the time-to-digital converter.

In the prior art, some technicians have proposed a method of correlating the Bang-Bang PLL loop with a random signal injected from outside the loop to estimate the bandwidth of the loop and adjust the loop filter coefficients so that method with constant loop bandwidth. The random signal used in this method is injected into the loop from outside the loop. The injection of random signals in the loop can introduce additional noise into the loop, degrade the noise performance of the loop, and increase the overall output noise power of the loop. Additionally, analog delays in the loop can lead to inaccurate estimates of loop gain.

Patent "Chinese Patent CN113037280A, 2021.04.08": A bandwidth calibration method is proposed. Firstly, the phase-locked loop is in a closed-loop state, and after the phase-locked loop is locked, the first frequency output by the voltage-controlled oscillator and the corresponding input control voltage are obtained. Then make the phase-locked loop in the first mode, control the output current of the charge pump, make the input voltage of the voltage-controlled oscillator be the preset first input voltage, and according to the second output of the voltage-controlled oscillator within the preset time frequency, and the frequency division value of the first frequency divider to obtain the first period. Then adjust the phase-locked loop to the second mode, control the charge pump, make the input voltage of the voltage-controlled oscillator be the preset second input voltage, and according to the third frequency output of the voltage-controlled oscillator within the preset time, The division value of the first frequency divider to obtain the second period. Finally, the control bit value is obtained according to the first period, the second period and the target gain bandwidth, and the charge pump is configured according to the value to keep the gain bandwidth of the phase-locked loop constant. However, the steps of this method are too complicated to be implemented easily.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present invention is to provide an adaptive background calibration method for the bandwidth of the all-digital phase-locked loop, which calibrates the loop bandwidth of the all-digital phase-locked loop Bandwidth-calibrated phase-locked loop, the loop's sensitivity to analog parameters is greatly reduced, thus preventing loop bandwidth changes due to non-ideal factors such as process, voltage, temperature, etc., and greatly improving the loop performance.

In order to achieve the above object, the present invention adopts the following technical solutions:

An adaptive background calibration method for the bandwidth of an all-digital phase-locked loop, the all-digital phase-locked loop comprising: a variable phase accumulator VPA, a reference phase accumulator RPA, an automatic frequency calibration module AFC, a numerically controlled oscillator DCO, Digital loop filter DLF, time-to-digital converter TDC, delta-sigma modulator DSM and subtractor;

The calibration method includes the following steps:

First, for the all-digital phase-locked loop, determine its loop gain, the expression is:

In this formula, N is the frequency division ratio of the phase-locked loop, which means that the frequency divider accumulates N numerical control oscillator DCO output signal cycles in one reference clock cycle, and K _T and K _TDC are the numerical control oscillator DCO and time-digital respectively. Gain of converter TDC, α and β are loop filter parameters;

Then, using the normalized gain frequency of the loop bandwidth to approximate the loop bandwidth, the loop bandwidth is expressed as:

In this formula, f _ref is the reference frequency of the phase-locked loop, and the loop gain factor G=NK _T K _TDC ;

Finally, by introducing two calibration loops based on the LMS algorithm, the loop gain factor is estimated, and then the loop gain factor g obtained through the estimation is inserted into the loop through an inversion operation, so that the loop The bandwidth becomes:

At this time, the loop bandwidth is only related to the filter parameter β and the PLL reference clock frequency _fref ;

Among them, two calibration loops based on the LMS algorithm are used. The input of one loop is the training sequence without delay processing, and the input of the other loop is the training sequence that has been delayed by a reference clock cycle. , after the two calibration loops both generate the corresponding estimated value of the loop gain factor, add the two to obtain the final estimated value of the loop gain factor, and access the loop through the inversion operation, and finally get the bandwidth estimation result is not Bandwidth calibration loop subject to non-idealities.

Further, the two calibration loops based on the LMS algorithm are used, and the training sequence used is a pseudo-random sequence, and the pseudo-random sequence is a combination of the digital loop filter DLF and the numerically controlled oscillator DCO. Pseudo-random sequence between the delta-sigma modulator DSM outputs.

Further, the gain of the numerically controlled oscillator DCO is specifically expressed as:

△C is the minimum variable capacitance value of the switched capacitor array of the numerically controlled oscillator, _Ctot is the capacitance of the numerically controlled oscillator resonant cavity, and _Tout is the period of the DCO output signal.

Further, the gain of the time-to-digital converter TDC is specifically expressed as:

In this formula, Δt _TDC is the resolution of the time-to-digital converter.

Further, the non-ideal factors specifically include: process P, voltage V, and temperature T.

Further, the variable phase accumulator VPA and the reference phase accumulator RPA are used to convert frequency information into phase information;

The described automatic frequency calibration module AFC is used to compare the output value of the variable phase accumulator VPA and the reference clock cycle counter counter, to judge the magnitude relationship between the two, and then to change the coarse adjustment and middle adjustment of the numerically controlled oscillator DCO. control word;

The numerically controlled oscillator DCO outputs a signal corresponding to a frequency according to the input multi-bit control word.

Further, when the all-digital phase-locked loop loop starts to work, it specifically includes the following working process:

First, the frequency of the output signal of the numerically controlled oscillator DCO is locked to the sub-band of the target frequency by the automatic frequency calibration module AFC to complete the calibration of the numerically controlled oscillator DCO coarse adjustment and middle adjustment control words; after the calibration is completed, the full digital lock The coarse adjustment and middle adjustment loops of the phase loop complete the locking; after the locking is completed, the phase detection loop adjusts the fine adjustment part of the DCO control word to lock it to the target frequency, wherein the phase detection loop includes: reference Phase accumulator RPA, variable phase accumulator VPA, time-to-digital converter TDC, digital loop filter DLF, delta-sigma modulator DSM and subtractor;

Then, the fine-tuning loop of the all-digital phase-locked loop starts to work, which includes: the output signal CKV of the numerically controlled oscillator DCO after being divided by the frequency divider N enters the time-to-digital converter TDC and the variable phase accumulator respectively. VPA; the variable phase accumulator VPA counts the integer part of the period of the CKV after the DCO is divided by the frequency divider N, and the time-to-digital converter TDC quantizes the fractional part of the CKV; and then integrates the variable phase accumulator The output of VPA and time-to-digital converter TDC, wherein the output obtained after integration is the phase value of the output frequency CKV;

Finally, the subtractor subtracts the reference phase and the output phase, and the obtained phase error is sent to the digital loop filter DLF. The digital loop filter DLF calculates a new numerical control oscillator DCO control word according to the phase error, where , the new numerical control oscillator DCO control word is sent to the input end of the numerical control oscillator DCO after passing through the delta-sigma modulator DSM; after the fine adjustment part of the numerical control oscillator DCO control word is calibrated, the all-digital phase-locked loop is completed. locking.

The beneficial effects of the present invention are:

The present invention uses the two-tap LMS algorithm, and uses two calibration loops of the LMS algorithm to replace the calibration loop of the single LMS algorithm to estimate the loop bandwidth factor. After the two calibration loops both generate corresponding loop gain estimates, The two are added to obtain the final estimated value of the loop gain, and are connected to the loop through the inversion operation, which avoids the inaccurate problem that the bandwidth estimation result is affected by non-ideal factors such as the delay of the loop divider.

The invention uses the pseudo-random sequence output by the delta-sigma modulator in the loop to replace the random training sequence input from the outside, and avoids the influence of the training sequence input from the outside on the noise performance and power consumption of the loop.

The LMS algorithm of the present invention uses floating-point arithmetic. Compared with the traditional fixed-point arithmetic, the floating-point arithmetic has higher representation precision, and can represent a much larger range, and can track the change of the loop bandwidth more accurately.

Description of drawings

Fig. 1 is the structural representation of the ADPLL loop adopted in embodiment 1;

2 is a schematic diagram of loop bandwidth factor estimation in Embodiment 1;

3 is a schematic structural diagram of a traditional single-tap LMS calibration loop mentioned in Embodiment 1 for the loop shown in FIG. 1;

4 is a schematic diagram of a non-ideal factor caused by the delay of the loop divider in FIG. 1 mentioned in Embodiment 1;

FIG. 5 is a schematic structural diagram of the LMS calibration loop with two taps mentioned in Embodiment 1 for the loop shown in FIG. 1 .

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

Example 1

Referring to FIG. 1 to FIG. 5 , this embodiment provides an adaptive background calibration method for the bandwidth of an all-digital phase-locked loop, and the specific structure of the all-digital phase-locked loop (ADPLL) loop for the method is As shown in Figure 1, it includes;

Variable Phase Accumulator VPA (Variable Phase Accumulator), Reference Phase Accumulator RPA (Reference Phase Accumulator), Automatic Frequency Calibration Module AFC (Auto Frequency Calibrator), Numerically Controlled Oscillator DCO, Digital Loop Filter DLF (Digital Loop Filter) , Time-to-digital converter TDC (TimeDigital Convertor), delta-sigma modulator DSM (Delta-Sigma Modulator) and subtractor.

Wherein, the above-mentioned variable phase accumulator VPA and reference phase accumulator RPA are used to convert frequency information into phase information;

The above-mentioned automatic frequency calibration module AFC is used to compare the output value of the variable phase accumulator VPA and the reference clock cycle counter counter, and determine the magnitude relationship between the two, and then change the coarse adjustment and middle adjustment control of the numerical control oscillator DCO. Character;

The above-mentioned numerically controlled oscillator DCO outputs a signal corresponding to the frequency according to the input multi-bit control word.

Specifically, when the all-digital phase-locked loop loop starts to work, it specifically includes the following working process:

First, the frequency of the output signal of the numerically controlled oscillator DCO is quickly locked to the sub-band of the target frequency by the above-mentioned automatic frequency calibration module AFC, so as to complete the calibration of the control words of the numerically controlled oscillator DCO for coarse adjustment and intermediate adjustment. After the coarse adjustment and the middle adjustment part of the numerical control oscillator DCO control word are calibrated, the coarse adjustment and the middle adjustment loop of the all-digital phase-locked loop are locked. After the locking is completed, the phase detection loop adjusts the fine-tuning part of the DCO control word to lock it to the target frequency, wherein the phase detection loop includes: the reference phase accumulator RPA, the variable phase accumulator VPA, the time - Digital converter TDC, digital loop filter DLF, delta-sigma modulator DSM and subtractor.

Then, the fine-tuning loop of the all-digital phase-locked loop starts to work, which includes: the output signal CKV of the above-mentioned numerically controlled oscillator DCO after being divided by the frequency divider N enters the time-to-digital converter TDC and the variable phase accumulator respectively. VPA. The variable phase accumulator VPA counts the integer part of the period of the CKV after the DCO is divided by the frequency divider N, and the above-mentioned time-to-digital converter TDC quantizes the fractional part of the CKV; and then integrates the variable phase accumulator VPA with the time - the output of the digital converter TDC, wherein the output obtained after integration is the phase value of the output frequency CKV.

Finally, the subtractor subtracts the reference phase and the output phase, and the obtained phase error is sent to the digital loop filter DLF. The digital loop filter DLF calculates a new numerical control oscillator DCO control word according to the phase error, where , the new numerical control oscillator DCO control word is sent to the input end of numerical control oscillator DCO after passing through the delta-sigma modulator DSM. After the fine-tuning part of the digitally controlled oscillator DCO control word is calibrated, the all-digital phase-locked loop is locked.

Specifically, in this embodiment, as shown in FIG. 1 , the output signal of the numerically controlled oscillator DCO is an N-multiplied CKV, and the delta-sigma modulator DSM is used in the numerically controlled oscillator DCO to improve the output signal of the DCO. Output frequency accuracy, and can also shape the DCO quantization noise to move the quantization noise from low frequency to high frequency.

The method specifically includes the following steps:

Step S1, for this all-digital phase-locked loop, calculate its bandwidth;

Specifically, in this embodiment, the step S1 includes the following steps:

Step S101, determine its loop gain, the expression is:

In this formula, N is the frequency division ratio of the phase-locked loop, which means that the frequency divider accumulates N numerical control oscillator DCO output signal cycles in one reference clock cycle, and K _T and K _TDC are the numerical control oscillator DCO (s/bit ) and the gain of the time-to-digital converter TDC (bit/s), α and β are loop filter parameters;

In step S102, in order to obtain a simplified formula of the loop bandwidth, the normalized gain frequency of the loop bandwidth can be used to approximate the loop bandwidth. Therefore, the loop bandwidth is obtained by the following formula:

In this formula, f _ref is the reference frequency of the phase-locked loop, and the loop gain factor G=NK _T K _TDC , which is proportional to the DCO and TDC gains.

Among them, the above-mentioned DCO gain (s/bit) is specifically expressed as:

In this formula, ΔC is the minimum variable capacitance value of the switched capacitor array of the numerically controlled oscillator, _Ctot is the capacitance of the numerically controlled oscillator resonant cavity, and _Tout is the period of the DCO output signal, which is determined by the resistance and capacitance of the DCO, And it is greatly affected by the process.

The above TDC gain (bit/s) is specifically expressed as:

In this formula, Δt _TDC is the resolution of the time-to-digital converter, which is proportional to the propagation delay of the digital logic gate and is greatly affected by process, voltage, and temperature. Therefore, the loop bandwidth factor G is easily changed by non-ideal factors such as process, voltage, and temperature.

Step S103: Estimate the loop gain factor through an adaptive calibration loop, and then insert the loop gain factor g obtained through the estimation into the loop through an inversion operation, so that the loop bandwidth becomes:

At this time, the loop bandwidth is only related to the filter parameter β and the reference clock frequency of the phase-locked loop, and will not change due to the influence of loop non-ideal factors such as process, voltage, temperature, etc.

Step S2, for the all-digital phase-locked loop, estimate its loop bandwidth factor;

Specifically, in this embodiment, the step S2 specifically includes:

As can be seen from Figure 1, the ADPLL fine-tuning loop consists of an analog part and a digital part. The analog part includes a signal transmission chain of DCO, frequency divider, and TDC, and the rest are digital parts.

因此环路增益因子G可以通过在DCO输入端注入一个训练信号估计出来，并且在TDC输出端被校准。The open-loop transfer function of the analog part of the loop can be expressed as

Thus the loop gain factor G can be estimated by injecting a training signal at the input of the DCO and calibrated at the output of the TDC.

The schematic diagram of loop bandwidth factor estimation is shown in Figure 2, which includes:

x[n] is the training sequence, which is a pseudo-random sequence, which is injected into the ADPLL loop and the calibration loop at the same time to connect the two.

In the calibration loop, the integration operation in the ADPLL open-loop transfer function is replaced by a digital integrator, and the result after x[n] passes through the integrator is multiplied by the loop gain factor estimate g[n] and summed with the TDC output d[ n] for comparison, the difference e[n] between the two is fed back to the adaptive algorithm module, and then the newly estimated loop gain factor g[n] is output, and the cycle is repeated until e[n] is zero.

Step S3, select a training sequence;

Specifically, in this embodiment, the step S3 specifically includes:

For the training sequence x[n], an externally input pseudorandom sequence can be used instead, but this will introduce additional noise into the loop, deteriorating the noise performance of the loop.

In order to avoid the influence of the externally input training sequence on the noise performance and power consumption of the loop, it is better to use the signal already existing in the loop instead.

The ADPLL loop in this embodiment uses the DSM in the DCO to improve the output frequency accuracy of the DCO and shape the DCO quantization noise. The output of the DSM happens to be a random sequence. In this embodiment, the pseudo-random sequence output by the DSM in the loop is used to replace the externally input training sequence, which ensures the noise performance of the loop.

Step S4, execute the adaptive LMS algorithm in the calibration loop:

Specifically, the adaptive LMS algorithm in the calibration loop is divided into a single-tap LMS algorithm and the two-tap LMS algorithm proposed in this embodiment.

Single-tap adaptive LMS algorithm:

An ADPLL using a traditional single-tap calibration loop is shown in Figure 3. The pseudo-random sequence output by the DSM in the loop is used as the input training sequence of the calibration loop, and the estimated value of the loop gain factor obtained by the calibration loop is connected to the loop through the inversion operation, so that the loop bandwidth is not affected by non-ideal factors.

The two-tap adaptive LMS algorithm adopted in this embodiment:

Non-ideal factors such as loop dividers can lead to inaccurate loop gain factors estimated by the single-tap adaptive LMS algorithm. The non-ideal factor caused by the delay of the loop divider is shown in Figure 4. Assuming that the training signal x[n] injected into the DCO is a unit pulse, the period increment of the DCO output signal is the duration T _ref , the amplitude K A rectangular pulse of _T.

In the next reference cycle, x[n] becomes zero, so the phase jump variable remains to its final peak value NK _T . As shown in (a) of Figure 4, assuming that the loop divider has no delay, the output signal of the DCO is sub-sampled by the divider and then multiplied by the TDC gain K _TDC . The sequence d[n] is delayed A training signal x[n] with a reference clock period and an amplitude that is expanded by a gain factor G times, the single-tap LMS algorithm can accurately predict the loop gain factor G at this time.

As shown in (b) of Figure 4, in practice, there is a delay in the loop divider. Since the loop divider sub-samples the output signal of the DCO once per reference clock cycle, the loop divider Due to the existence of delay, the phase jump variable has not reached its peak value when it is sub-sampled by the frequency divider after one reference clock cycle when the value of the training sequence x[n] changes, so the sequence d[n] is in the training sequence x[n] After one reference clock cycle changes, the value of is smaller than the loop gain factor G, and the loop gain factor G predicted by the single-tap LMS algorithm has a large error at this time. Due to the existence of the delay of the loop divider, the output signal of the DCO is subsampled by the divider again after the two reference clock cycles changed by x[n] and multiplied by the TDC gain K _TDC , the obtained d[ n] value is not zero. Since the phase jump variable NK _T is constant, the sum of the forward instantaneous d[n] values obtained by these two reference clock cycles is exactly equal to the loop gain factor G.

In this embodiment, two calibration loops of the LMS algorithm are used instead of a single calibration loop of the LMS algorithm to estimate the loop bandwidth, as shown in FIG. 5 . Among them, the input of one loop is the original training sequence x[n] without delay processing, and the input of the other loop is the training sequence delayed by one reference clock cycle. Both calibration loops generate corresponding After the estimated value of the loop gain factor g[k], the accurate estimated value of the loop gain factor G is obtained by adding it up, and it is connected to the loop through the inversion operation, and finally the bandwidth estimation result is obtained without the delay of the loop divider, etc. Bandwidth calibration loop affected by non-idealities.

In summary, the present invention provides an adaptive background calibration method for the bandwidth of an all-digital phase-locked loop, which reduces the sensitivity of the loop bandwidth to the analog parameters in the loop by using an all-digital automatic control loop, so that the The bandwidth remains constant. The calibration algorithm in the present invention adopts a two-tap LMS algorithm. Compared with the single-tap LMS algorithm, the problem of inaccurate estimation results caused by non-ideal factors such as loop divider delay can be eliminated. At the same time, the algorithm adopts floating-point number operation. Compared with fixed-point number operation, floating-point number operation has higher precision and can represent a much larger range, which can more accurately track the change of loop bandwidth.

The parts that are not described in detail in the present invention are known techniques of those skilled in the art.

The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make many modifications and changes according to the concept of the present invention without creative efforts. Therefore, all technical solutions that can be obtained by those skilled in the art through logical analysis, reasoning or limited experiments on the basis of the prior art according to the concept of the present invention shall fall within the protection scope determined by the claims.

Claims (7)

1. an adaptive background calibration method for all-digital phase-locked loop bandwidth, is characterized in that, described all-digital phase-locked loop comprises: variable phase accumulator VPA, reference phase accumulator RPA, automatic frequency calibration module AFC , numerically controlled oscillator DCO, digital loop filter DLF, time-to-digital converter TDC, delta-sigma modulator DSM and subtractor; The calibration method includes the following steps: First, for the all-digital phase-locked loop, determine its loop gain, the expression is:

In this formula, N is the frequency division ratio of the phase-locked loop, which means that the frequency divider accumulates N cycles of the numerical control oscillator DCO output signal in one reference clock cycle, and K _T and K _TDC are the numerical control oscillator DCO and time- Gain of digital converter TDC, α and β are loop filter parameters; Then, using the normalized gain frequency of the loop bandwidth to approximate the loop bandwidth, the loop bandwidth is expressed as:

In this formula, f _ref is the reference frequency of the phase-locked loop, and the loop gain factor G=NK _T K _TDC ; Finally, by introducing two calibration loops based on the LMS algorithm, the loop gain factor is estimated, and then the loop gain factor g obtained by the estimation is inserted into the loop through the inversion operation, so that the loop The bandwidth becomes:

At this time, the loop bandwidth is only related to the filter parameter β and the PLL reference clock frequency _fref ; Among them, two calibration loops based on the LMS algorithm are used. The input of one loop is the training sequence without delay processing, and the input of the other loop is the training sequence that has been delayed by a reference clock cycle. , after the two calibration loops both generate the corresponding estimated value of the loop gain factor, the two are added together to obtain the final estimated value of the loop gain factor, and are connected to the loop through the inversion operation, and finally the bandwidth is not affected. An all-digital phase-locked loop loop affected by ideality factors. 2. a kind of self-adaptive background calibration method for all-digital phase-locked loop bandwidth according to claim 1, is characterized in that, described has adopted two calibration loops based on LMS algorithm, the input training sequence that it uses is a pseudo-random sequence, and the pseudo-random sequence is a pseudo-random sequence output by the delta-sigma modulator DSM between the digital loop filter DLF and the numerically controlled oscillator DCO. 3. a kind of adaptive background calibration method for full digital phase-locked loop bandwidth according to claim 1, is characterized in that, the gain of described numerically controlled oscillator DCO, it is specifically expressed as:

△C is the minimum variable capacitance value of the switched capacitor array of the numerically controlled oscillator, _Ctot is the capacitance of the numerically controlled oscillator resonant cavity, and _Tout is the period of the DCO output signal. 4. a kind of adaptive background calibration method for all-digital phase-locked loop bandwidth according to claim 1, is characterized in that, the gain of described time-to-digital converter TDC, it is specifically expressed as:

In this formula, Δt _TDC is the resolution of the time-to-digital converter. 5 . An adaptive background calibration method for an all-digital phase-locked loop bandwidth according to claim 1 , wherein the non-ideal factors specifically include: process P, voltage V, and temperature T. 6 . 6. A kind of adaptive background calibration method for full digital phase-locked loop bandwidth according to claim 1, it is characterized in that, described variable phase accumulator VPA and reference phase accumulator RPA, it is used for frequency information is converted into phase information; The described automatic frequency calibration module AFC is used to compare the output value of the variable phase accumulator VPA and the reference clock cycle counter counter, to judge the magnitude relationship between the two, and then to change the coarse adjustment and middle adjustment of the numerically controlled oscillator DCO. control word; The numerically controlled oscillator DCO outputs a signal corresponding to a frequency according to the input multi-bit control word. 7. a kind of adaptive background calibration method for all-digital phase-locked loop bandwidth according to claim 6, is characterized in that, when described all-digital phase-locked loop loop starts to work, it specifically comprises following work process: First, the frequency of the output signal of the numerically controlled oscillator DCO is locked to the sub-band of the target frequency by the automatic frequency calibration module AFC to complete the calibration of the numerically controlled oscillator DCO coarse adjustment and middle adjustment control words; after the calibration is completed, the full digital lock The coarse adjustment and middle adjustment loops of the phase loop complete the locking; after the locking is completed, the phase detection loop adjusts the fine adjustment part of the DCO control word to lock it to the target frequency, wherein the phase detection loop includes: reference Phase accumulator RPA, variable phase accumulator VPA, time-to-digital converter TDC, digital loop filter DLF, delta-sigma modulator DSM and subtractor; Then, the fine-tuning loop of the all-digital phase-locked loop starts to work, which includes: the output signal CKV of the numerically controlled oscillator DCO after being divided by the frequency divider N enters the time-to-digital converter TDC and the variable phase accumulator respectively. VPA; the variable phase accumulator VPA counts the integer part of the period of the CKV after the DCO is divided by the frequency divider N, and the time-to-digital converter TDC quantizes the fractional part of the CKV; and then integrates the variable phase accumulator The output of VPA and time-to-digital converter TDC, wherein the output obtained after integration is the phase value of the output frequency CKV; Finally, the subtractor subtracts the reference phase and the output phase, and the obtained phase error is sent to the digital loop filter DLF. The digital loop filter DLF calculates a new numerical control oscillator DCO control word according to the phase error, where , the new numerical control oscillator DCO control word is sent to the input end of the numerical control oscillator DCO after passing through the delta-sigma modulator DSM; after the fine adjustment part of the numerical control oscillator DCO control word is calibrated, the all-digital phase-locked loop is completed. locking.

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