CN114883301A - Chiplet-based microsystem reconfigurable network topology structure and implementation method - Google Patents

Abstract

The invention belongs to the technical field of electronic circuits, and particularly relates to a reconfigurable network topology structure and an implementation method thereof, which mainly solve the problems of the existing micro-system based on a large SoC that the functions are solidified, the expansibility is poor, the design period is long, and the cost is high. The reconfigurable network topology control circuit comprises a reconfigurable network topology control unit (1), a bonding pad (2), a conical through silicon hole (3), a rewiring layer (4), a micro bump (5), a chip (6), a switch matrix (7) and a plurality of wafers (8); the reconfigurable network topology control unit and the switch matrix are integrated on a first layer of wafer, and the chipset is integrated on a second layer of wafer; the pad, the conical silicon through hole, the rewiring layer and the micro bump are used for achieving electrical interconnection of the microsystem, and the reconfigurable control unit is used for flexibly configuring the chip and achieving that one set of hardware can rapidly build one or more microsystems with multiple functions. The invention has high function reconstruction capability and expansion capability and can be used for micro-system design.

Description

Microsystem Reconfigurable Network Topology Structure and Implementation Method Based on Chiplet

technical field

The invention belongs to the technical field of electronic circuits, and in particular relates to a reconfigurable network topology structure and an implementation method, which can be used in a semiconductor micro-integrated system.

Background technique

Traditional SoC-based microsystems use a monolithic integration process to integrate a large number of transistors to build a system with specific functions.

It has the problems of functional solidification, process incompatibility, design difficulty, and high cost, and has gradually been unable to meet the multi-task concurrent requirements of the system. Chiplet is a general-purpose small-scale hard core IP with specific functions. The flexible combination of Chiplets can form a micro-system with flexible configuration to solve the design problems and cost problems based on large SoCs. It has wide application prospects in the fields of high-performance computing and radio frequency. . The patent document with the application number CN202111237938.1 discloses "An arbitrary routing radio frequency switch matrix", which realizes the routing of radio frequency signals from any input port to any output port through an N-port radio frequency switch matrix, but cannot realize system-level functional reconstruction . The patent document with the application number CN202111291800.X discloses "a three-dimensional multi-die interconnection network structure", which mainly realizes reducing the number of routing hops, shortening the transmission path, and reducing the network delay by reducing the network structure of the multi-die on the chip. The network also cannot realize the dynamic reconfiguration of system functions.

At present, the lack of a network topology to realize the functional reconstruction of the Chiplet microsystem is not only the key to the low reuse rate of Chiplet and the inability to give full play to the advantages of versatility and modularity, but also affects the versatility and poor scalability of the electronic system, restricting the Development of reconfigurable, scalable, multifunctional, and low-cost microsystems.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a chiplet-based microsystem reconfigurable network topology and implementation method to reduce costs, shorten the research and development cycle, improve the versatility of the microsystem, and meet diversified application requirements,

To achieve the above object, the technical scheme of the present invention includes the following:

1. A chiplet-based microsystem reconfigurable network topology, characterized in that, comprising a reconfigurable network topology control unit (1), a pad (2), a tapered through-silicon via (3), a rewiring layer (4), a micro-bump (5), a Chiplet (6), a switch matrix (7) and a plurality of wafers (8); the reconfigurable network topology control unit (1) and the switch matrix (7) are integrated in the first On one layer of wafers, Chiplets (6) are integrated on the second layer of wafers, and the two layers of wafers are integrated in a three-dimensional manner; pads (2), tapered TSVs (3), rewiring layers (4) ), the micro-bumps (5) are used to realize the electrical interconnection of the micro-system; the reconfigurable control unit (1) is used to flexibly configure the Chiplet (6), and realize one or more micro-systems with multiple functions quickly constructed by a set of hardware. system.

Further, the reconfigurable network topology control unit (1) includes an encoding-decoding circuit and a switch matrix state storage circuit, the encoding-decoding circuit is used to generate an encoding sequence and an enable signal, and the encoding sequence is decoded by the decoding circuit to generate a control The signal is transmitted to the switch matrix storage circuit and stored, and when the switch control signal jumps, the jumped control signal is transmitted to the switch matrix (7).

Further, the switch matrix (7) includes: a switch tube drive circuit, a switch tube, a signal filter circuit, a signal conditioning circuit, and a signal hold circuit, the switch tube drive circuit is used to enhance the drive capability of the switch tube control signal, and its output signal Transmission to the switch tube; the switch tube is used to control the circuit on/off of the reconfigurable network topology. After the switch tube is turned on, it transmits the enable signal generated by the encoding-decoding circuit, and the enable signal is transmitted to the signal filtering circuit; The signal filter circuit is used to filter out the noise in the enable signal, and the filtered enable signal is transmitted to the signal conditioning circuit; the signal conditioning circuit is used to modulate the waveform of the enable signal, and the modulated enable signal It is transmitted to the signal holding circuit; the signal holding circuit is used to store the enable signal of each Chiplet, and when the enable signal jumps, the enable signal is transmitted to the corresponding Chiplet.

Further, the Chiplet (6) is a functional chip prepared by using Si or GaAs or GaN material and using a CMOS or BiCMOS or Bipolar process, which is connected to the reconfigurable network topology control unit (1) to form a microsystem;

2. a realization method based on the microsystem reconfigurable network topology of Chiplet, is characterized in that, comprises the steps:

1) Prepare tapered TSVs on wafer 1:

The through hole is etched on the first layer of silicon wafer by laser drilling technology, and the polymer is filled in the through hole, and then the polymer in the hole is ablated with a laser to form a through hole with an insulating inner wall;

A TiN barrier layer is prepared in the through hole by physical vapor deposition (PVD), and a seed layer is prepared on the TiN barrier layer by physical vapor deposition (PVD) process. Through silicon via;

2) Thinning the first silicon wafer prepared with the conical TSVs, that is, using chemical mechanical polishing process CMP to polish the front surface, and then using the back grinding process to grind the back surface, so that the two conical TSVs are polished. exposed end;

3) The switch matrix and reconfigurable network control unit are successively integrated on the first layer of silicon wafer by CMOS process, and then the rewiring layer is prepared on the first layer of wafer by Damascus process to realize the switch matrix and tapered TSV the electrical interconnection to transmit the enable signal;

4) After the tapered through-silicon vias, the reconfigurable network control unit, the switch matrix, and the rewiring layer are prepared on the first-layer wafer, the first alignment marker is produced;

5) Prepare a chamber on the surface of the second layer wafer by dry etching process to integrate Chiplet; then use SiO ₂ to passivate the bottom of the chamber and make a second alignment mark on the surface of the wafer, using For precise positioning of Chiplet placement;

6) Place the Chiplet in the chamber according to the second alignment marker;

7) Prepare the electrical interconnection structure on the second-layer wafer, that is, first use the Damascus process to prepare the re-wiring layer, and then use the re-wiring layer to lead out the enabling end of the Chiplet to the surface of the second-layer wafer; Preparation of bumps above the redistribution layer to enable electrical interconnection with tapered TSVs and to bond wafers;

8) Fill the chamber with epoxy to fix the Chiplet;

9) The backside of the second-layer wafer is thinned by a back grinding process, and a third alignment marker is made;

10) According to the positions of the first alignment marker and the third alignment marker, the first-layer wafer and the second-layer wafer are bonded at 300°C using a bump bonding process, and a laser cutting process is used. slicing it;

11) Integrate and encapsulate the modules obtained by dicing, and obtain a functionally reconfigurable microsystem based on Chiplet.

Compared with the prior art, the present invention has the following advantages:

First, the present invention effectively overcomes the shortcomings of the existing SoC-based micro-system function solidification and low utilization of hardware resources due to dynamically calling Chiplets through reconfigurable network topology. Moreover, the system design efficiency and robustness are improved, and the research and development cost of the microsystem is reduced, and a microsystem with higher function reconfigurability and higher reliability is obtained.

Second, the present invention effectively overcomes the disadvantage of poor scalability of the existing microsystems and effectively improves the flexibility of the expansion of the microsystems due to the use of a reconfigurable network topology that can be cascaded arbitrarily to expand the microsystem.

Third, the present invention effectively overcomes the shortcomings of the existing SoC-based microsystems that are incompatible in technology and difficult to optimize performance due to the chiplet construction system prepared by different materials. The present invention not only effectively improves the heterogeneous characteristics of the microsystem, but also Reduced design costs and a more flexible approach to performance optimization.

Fourth, the present invention integrates multiple wafers through the three-dimensional wafer-level integration technology, effectively overcomes the shortcomings of the existing chip-level integration technology, such as poor product performance uniformity and low preparation efficiency, and effectively improves the batch preparation of microsystems. performance consistency and efficiency.

Description of drawings

1 is a three-dimensional structural diagram of a basic network topology unit with reconfigurability and scalability of the present invention;

Fig. 2 is the basic network topology unit structure diagram with reconfigurability and scalability of the present invention;

Fig. 3 is the network topology unit structure diagram of the first embodiment after the structure of Fig. 1 is expanded according to the present invention;

Fig. 4 is the network topology unit structure diagram of the second embodiment after the present invention expands the structure of Fig. 1;

Fig. 5 is the network topology unit structure diagram of the third embodiment after the present invention expands the structure of Fig. 1;

Fig. 6 is the three-dimensional structure schematic diagram of Fig. 4;

FIG. 7 is a flow chart showing the realization of the micro-system constructed by the network topology of the expanded three-dimensional structure of the present invention.

The specific plan is as follows

The embodiments of the present invention will be further described below with reference to the accompanying drawings.

1, the basic network topology unit of the present invention includes a reconfigurable network topology control unit 1, a pad 2, a tapered TSV 3, a redistribution layer 4, a micro-bump 5, a Chiplet 6, a switch matrix 7 and Multiple wafers 8; this example employs but is not limited to two wafers. The reconfigurable network topology control unit 1 and the switch matrix 7 are integrated on the first-layer wafer, the Chiplet 6 is integrated on the second-layer wafer, and the two layers of wafers are integrated in a three-dimensional manner; the pad 2, the tapered Through silicon vias 3, redistribution layers 4, and micro-bumps 5 are used to realize the electrical interconnection of the microsystem. Specifically, after the control unit generates the control signal, the signal is first transmitted to the pad 2, and then to the redistribution layer on the first-layer wafer to realize the redistribution of the signal; then, the signal flows through the first-layer wafer The tapered TSVs in the circle then enter the signal path formed by the switch matrix reconstruction, and finally enable the signal to flow through the vertical TSVs and micro-bumps in the second-layer wafer to enter the function Chiplet. The reconfigurable control unit 1 is used to flexibly configure the Chiplet 6. Specifically, when the application requirements change, the reconfigurable network topology control unit generates a coding sequence and an enable signal, and the coding sequence is decoded to generate a control switch matrix The switch control signal of the switch tube and form a signal path; after the enable signal enters the signal path, it reaches the function Chiplet after filtering, modulation, storage, etc. Control cells, pads, tapered TSVs, redistribution layers, microbumps, chiplets, switch matrices, and two wafers to rapidly build functionally reconfigurable microsystems.

In order to explain the working principle of the reconfigurable and scalable network topology more clearly, the present invention takes the simplified schematic diagram shown in FIG. 2 as an example to illustrate the working principle of the basic network topology unit, wherein C1 and C2 represent two Chiplets, S11-S16 represent 6 switch tubes in the switch matrix. When application requirements change, the 6 switches in the switch matrix are dynamically configured by the reconfigurable network topology control unit 1 to generate different enabling signal flow paths, so as to flexibly call Chiplets and dynamically reconfigure microsystem functions. Specifically, when the microsystem only needs to call the first function ChipletC1, under the configuration of the reconfigurable network topology control unit 1, the first three switches S11, S12, and S13 are closed, and the last three switches S14, S15, and S16 are closed. On; when the microsystem only needs to call the second function Chiplet C2, under the configuration of the reconfigurable network topology control unit 1, the fourteenth switch S14 and the sixteenth switch S16 are closed, and the eleventh switch S11 and the twelfth switch S11 and the twelfth switch are closed. The switch S12, the thirteenth switch S13, and the fifteenth switch S15 are turned off; when the microsystem needs to call the first function Chiplet C1 and the second function C2, under the adjustment of the reconfigurable network topology control unit, the first The eleventh switch S11, the fifteenth switch S15, and the sixteenth switch S16 are closed, and the twelfth switch S12, the thirteenth switch S13, and the fourteenth switch S14 are open. When the microsystem does not need to call the first function Chiplet C1 and the second function Chiplet C2, the thirteenth switch S13 is closed, the eleventh switch S11, the twelfth switch S12, the fourteenth switch S14, and the fifteenth switch S15, the sixteenth switch S16 is turned off.

Taking the structure of FIG. 1 as an example, through the flexible configuration of the switch matrix in the reconfigurable network topology, multiple working modes can be reconfigured. This example gives but is not limited to the following three:

The first is to use the basic network topology unit and cascade at the expansion point to realize the expansion of the microsystem, that is, to expand the Chiplets in Figure 1 to 4, as shown in Figure 3. Through different combinations of these four Chiplets, different functional reconstructions of the microsystem can be realized:

When the microsystem only calls one function Chiplet, that is, only the first function Chiplet C1 or the second function Chiplet C2 or the third function Chiplet C3 or the fourth function Chiplet C4, four system functions can be reconstructed;

When the micro-system calls two functions Chiplet, namely the first function Chiplet C1 and the second function Chiplet C2, the first function Chiplet C1 and the third function Chiplet C3, the first function Chiplet C1 and the fourth function Chiplet C4, the first function Chiplet C1 and the fourth function Chiplet C4, When the second function Chiplet C2 and the third function Chiplet C3, the second function Chiplet C2 and the fourth function Chiplet C4, the third function Chiplet C3 and the fourth function Chiplet C4 are series, six system functions can be reconfigured;

When the micro-system calls three functions Chiplet, namely, the first function Chiplet C1 and the second function Chiplet C2 and the third function Chiplet C3, the first function Chiplet C1 and the second function Chiplet C2 and the fourth function Chiplet C4, When the second function Chiplet C2, the third function Chiplet C3 and the fourth function Chiplet C4, the three system functions can be reconfigured;

When the micro-system calls four function Chiplets, namely, when calling the first function Chiplet C1, the second function Chiplet C2, the third function Chiplet C3 and the fourth function Chiplet C4, one system function can be reconfigured.

The second is to extend the basic network topology unit in FIG. 1 into a network topology with 3 Chiplets, the structure of which is shown in FIG. 4 . Through different combinations of these three Chiplets, different functional reconstructions of the microsystem can be realized:

When the microsystem only calls one function Chiplet, that is, only calls the first function Chiplet C1 or the second function Chiplet C2 or the third function Chiplet C3, three system functions can be reconstructed;

When the micro-system calls two function Chiplets, namely the first function Chiplet C1 and the second function Chiplet C2, the first function Chiplet C1 and the third function Chiplet C3, the second function Chiplet C2 and the third function Chiplet C3, respectively, the Refactoring three system functions;

When the micro-system calls three function Chiplets, that is, when calling the first function Chiplet C1, the second function Chiplet C2 and the third function Chiplet C3, one system function can be reconfigured.

In the third type, a reconfigurable network integrating four basic network topology units in Fig. 1 is taken as an example to illustrate its reconfiguration working principle. As shown in Figure 5, where EN represents the enable signal entering the switch matrix, C1-C8 represent Chiplets with different functions, S11-S16, S21-S26, S31-S36, S41-S46 represent the switch tubes in the switch matrix:

When the micro-system needs to call the first, third, fifth and seventh functions Chiplets C1, C3, C5, and C7, the reconfigurable network topology network control unit generates a coding sequence and an enable signal EN. After the coding sequence is decoded by the decoding circuit, a control signal is generated and transmitted to the switch matrix storage circuit and stored. When the switch control signal jumps, the jumped control signal is transmitted to the switch matrix. After filtering and conditioning, the control signal is It is transmitted to the switch driving circuit to drive the zero-first switch S01, the eleventh switch S11, the twelfth switch S12, the thirteenth switch S13, the zero-second switch S02, the twenty-first switch S21, and the twenty-second switch S22 , the twenty-third switch S23, the zero-third switch S03, the thirty-first switch S31, the thirty-second switch S32, the thirty-third switch S33, the zero-fourth switch S4, the forty-first switch S41, the fourth switch The twelfth switches S42 and the forty-third S43 are closed, the other switches are open, and the guide enable signal EN is transmitted to the first, third, and second layers of the wafer through the tapered through-silicon vias in the first layer of wafers. 5. The enable terminal of the seventh function Chiplet C1, C3, C5, and C7 to build a microsystem with A function;

When the micro-system needs to call the second, fourth, sixth, and eighth functions Chiplets C2, C4, C6, and C8, the reconfigurable network topology network control unit generates a coding sequence and an enable signal EN. After the coding sequence is decoded by the decoding circuit, a control signal is generated and transmitted to the switch matrix storage circuit and stored. When the switch control signal jumps, the jump control signal is transmitted to the switch matrix. After filtering and conditioning, the control signal is transmitted to the switch matrix. The switch drive circuit drives the zero-first switch S01, the fourteenth switch S14, the fifteenth switch S15, the zero-second switch S2, the twenty-fourth switch S24, the twenty-fifth switch S25, the zero-third switch S3, the The thirty-fourth switch S34, the thirty-fifth switch S35, the zero-fourth switch S04, the forty-fourth switch S44, and the forty-fifth switch S45 are closed, and the other switches are open, and the enable signal EN is guided through the first-layer wafer The tapered TSVs in the second-layer wafer are transferred to the enable terminals of the second, fourth, sixth, and eighth function Chiplets C2, C4, C6, and C8 to build a microsystem with B function;

When the microsystem needs to call the functions Chiplets C1-C8, the reconfigurable network topology network control unit generates a coding sequence and an enable signal EN. After the coding sequence is decoded by the decoding circuit, a control signal is generated and transmitted to the switch matrix storage circuit and stored. When the switch control signal jumps, the jump control signal is transmitted to the switch matrix. After filtering and conditioning, the control signal is transmitted to the switch matrix. The switch driving circuit drives the zero-first switch S01, the eleventh switch S11, the fifteenth S15, the sixteenth switch S16, the zero-second switch S02, the twenty-first switch S21, the twenty-fifth switch S25, the second switch Sixteen switch S26, zero third switch S03, thirty first switch S31, thirty first switch S35, thirty sixth switch S36, zero fourth switch S04, forty first switch S41, forty fifth switch S45, the forty-sixth switch S46 is closed, the other switches are open, and the enable signal EN is guided to be transmitted to the enable terminals of the function Chiplets C1-C8 in the second-layer wafer through the tapered TSVs in the first-layer wafer , to build a microsystem with C functions;

Similarly, when the microsystem needs to reconfigure other functions, the reconfigurable network topology network control unit generates a coding sequence and an enable signal EN, the control signal controls the switch matrix to form a signal path, and the enable signal is processed to achieve the function Chiplet through the signal path. , plays the role of the dynamic configuration function Chiplet to realize the dynamic reconstruction of the microsystem function. The reconfigurable network topology shown in FIG. 4 has symmetry, which can keep the same time when the enable signal EN is transmitted to different key Chiplets, and improve the response symmetry of the Chiplets.

Compared with the existing method of turning off the enable signal by using the above switch matrix to control the flow of the enable signal, when the system function is reconfigured, the enable signal can be configured separately for each function chiplet in the network, that is, when the microsystem does not When any function Chiplet in the network needs to be called, the calls to other function Chiplets are not affected, and it has higher refactoring flexibility.

Referring to FIG. 6 , the expanded network topology unit structure of FIG. 4 is integrated in the vertical direction to obtain a three-dimensional structure, that is, 4 switch matrices, 1 control unit, 8 function Chiplets are integrated on two wafers respectively, and 4 layers of rewiring layer, 32 microbumps, 24 tapered TSVs of which:

Integrate 24 tapered TSVs, 16 micro-bumps, and 2 rewiring layers on the first-layer wafer; according to the cross structure, integrate the first switch matrix, the second switch matrix, the third switch matrix, the third switch matrix, and the third switch matrix. Four switch matrix; then integrate the control unit above the switch matrix;

According to the cross structure, 2 functional chiplets are integrated in the four directions of the second layer wafer; 2 layers of rewiring layers and 16 micro-bumps are integrated;

The first-layer wafer and the second-layer wafer are bonded to obtain a microsystem with a three-dimensional structure.

When the micro-system needs to work, the signal generated by the control unit controls the switch matrix to form a signal path, and guides the enable signal EN to flow through the tapered TSVs on the first layer of wafers, then through the micro-bumps, and then through the second The surface of the layer wafer is rewired, and finally the enabling end of the corresponding function chiplet in the second layer wafer is reached. Through the combination of different chiplets, different functions of the microsystem can be reconstructed.

Referring to FIG. 7 , the method for making a three-dimensional structure of a reconfigurable network topology according to the present invention provides the following three embodiments

Embodiment 1, making and integrating 1 basic network topology unit structure, N reconfigurable microsystems with 2 function Chiplets;

In step 1, tapered TSVs are prepared on the first-layer silicon wafer.

Since the enable signal in the reconfigurable network topology needs to be transmitted through the tapered TSVs, the tapered TSVs for signal transmission have the characteristics of low density and small number, so the cost-effective laser drilling technology is used in the first The tapered TSV is etched on a layer of silicon wafer, and the specific implementation is as follows:

1.1) Using a laser with a frequency of 30KHz, a wavelength of 355nm, a pulse width of 50ns, a pulse energy of 300μj and a spot diameter of 15μm, 6 tapered TSVs were etched on a silicon wafer with a thickness of 155μm;

1.2) Fill the polymer in the through hole, and ablate the polymer in the 6 through holes with a laser with a power of 1KW to form a through hole with an insulating inner wall;

1.3) The inert gas is argon, the sputtering target is TiN, the radio frequency source frequency is 13.56MHz, the pre-sputtering power is 40W, the sputtering power is 20W, and the sputtering time is 10min. Sputtering TiN barrier layer under conditions;

1.4) A tapered TSV seed layer is prepared on the barrier layer by a physical vapor deposition (PVD) process, and then CuSO ₄ with a concentration of 0.5 mol/L is used as the electroplating solution to fill the via hole on the seed layer, and finally a tapered silicon hole is obtained. through hole.

Step 2, performing a thinning process on the first-layer wafer prepared with the tapered TSVs.

In order to enable signal transmission, both ends of the tapered TSV need to be completely exposed. Therefore, the chemical mechanical polishing process CMP is used to polish the front side of the first-layer wafer to reduce its thickness. The specific implementation is as follows:

2.1) Place the first layer of wafer on the silicon wafer fixture, and use a polishing solution composed of an acidic chemical solution with a pH value of 3.5 and SiO ₂ particles with a diameter of 100 μm to polish the wafer 1, so that the conical through-silicon holes are formed. Both ends are exposed;

2.2) Using the electroplating ball-planting process to prepare cylindrical micro-bumps at the lower port of the conical through-silicon hole, the electroplating material is Cu, and the electroplating rate is 0.2 μm/min.

Step 3, integrating a control unit on the thinned first-layer wafer.

Under the condition of annealing temperature of 1000°C, a CMOS process is used to prepare a switch matrix through photolithography, exposure, development, deposition and etching on the front side of the first wafer, and then secondary photolithography and exposure are performed on the switch matrix. , developing, depositing and etching to prepare a control unit;

In step 4, a rewiring layer is prepared on the first layer wafer after integrating the control unit.

4.1) The rewiring layer is prepared by the Damascus process, that is, silicon nitride is used to deposit a diffusion barrier layer on the surface of the first-layer wafer, and then a SiO dielectric layer is deposited _;

4.2) patterning on the surface of the _SiO2 dielectric layer, and etching the excess dielectric layer after the patterning;

4.3) Deposit a diffusion barrier layer and a seed layer on the surface of the etched patterned dielectric layer, perform electroplating and chemical mechanical polishing again, and finally obtain a rewiring layer.

In step 5, a first alignment marker is prepared on the surface of the first layer wafer after the preparation of the redistribution layer.

The first cross-shaped alignment marker is prepared on the passive area of the first layer wafer surface by the positive labeling process, and the line length is 140 μm and the line width is 30 μm.

In step 6, a chamber is prepared on the second layer wafer.

6.1) Prepare the chamber on the surface of the two-layer wafer by dry etching process;

6.2) Use SiO ₂ as the insulating medium to passivate the bottom of the chamber to achieve electrical insulation between the Chiplet and the wafer.

In step 7, a second alignment marker is prepared at the bottom of the second-layer wafer chamber.

A second cross-shaped alignment mark was prepared at the center of the bottom of the second-layer wafer chamber by a positive labeling process. The cross mark had a line length of 140 μm and a line width of 30 μm.

Step 8, placing 2N chiplets in the second-layer wafer chamber.

The functional 2N chiplets are placed on the aligner, and the 2N functional chiplets are placed in the chamber according to the positions of the cross alignment markers in the second-layer wafer chamber.

In step 9, an interconnect structure is prepared on the surface of the second-layer wafer on which the Chiplets are placed.

9.1) Use the Damascus process to prepare the rewiring layer, that is, first use silicon nitride to deposit a diffusion barrier layer on the surface of the second-layer wafer, and then deposit a SiO ₂ dielectric layer;

9.2) Perform patterning on the surface of the dielectric layer, and etch the excess dielectric layer after the patterning;

9.3) Deposit a diffusion barrier layer and a seed layer on the surface of the patterned dielectric layer, and then perform electroplating;

9.4) The electroplating layer is polished by a chemical mechanical polishing process, and finally a rewiring layer is obtained.

9.5) Using Cu material on the second-layer wafer by the ball-mounting process, micro-bumps in the shape of a cylinder are electroplated at a plating rate of 0.3 μm/min.

Step 10, filling the second-layer wafer chamber with micro-bumps.

First use epoxy resin as material to fill the filling chamber, and then use chemical mechanical polishing process to remove epoxy resin higher than the surface of the second layer of wafer;

Step 11, thinning the backside of the second-layer wafer.

The backside of the second layer of wafers is first ground by rough grinding, then finely ground when the thickness of the second layer of wafers is 100μm, and the backside of the second layer of wafers is polished by chemical mechanical polishing when the thickness of the second layer of wafers is 40μm .

In step 12, a third bit marker is prepared on the backside of the thinned second-layer wafer.

A third cross-shaped alignment mark is prepared on the backside of the second-layer wafer by a positive labeling process. The line length of the cross mark is 140 μm and the line width is 30 μm.

Step 13, bonding the wafers.

Under the conditions of a bonding pressure of 200KPa, a bonding temperature of 300°C, and a temperature rise rate of 6°C/min, two wafers were bonded by a thermocompression bonding process.

Step 14, dicing and packaging the bonded wafer.

The bonded wafer is cut by a laser with a power of 1KW to obtain N three-dimensional circuit modules, and the N three-dimensional modules obtained by dicing are integrated on the packaging substrate and packaged with the outer shell to obtain N three-dimensional circuit modules with two chiplets. Functionally reconfigurable microsystems.

In Example 2, N reconfigurable microsystems integrating 2 basic network topology units and having 4 functional chiplets are produced.

In step 1, tapered TSVs are prepared on the first-layer silicon wafer.

Under the conditions of a laser frequency of 30KHz, a wavelength of 355nm, a pulse width of 50ns, a pulse energy of 300μj and a spot diameter of 15μm, a laser was used to etch 12 tapered TSVs on a silicon wafer with a thickness of 100μm, and Fill these through holes with polymer, and then use a laser with a power of 1KW to ablate the polymer in 12 through holes to form through holes with insulating inner walls;

The inert gas is argon, the sputtering target is TiN, the radio frequency source frequency is 13.56MHz, the pre-sputtering power is 50W, the sputtering power is 30W, and the sputtering time is 5min. A TiN barrier layer was sputtered on the insulating surface of the through hole; then a tapered TSV seed layer was prepared on the barrier layer by physical vapor deposition (PVD) process, and CuSO ₄ with a concentration of 1 mol/L was selected as the electroplating solution on the seed layer. Via filling, resulting in tapered TSVs.

In step 2, thinning is performed on the first-layer wafer prepared with the tapered TSVs.

The specific implementation of this step is the same as that of step 2 in Embodiment 1.

Step 3: Integrate a control unit on the thinned first-layer wafer.

The specific implementation of this step is the same as that of step 3 in Embodiment 1.

In step 4, a rewiring layer is prepared on the first-layer wafer after integrating the control unit.

The specific implementation of this step is the same as that of step 4 in Embodiment 1.

In step 5, a first alignment marker is prepared on the surface of the first layer wafer after the preparation of the rewiring layer.

The specific implementation of this step is the same as that of step 5 in Embodiment 1.

In step 6, a chamber is prepared on the second layer of wafers.

The specific implementation of this step is the same as that of step 6 in Embodiment 1.

In step 7, a second alignment marker is prepared at the bottom of the second-layer wafer chamber.

The specific implementation of this step is the same as that of step 7 in Embodiment 1.

Step 8, place the Chiplet in the second-layer wafer chamber.

The 4N functional chiplets are placed on the aligner, and the 4N functional chiplets are placed in the chamber according to the positions of the cross alignment markers in the second layer wafer chamber.

In step 9, an interconnection structure is prepared on the surface of the second-layer wafer on which the Chiplets are placed.

9a) using the Damascus process to prepare the rewiring layer, that is, firstly using Si ₃ N ₄ to deposit a diffusion barrier layer on the surface of the second wafer, and then depositing a SiO ₂ dielectric layer;

9b) patterning the surface of the dielectric layer, and etching the excess dielectric layer after the patterning;

9c) Deposit a diffusion barrier layer and a seed layer on the surface of the patterned dielectric layer, and then perform electroplating, and use a chemical mechanical polishing process to polish the electroplating layer to finally obtain a rewiring layer.

9d) Using Cu material on the second-layer wafer by a ball-mounting process, micro-bumps in the shape of a cylinder are electroplated at a plating rate of 0.4 μm/min.

Step ten, filling the second-layer wafer chamber with micro-bumps.

The specific implementation of this step is the same as that of step 10 in Embodiment 1.

The eleventh step is to thin the backside of the second-layer wafer.

The backside of the second layer of wafer is first ground by rough grinding, and then finely ground when the thickness of the second layer of wafer is 80μm, and the backside of the second layer of wafer is polished by chemical mechanical polishing when the thickness of the second layer of wafer is 30μm .

In step 12, a third bit marker is prepared on the backside of the thinned second-layer wafer.

The specific implementation of this step is the same as that of step 12 in Embodiment 1.

Step thirteen, bonding the wafers.

Under the conditions of a bonding pressure of 200KPa, a bonding temperature of 200°C, and a temperature rise rate of 5°C/min, two wafers are bonded by a thermocompression bonding process.

Step fourteen, dicing and packaging the bonded wafer.

The bonded wafer is cut by a laser instrument with a power of 1KW, and N three-dimensional circuit modules are obtained, and N modules containing 4 functional Chiplets are obtained by dicing, and the N modules are integrated on the packaging substrate. After encapsulating the shell again, N functional reconfigurable microsystems integrating 4 chiplets are obtained.

Example 3: N reconfigurable microsystems with 1 basic network topology unit extended and 3 functional chiplets are fabricated.

In step A, tapered TSVs are prepared on the first-layer silicon wafer.

Using laser drilling technology to etch tapered TSVs on the first layer of silicon wafers, the specific implementation is as follows:

A1) Using a laser with a frequency of 30KHz, a wavelength of 300nm, a pulse width of 50ns, a pulse energy of 300μj and a spot diameter of 10μm, 24 tapered TSVs were etched on a silicon wafer with a thickness of 100μm;

A2) Fill the polymer in the through holes, and ablate the polymer in the 24 through holes with a laser with a power of 1KW to form through holes with insulating inner walls;

A3) Prepared by physical vapor deposition PVD, the inert gas is argon, the sputtering target is TiN, the radio frequency source frequency is 13.56MHz, the pre-sputtering power is 60W, the sputtering power is 40W, and the sputtering time is 5min. Sputtering TiN barrier layer under conditions;

A4) Use physical vapor deposition (PVD) process to prepare a tapered through-silicon hole seed layer on the barrier layer, and then select CuSO4 with a concentration of _1.5mol /L as the electroplating solution to fill the through-hole on the seed layer, and finally obtain a tapered silicon hole through hole.

In step B, thinning is performed on the first-layer wafer prepared with the tapered TSVs.

In order to enable signal transmission, both ends of the tapered TSV need to be completely exposed. Therefore, the chemical mechanical polishing process CMP is used to polish the front side of the first-layer wafer to reduce its thickness. The specific implementation is as follows:

B1) Place the first-layer wafer on the silicon wafer holder, and use the polishing solution composed of an acidic chemical solution with a pH value of 4 and SiO ₂ particles with a diameter of 800 μm to polish both sides of the first-layer wafer to make the cone Both ends of the through-silicon via are exposed;

B2) Using the electroplating ball-planting process to prepare cylindrical micro-bumps at the lower port of the conical through-silicon hole, the electroplating material is Cu-Pb, and the electroplating rate is 0.2 μm/min.

In step C, a control unit is integrated on the thinned first-layer wafer.

The specific implementation of this step is the same as that of step 3 in Embodiment 1.

In step D, a rewiring layer is prepared on the first layer of wafer after integrating the control unit.

The specific implementation of this step is the same as that of step 4 in Embodiment 1.

In step E, a first alignment marker is prepared on the surface of the first layer wafer after the preparation of the redistribution layer.

The specific implementation of this step is the same as that of step 5 in Embodiment 1.

In step F, the chamber is prepared on the second layer wafer.

The specific implementation of this step is the same as that of step 6 in Embodiment 1.

In step G, a second alignment marker is prepared at the bottom of the second-layer wafer chamber.

The specific implementation of this step is the same as that of step 7 in Embodiment 1.

In step H, a chiplet is placed in the second-layer wafer chamber.

The 3N functional chiplets are placed on the aligner, and the 3N functional chiplets are placed in the chamber according to the positions of the cross alignment markers in the second layer wafer chamber.

In step 1, an interconnect structure is prepared on the surface of the second-layer wafer on which the Chiplets are placed.

I1) The rewiring layer is prepared by the Damascus process, that is, silicon nitride is first used to deposit a diffusion barrier layer on the surface of the second-layer wafer, and then a _SiO2 dielectric layer is deposited; then patterning is performed on the surface of the dielectric layer, and the patterned After the redundant dielectric layer is etched;

I2) successively deposit a diffusion barrier layer and a seed layer on the surface of the patterned dielectric layer, and perform electroplating on the surface of the seed layer and then use a chemical mechanical polishing process to polish the electroplating layer to finally obtain a rewiring layer;

I3) The Cu-Sn material is used on the second-layer wafer by the ball-mounting process, and the cylindrical micro-bumps are electroplated at a plating rate of 0.2 μm/min.

Step J, filling the second-layer wafer chamber with micro-bumps.

The specific implementation of this step is the same as that of step 10 in Embodiment 1.

In step K, the back surface of the second layer wafer is thinned.

The specific implementation of this step is the same as that of step 11 in Embodiment 1.

In step L, a third bit marker is prepared on the backside of the thinned second-layer wafer.

The specific implementation of this step is the same as that of step 12 in Embodiment 1.

Step M, bonding the wafers.

Under the conditions of a bonding pressure of 200KPa, a bonding temperature of 300°C, and a temperature rise rate of 6°C/min, two wafers were bonded by a thermocompression bonding process.

In step N, the bonded wafers are diced and packaged.

Use a laser with a power of 1KW to cut the bonded wafer to obtain a circuit module, obtain N modules integrated with 3 Chiplets by dicing, integrate the N modules on the packaging substrate, and then package the shell to obtain N functional reconfigurable microsystems integrating 3 chiplets.

The above descriptions are only three specific examples of the present invention, and do not constitute any limitation to the present invention. Obviously, for those skilled in the art, after understanding the content and principles of the present invention, they may not deviate from the principles of the present invention, In the case of the structure, various modifications and changes in form and details are made, but the modifications and changes of these basic inventive concepts still fall within the protection scope of the claims of the present invention.

Claims (10)

1. A chiplet-based microsystem reconfigurable network topology, characterized in that, comprising a reconfigurable network topology control unit (1), a pad (2), a tapered through-silicon via (3), a rewiring layer (4), a micro-bump (5), a Chiplet (6), a switch matrix (7) and a plurality of wafers (8); the reconfigurable network topology control unit (1) and the switch matrix (7) are integrated in the first On one layer of wafers, Chiplets (6) are integrated on the second layer of wafers, and the two layers of wafers are integrated in a three-dimensional manner; pads (2), tapered TSVs (3), rewiring layers (4) ), the micro-bumps (5) are used to realize the electrical interconnection of the micro-system; the reconfigurable control unit (1) is used to flexibly configure the Chiplet (6), and realize one or more micro-systems with multiple functions quickly constructed by a set of hardware. system. 2. The method according to claim 1, wherein the reconfigurable network topology control unit (1) comprises an encoding-decoding circuit, a switch matrix state storage circuit, and the encoding-decoding circuit is used to generate the encoding sequence and the The enable signal, the coding sequence is decoded by the decoding circuit to generate a control signal and transmit it to the switch matrix storage circuit for storage. When the switch control signal jumps, the jumped control signal is transmitted to the switch matrix (7). 3. The method according to claim 1, wherein the switch matrix (7) comprises: The switch tube driving circuit is used to enhance the driving capability of the switch tube control signal, and its output signal is transmitted to the switch tube; The switch tube is used to control the circuit on and off of the reconfigurable network topology. After the switch tube is turned on, it transmits the enable signal generated by the encoding-decoding circuit, and the enable signal is transmitted to the signal filtering circuit; A signal filter circuit is used to filter out the noise in the enable signal, and the filtered enable signal is transmitted to the signal conditioning circuit; The signal conditioning circuit is used to modulate the enable signal waveform, and the modulated enable signal is transmitted to the signal holding circuit; The signal holding circuit is used to store the enable signal of each Chiplet, and when the enable signal transitions, the enable signal is transmitted to the corresponding Chiplet. 4. The method according to claim 1, wherein the Chiplet (6) is a functional chip prepared by selecting Si or GaAs or GaN material and utilizing CMOS or BiCMOS or Bipolar process, which is connected with the reconfigurable network topology control The units (1) are connected to form a microsystem. 5. the realization method of the microsystem reconfigurable network topology structure based on Chiplet, is characterized in that, comprises the steps: 1) Prepare tapered TSVs on wafer 1: The through hole is etched on the first layer of silicon wafer by laser drilling technology, and the polymer is filled in the through hole, and then the polymer in the hole is ablated with a laser to form a through hole with an insulating inner wall; A TiN barrier layer is prepared in the through hole by physical vapor deposition (PVD), and a seed layer is prepared on the TiN barrier layer by physical vapor deposition (PVD) process. Through silicon via; 2) thinning the first silicon wafer prepared with the tapered TSV, that is, polishing it by chemical mechanical polishing process CMP, so that both ends of the tapered TSV are bare; 3) The switch matrix and reconfigurable network control unit are successively integrated on the first layer of silicon wafer by CMOS process, and then the rewiring layer is prepared on the first layer of wafer by Damascus process to realize the switch matrix and tapered TSV the electrical interconnection to transmit the enable signal; 4) After the tapered through-silicon vias, the reconfigurable network control unit, the switch matrix, and the rewiring layer are prepared on the first-layer wafer, the first alignment marker is produced; 5) Prepare a chamber on the surface of the second layer wafer by dry etching process to integrate Chiplet; then use SiO ₂ to passivate the bottom of the chamber and make a second alignment mark on the surface of the wafer, using For precise positioning of Chiplet placement; 6) Place the Chiplet in the chamber according to the second alignment marker; 7) Prepare the electrical interconnection structure on the second-layer wafer, that is, first use the Damascus process to prepare the re-wiring layer, and then use the re-wiring layer to lead out the enabling end of the Chiplet to the surface of the second-layer wafer; Preparation of bumps above the redistribution layer to enable electrical interconnection with tapered TSVs and to bond wafers; 8) Fill the chamber with epoxy to fix the Chiplet; 9) The backside of the second-layer wafer is thinned by a back grinding process, and a third alignment marker is made; 10) According to the positions of the first alignment marker and the third alignment marker, the first-layer wafer and the second-layer wafer are bonded at 300°C using a bump bonding process, and a laser cutting process is used. slicing it; 11) Integrate and encapsulate the modules obtained by dicing, and obtain a functionally reconfigurable microsystem based on Chiplet. 6. method according to claim 5 is characterized in that, adopting physical vapor deposition PVD adopted in described step 1), processing condition is as follows: The inert gas used for sputtering is argon, the sputtering target is TiN, the pre-sputtering power is 40-60W, the sputtering power is 20-30W, and the sputtering time is 8-10min. 7. The method according to claim 5, wherein the CMOS process conditions used in the step 3) are: the thickness of the silicon wafer is 0.1mm-1.5mm, the annealing temperature is 1000-1200°C; the Damascus process conditions Yes: the diffusion barrier material is TiN, the metal material is Cu, the inert gas is argon, the circulation time is 100-600s, and the temperature is 20-350℃. 8 . The method according to claim 5 , wherein, in the step 6), the alignment mark adopts a positive marking process, the shape of the marker is a cross, and the side length of the marker is 200-350 μm. 9 . 9. method according to claim 5, is characterized in that, the ball-planting process condition in described step 7) is as follows: The bump material is Cu, the height is 80-100 μm, and the plating rate is 0.2-0.4 μm/min. 10. The method according to claim 5, wherein the laser cutting process conditions in the step 10) are as follows: Laser power 1-1.5KW.

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