CN114859218B - Detection circuit and detection method for lookup table in FPGA chip - Google Patents
Detection circuit and detection method for lookup table in FPGA chip Download PDFInfo
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Abstract
The invention discloses a detection circuit and a detection method of a lookup table in an FPGA chip, wherein the detection circuit comprises a plurality of detection units which are sequentially connected in series, each detection unit comprises 2 (N-1) N-input LUTs, N-1 time sequence detection registers and N-1 fan-out correction registers, N input ends of a first-stage LUT are respectively connected with N data input ports, one time sequence detection register is connected behind each two-stage LUT, a combined logic output end O of the 2 i-1-stage LUT is connected to a first input end of the 2 i-stage LUT, a combined logic output end O of the 2 i-stage LUT is connected to an input end of the i-th time sequence detection register, and an output end of the i-th time sequence detection register is connected to a first input end of the 2i+1-stage LUT; the input end of the first fan-out correction register is connected with the second data input port. The detection circuit provided by the invention corrects the defect that the fan-out of the data input changes along with the number of the LUTs, improves the problem of time sequence asynchronism, and improves the LUT test speed.
Description
Technical Field
The invention belongs to the technical field of chip testing, and particularly relates to a detection circuit and a detection method for a lookup table in an FPGA chip.
Background
The user programmability and low development cost of field programmable gate arrays (Field Programmable Gate Array, FPGAs) make them an important technology for implementing modern circuits and systems. Compared with an application specific integrated circuit (Application Specific Integrated Circuits, ASIC), the characteristics of low development cost, short development period and the like of the FPGA make the FPGA an important core technology for realizing modern digital circuits and systems, and the market share of the FPGA is increasing year by year. The testing work of FPGAs is becoming more and more important, especially for delayed fault detection of FPGAs.
Generally, the testing of FPGAs is classified into middle-test and finished-test, i.e., testing when the flow of FPGA chips ends without dicing and testing after dicing and packaging. And the test models with different pertinence are used for centering test and forming test. For example, detection of a clock network failure, detection of a channel wiring failure, detection of an I/O failure, detection of an LUT failure, and the like. The detection of LUT faults is particularly critical, one reason is that the LUT is a main part of function implementation in the FPGA, and the other reason is that accurate fault detection of part of the LUT is a precondition guarantee of fault-tolerant use of the FPGA. The faults of the LUT in the FPGA are mainly divided into two types of functional faults and delay faults, wherein the functional faults refer to that the LUT cannot complete the configured functions, including the Static Random-Access Memory (SRAM) cannot be configured, open circuit of connection, and the like; the delay fault refers to that the LUT cannot complete the configuration function in time, for example, the input/output delay of the LUT is too long. However, the existing lookup table detection method mainly aims at the test of the functional fault, taking a four-input LUT as an example, namely, inputting 4-bit data (for example, any 4-bit data from 0000 to 1111) and outputting a corresponding lookup table value. In order to check whether the process is abnormal or not, referring to fig. 1, fig. 1 is a schematic diagram of a lookup table detection circuit in an FPGA chip in the prior art, mainly by serially connecting LUTs step by step, the specific test method is as follows: the multi-stage LUTs are sequentially connected in series, wherein the input of the 0 th-stage LUT is connected with the data input of A, B, C, D, and the A, B, C, D inputs 4bit data together; input terminal I of level 1 LUT 0 Connected with the 0 th level of combined logic output O and the 1 st level of input end I 1 、I 2 、I 3 Input data B, C, D are connected respectively; the connection mode of the rest LUT is the same as that of the 1 st stage; and (3) checking whether the output state of the last stage is an expected value or not by changing the data of the ABCD input end, and performing LUT function detection.
However, the above detection method has problems in that: the existing detection method is static test, only comprises a combinational logic circuit, does not test a time sequence related circuit part, and fails to detect the function of the time sequence related circuit; the fan-out of the data input B, C, D in the test circuit can be changed according to the number of LUTs, and the fan-out is too large, so that the time sequence is poor, and the test speed is slow.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a detection circuit and a detection method for a lookup table in an FPGA chip. The technical problems to be solved by the invention are realized by the following technical scheme:
one aspect of the present invention provides a detection circuit for a look-up table in an FPGA chip, comprising a plurality of detection cells serially connected in sequence, each detection cell comprising 2 (N-1) N-input LUTs, N-1 timing detection registers, and N-1 fan-out correction registers, wherein,
the N input ends of the first-stage LUT are respectively connected with N data input ports, each two stages of LUTs are connected with a time sequence detection register, the combination logic output end of the 2i-1 st-stage LUT is connected to the first input end of the 2 i-th-stage LUT, the combination logic output end of the 2 i-th-stage LUT is connected to the input end of the i-th time sequence detection register, the output end of the i-th time sequence detection register is connected with the first input end of the 2i+1-th-stage LUT, wherein i is more than or equal to 2 and less than or equal to N, and N is an integer larger than or equal to 4;
the input end of the first fan-out correction register is connected with the second data input port, and the output end of the first fan-out correction register is respectively connected with the second input end of each LUT in the remaining N-1 stages of LUTs;
the input end of the jth fan-out correction register is connected with the j+1 input end of each LUT in the previous 2j-1 stage LUT, and the output end of the jth fan-out correction register is connected with the j+1 input end of each LUT in the rest stage LUT, wherein j is more than or equal to 2 and less than or equal to N.
In one embodiment of the present invention, each of the N data entry ports is used to enter 1bit of data.
In one embodiment of the present invention, the N-1 timing detection registers and the N-1 fan-out correction registers each include a timing control port for inputting a clock control signal.
In one embodiment of the invention, each detection cell comprises a first level LUT, a second level LUT, a third level LUT, a fourth level LUT, a fifth level LUT, a sixth level LUT, a first timing detection register, a second timing detection register, a third timing detection register, a first fan-out correction register, a second fan-out correction register, and a third fan-out correction register, wherein,
the first-stage LUT, the second-stage LUT, the third-stage LUT, the fourth-stage LUT, the fifth-stage LUT and the sixth-stage LUT are four-input LUTs;
the four input ends of the first-stage LUT are respectively connected with a data input port A, B, C, D, the combined logic output end of the first-stage LUT is connected with the first input end of the second-stage LUT, the combined logic output end of the second-stage LUT is connected with the input end of the first time sequence detection register, the output end of the first time sequence detection register is connected with the first input end of the third-stage LUT, the combined logic output end of the third-stage LUT is connected with the first input end of the fourth-stage LUT, the combined logic output end of the fourth-stage LUT is connected with the input end of the second time sequence detection register, the output end of the second time sequence detection register is connected with the first input end of the fifth-stage LUT, the combined logic output end of the fifth-stage LUT is connected with the input end of the third time sequence detection register, and the output end of the third time sequence detection register is connected with the next detection unit;
the input end of the first fan-out correction register is connected to the data input port B, and the output end of the first fan-out correction register is respectively connected to the second input end of the second-stage LUT, the second input end of the third-stage LUT, the second input end of the fourth-stage LUT, the second input end of the fifth-stage LUT and the second input end of the sixth-stage LUT, and is connected to the input end of the first fan-out correction register of the next detection unit;
the input end of the second fan-out correction register is connected to the data input port C, the third input end of the second-stage LUT and the third input end of the third-stage LUT, and the output end of the second fan-out correction register is connected to the third input end of the fourth-stage LUT, the third input end of the fifth-stage LUT and the third input end of the sixth-stage LUT and connected to the next detection unit;
the input end of the third fan-out correction register is connected to the data input port D, the fourth input end of the second-stage LUT, the fourth input end of the third-stage LUT, the fourth input end of the fourth-stage LUT and the fourth input end of the fifth-stage LUT, and the output end of the third fan-out correction register is connected to the third input end of the sixth-stage LUT and connected to the next detection unit.
In one embodiment of the present invention, a first input terminal of the first stage LUT in the next detection cell is connected to an output terminal of the third timing detection register, a second input terminal of the first stage LUT in the next detection cell is connected to an output terminal of the first fan-out correction register, a third input terminal of the first stage LUT in the next detection cell is connected to an output terminal of the second fan-out correction register, and a fourth input terminal of the first stage LUT in the next detection cell is connected to an output terminal of the third fan-out correction register.
Another aspect of the present invention provides a method for detecting a lookup table in an FPGA chip, including
S1: constructing the detection circuit of any one of the above embodiments to form a first detection circuit;
s2: setting clock control signals in the timing detection register and the fan-out correction register;
s3: obtaining an output signal of the first detection circuit based on the clock control signal and an input signal of a data input port;
s4: judging whether a lookup table in the detection circuit is qualified or not according to the output signal of the first detection circuit.
In one embodiment of the present invention, after the step S3, the method further includes:
exchanging the 2i-1 level LUT with the 2i level LUT to form a second detection circuit, obtaining an output signal of the second detection circuit based on the clock control signal and the input signal of the data input port, and judging whether a lookup table in the second detection circuit is qualified or not according to the output signal of the second detection circuit, wherein i is more than or equal to 2 and less than or equal to N.
In one embodiment of the present invention, the method for detecting a lookup table in the FPGA chip further includes:
and obtaining ideal output results of the first detection circuit and the second detection circuit under the condition that the lookup tables are qualified in advance.
In one embodiment of the present invention, the S3 includes:
1bit of data is respectively input into N input ends of a first stage LUT of a first detection unit in the first detection circuit, rising edge clock control signals are respectively input into the N-1 time sequence detection registers and the N-1 fan-out correction registers, and output signals of the first detection circuit are obtained at the output end of a last detection unit.
In one embodiment of the present invention, the S4 includes:
comparing the output signal of the first detection circuit or the output signal of the second detection circuit with ideal output results respectively, and if the output signals are different, judging that the detection circuits contain LUTs with unqualified functions;
and performing CRC (cyclic redundancy check) on the output signal of the first detection circuit and the output signal of the second detection circuit respectively, and judging that the detection circuit comprises a LUT with delay faults if the CRC value is abnormal.
Compared with the prior art, the invention has the beneficial effects that:
1. the lookup table detection circuit and the detection method can perform functional test on all LUTs in the FPGA, and simultaneously can complete time sequence performance test through the time sequence detection register, so that the test process is more perfect, and the test result is more accurate.
2. The detection circuit provided by the invention corrects the defect that the data input fan-out changes along with the number of the LUTs by adding the fan-out correction register, improves the problem of time sequence dyssynchrony, and improves the LUT test speed.
3. The lookup table detection circuit and the detection method are applicable to LUT test in any logic resource FPGA.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a look-up table detection circuit in an FPGA chip of the prior art;
fig. 2 is a schematic circuit diagram of a detection circuit of a lookup table in an FPGA chip according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a specific connection relationship between a lookup table and a timing detection register according to an embodiment of the present invention;
fig. 4 is a schematic circuit diagram of a detection circuit of a lookup table in another FPGA chip according to an embodiment of the present invention;
fig. 5 is a flowchart of a method for detecting a lookup table in an FPGA chip according to an embodiment of the present invention.
Detailed Description
In order to further explain the technical means and effects adopted by the invention to achieve the preset aim, the following describes in detail a detection circuit and a detection method of a lookup table in an FPGA chip according to the invention with reference to the accompanying drawings and detailed description.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. The technical means and effects adopted by the present invention to achieve the intended purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only, and are not intended to limit the technical scheme of the present invention.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises the element.
Example 1
Referring to fig. 2 and fig. 3, fig. 2 is a schematic circuit diagram of a detection circuit of a lookup table in an FPGA chip according to an embodiment of the present invention, and fig. 3 is a schematic diagram of a specific connection relationship between the lookup table and a timing detection register according to an embodiment of the present invention. The detection circuit comprises a plurality of detection units which are sequentially connected in series, wherein each detection unit comprises two N-input LUTs and a time sequence detection register, N input ends of a first LUT are respectively connected with N data input ports, and each data input port in the N data input ports is used for inputting 1bit of data. The combinational logic output terminal O of the first LUT is connected to the first input terminal of the second LUT, the combinational logic output terminal O of the second LUT is connected to the input terminal of the time sequence detection register, and the output terminal of the time sequence detection register is connected to the combinational logic output terminal O of the first LUT in the next detection unit.
Further, a second input terminal of the second LUT is connected to a second input port B of the N data input ports, a third input terminal of the second LUT is connected to a third input port C of the N data input ports, and so on, and an nth input terminal of the second LUT is connected to an nth input port of the N data input ports. The time sequence detection register comprises time sequence control ports which are respectively used for inputting clock control signals so as to transmit signals registered by the time sequence detection register to the next LUT when the clock control signals are in rising edges.
In this embodiment, the LUTs are four-output LUTs, where four input/output ports of the first four-output LUT are respectively connected to four input ports A, B, C, D.
Specifically, during the actual test, the input data is changed A, B, C, D on the rising edge of each clock control signal, while the sequential logic output, i.e., the output of the timing detection register, is the combined logic value of the four input values of the last LUT. In one-to-one correspondence of clocks to sequential logic values, this means that the crc check value is fixed for each clock cycle. In other words, when a clock is output abnormally, the crc check value generated according to the sequential logic value at the next clock rising edge is abnormal, so as to achieve the purpose of detection.
With the detection circuit with the structure, the dynamic test is realized by inserting a time sequence detection register between LUTs to introduce time sequence control, and then the performance test (the refresh test of LUT values is performed according to a certain clock rate) can be performed. In terms of circuit design, the LUT is connected to the LUT and then connected to the timing detection Register (REG), the result of half of the LUT is output from the combinational logic output terminal O, the result of the other half of the LUT is output from the timing logic output terminal Q of the timing detection register, and the circuits each detect half, that is, the first LUT in each detection cell detects the function of obtaining the combinational logic value, and the second LUT detects the timing control function.
Further, on the basis of the detection circuit, the first LUT and the second LUT in each detection unit are exchanged two by two to obtain a second detection circuit, and in the second detection circuit, the function of the other half LUT for obtaining the combined logic value and the time sequence control function of the other half LUT are detected, so that the simultaneous detection of the logic calculation function and the time sequence function of each LUT in the circuit is realized, and the circuit detection is 100% coverage.
However, as shown in fig. 2, in the testing process of the present detection circuit, the fanout of the data input B, C, D will be changed according to the number of LUTs, and the fanout is too large, which results in poor design timing and slower testing speed, so that a larger error occurs in the timing performance test of the LUTs.
Example two
In view of this, this embodiment proposes another detection circuit for a lookup table in an FPGA chip, where the detection circuit includes a plurality of detection units sequentially connected in series, each detection unit includes 2 (N-1) N-input LUTs, N-1 timing detection registers, and N-1 fan-out correction registers, where N input ends of a first-stage LUT are respectively connected to N data input ports, one timing detection register is connected after each two-stage LUT, a combinational logic output end O of a 2 i-1-stage LUT is connected to a first input end of a 2 i-stage LUT, a combinational logic output end O of a 2 i-stage LUT is connected to an input end of an i-th timing detection register, and an output end of the i-th timing detection register is connected to a first input end of a 2i+1-stage LUT, where 2 is an integer equal to or greater than or equal to 4; the input end of the first fan-out correction register is connected with the second data input port, and the output end of the first fan-out correction register is respectively connected with the second input end of each LUT in the remaining N-1 stages of LUTs; the input end of the jth fan-out correction register is connected with the j+1 input end of each LUT in the previous 2j-1 stage LUT, and the output end of the jth fan-out correction register is connected with the j+1 input end of each LUT in the rest stage LUT, wherein j is more than or equal to 2 and less than or equal to N. Each of the N data entry ports is for inputting 1bit of data.
Further, the N-1 timing detection registers and the N-1 fan-out correction registers each include a timing control port for inputting a clock control signal.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of a detection circuit of a lookup table in an FPGA chip according to another embodiment of the present invention. The detection circuit of the embodiment comprises a plurality of detection units which are sequentially connected in series, wherein each detection unit comprises a first-stage LUT, a second-stage LUT, a third-stage LUT, a fourth-stage LUT, a fifth-stage LUT, a sixth-stage LUT, a first time sequence detection register, a second time sequence detection register, a third time sequence detection register, a first fan-out correction register, a second fan-out correction register and a third fan-out correction register, and the first-stage LUT, the second-stage LUT, the third-stage LUT, the fourth-stage LUT, the fifth-stage LUT and the sixth-stage LUT are four-input LUTs; the four input ends of the first-stage LUT are respectively connected with a data input port A, B, C, D, the combination logic output end O of the first-stage LUT is connected with the first input end of the second-stage LUT, the combination logic output end O of the second-stage LUT is connected with the input end of the first time sequence detection register, the output end of the first time sequence detection register is connected with the first input end of the third-stage LUT, the combination logic output end O of the third-stage LUT is connected with the first input end of the fourth-stage LUT, the combination logic output end O of the fourth-stage LUT is connected with the input end of the second time sequence detection register, the output end of the second time sequence detection register is connected with the first input end of the fifth-stage LUT, the combination logic output end O of the fifth-stage LUT is connected with the first input end of the third time sequence detection register, and the output end of the third time sequence detection register is connected with the next detection unit.
The input end of the first fan-out correction register is connected to the data input port B, and the output end of the first fan-out correction register is respectively connected to the second input end of the second-stage LUT, the second input end of the third-stage LUT, the second input end of the fourth-stage LUT, the second input end of the fifth-stage LUT and the second input end of the sixth-stage LUT, and is connected to the input end of the first fan-out correction register of the next detection unit;
the input end of the second fan-out correction register is connected to the data input port C, the third input end of the second-stage LUT and the third input end of the third-stage LUT, and the output end of the second fan-out correction register is connected to the third input end of the fourth-stage LUT, the third input end of the fifth-stage LUT and the third input end of the sixth-stage LUT and connected to the next detection unit;
the input end of the third fan-out correction register is connected to the data input port D, the fourth input end of the second-stage LUT, the fourth input end of the third-stage LUT, the fourth input end of the fourth-stage LUT and the fourth input end of the fifth-stage LUT, and the output end of the third fan-out correction register is connected to the third input end of the sixth-stage LUT and connected to the next detection unit.
Further, a first input end of the first-stage LUT in the next detection unit is connected to an output end of the third timing detection register, a second input end of the first-stage LUT in the next detection unit is connected to an output end of the first fan-out correction register, a third input end of the first-stage LUT in the next detection unit is connected to an output end of the second fan-out correction register, and a fourth input end of the first-stage LUT in the next detection unit is connected to an output end of the third fan-out correction register.
Similar to the embodiment, in this embodiment, the LUTs are four-output LUTs, where four input/output ports of the first four-output LUT are respectively connected to four input ports A, B, C, D.
Specifically, during the actual test, the input data is changed A, B, C, D on the rising edge of each clock control signal, while the sequential logic output, i.e., the output of the timing detection register, is the combined logic value of the four input values of the last LUT. In the case of a one-to-one correspondence of clock and sequential logic values, this means that the CRC check value is fixed for each clock cycle. In other words, when a clock is output abnormally, the crc check value generated according to the sequential logic value at the next clock rising edge is abnormal, so as to achieve the purpose of detection.
With the detection circuit with the structure, the dynamic test is realized by inserting a time sequence detection register between LUTs to introduce time sequence control, and then the performance test (the refresh test of LUT values is performed according to a certain clock rate) can be performed. In terms of circuit design, the LUT is connected to the LUT and then connected to the timing detection Register (REG), the result of half of the LUT is output from the combinational logic output terminal O, the result of the other half of the LUT is output from the timing logic output terminal Q of the timing detection register, and the circuits each detect half, that is, the first LUT in each detection cell detects the function of obtaining the combinational logic value, and the second LUT detects the timing control function.
On the basis of the detection circuits, the 2i-1 level LUT and the 2i level LUT in each detection unit are exchanged two by two to obtain a second detection circuit, and in the second detection circuit, the function of the other half LUT for obtaining the combined logic value and the time sequence control function of the other half LUT are detected, so that the simultaneous detection of the logic calculation function and the time sequence function of each LUT in the circuit is realized, and the circuit detection is 100% covered.
Furthermore, the detection circuit of the lookup table in the FPGA chip corrects the defect that the data input fan-out changes along with the number of the LUTs by arranging the fan-out correction register, thereby improving the design time sequence problem and improving the LUT test speed.
The lookup table detection circuit of the embodiment can perform functional test on all LUTs in the FPGA, and can complete time sequence performance test through the time sequence detection register, so that the test process is more perfect, and the test result is more accurate.
Example III
On the basis of the second embodiment, the present embodiment provides a method for detecting a lookup table in an FPGA chip, referring to fig. 5, fig. 5 is a flowchart of a method for detecting a lookup table in an FPGA chip, where the method includes:
s1: constructing a detection circuit of a lookup table in the FPGA chip as described in the second embodiment to form a first detection circuit;
s2: setting clock control signals in the timing detection register and the fan-out correction register.
Specifically, taking a four-input LUT as an example, the LUT of the present embodiment is configured as a four-input exclusive-or gate structure, and the initialization data is 16' h6996, which is actually a 16-bit binary code consisting of 0 and 1.
At the first clock rising edge of the clock control signal, a 4-bit (0000-1111) random number is input, the first LUT exclusive-or value is output to the input of the second LUT, and the second LUT outputs the corresponding exclusive-or value to the input end of the first timing detection register REG;
the second clock rising edge refreshes all LUT input end values, and simultaneously refreshes the value of the time sequence detection register REG (the first time sequence detection register REG stores the exclusive OR value of the second LUT of the last clock), and the subsequent LUT states are sequentially rhythmically pushed.
S3: and obtaining an output signal of the detection circuit based on the clock control signal and the input signal of the data input port.
Specifically, the S3 includes:
1bit of data is respectively input into N input ends of a first-stage LUT of a first detection unit, rising edge clock control signals are respectively input into the N-1 time sequence detection registers and the N-1 fan-out correction registers, and output signals of the detection circuit are obtained at the output end of a last detection unit.
Further, after S3, the method further includes:
exchanging the 2i-1 level LUT with the 2i level LUT to form a second detection circuit, obtaining an output signal of the second detection circuit based on the clock control signal and the input signal of the data input port, and judging whether a lookup table in the second detection circuit is qualified or not according to the output signal of the second detection circuit, wherein i is more than or equal to 2 and less than or equal to N.
Further, the method for detecting the lookup table in the FPGA chip further comprises:
and obtaining ideal output results of the first detection circuit and the second detection circuit under the condition that the lookup tables are qualified in advance.
Specifically, before detecting the built detection circuit, we can obtain in advance a theoretical value that should be output when the LUT in the detection circuit is fully qualified each time a signal is output to the detection circuit, and compare the theoretical output result with the actual output result of the detection circuit in the actual test process, so as to determine whether there is an abnormal LUT in the detection circuit.
S4: and judging whether a lookup table in the detection circuit is qualified or not according to the output signal of the detection circuit.
Specifically, comparing the output signal of the first detection circuit or the output signal of the second detection circuit with ideal output results respectively, and if the output signals are different, judging that the detection circuits contain LUTs with unqualified functions; and performing CRC (cyclic redundancy check) on the output signal of the first detection circuit and the output signal of the second detection circuit respectively, and judging that the detection circuit comprises a LUT with delay faults if the CRC value is abnormal.
If the actual output result is different from the theoretical output result in any one of the two detection circuits formed by the LUT sequence exchange, the detection circuit is indicated to contain an unqualified LUT; if a CRC check abnormality occurs in either one of two detection circuits formed by LUT sequence switching, an LUT containing a delay fault in the detection circuit is described. When the detection circuit is detected to have a disqualified function or delay fault, all LUTs in the detection circuit are abandoned.
The detection method of the embodiment can perform functional test on all LUTs in the FPGA, and simultaneously can complete time sequence performance test through the time sequence detection register, so that the test process is more perfect, and the test result is more accurate. By adding the fan-out correction register, the defect that the fan-out of the data input changes along with the number of the LUTs is corrected, the problem of time sequence asynchronism is solved, and the LUT test speed is improved. The LUT test method is applicable to LUT test in any logic resource FPGA.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. A detection circuit of a lookup table in an FPGA chip is characterized by comprising a plurality of detection units which are sequentially connected in series, wherein each detection unit comprises 2 (N-1) N-input LUTs, N-1 time sequence detection registers and N-1 fan-out correction registers,
the N input ends of the first-stage LUT are respectively connected with N data input ports, each two stages of LUTs are connected with a time sequence detection register, the combination logic output end of the 2i-1 st-stage LUT is connected to the first input end of the 2 i-th-stage LUT, the combination logic output end of the 2 i-th-stage LUT is connected to the input end of the i-th time sequence detection register, the output end of the i-th time sequence detection register is connected with the first input end of the 2i+1-th-stage LUT, wherein i is more than or equal to 2 and less than or equal to N, and N is an integer larger than or equal to 4;
the input end of the first fan-out correction register is connected with the second data input port, and the output end of the first fan-out correction register is respectively connected with the second input end of each LUT in the remaining 2N-3 stages of LUTs;
the input end of the jth fan-out correction register is connected with the j+1 input end of each LUT in the previous 2j-1 stage LUT, and the output end of the jth fan-out correction register is connected with the j+1 input end of each LUT in the rest stage LUT, wherein j is more than or equal to 2 and less than or equal to N.
2. The circuitry for detecting a look-up table in an FPGA chip as recited in claim 1, wherein each of said N data input ports is configured to input 1bit of data.
3. The detection circuit of a look-up table in an FPGA chip of claim 1, wherein the N-1 timing detection registers and the N-1 fan-out correction registers each include a timing control port for inputting a clock control signal.
4. The FPGA chip look-up table detection circuit of claim 1, wherein each detection cell comprises a first level LUT, a second level LUT, a third level LUT, a fourth level LUT, a fifth level LUT, a sixth level LUT, a first timing detection register, a second timing detection register, a third timing detection register, a first fan-out correction register, a second fan-out correction register, and a third fan-out correction register, wherein,
the first-stage LUT, the second-stage LUT, the third-stage LUT, the fourth-stage LUT, the fifth-stage LUT and the sixth-stage LUT are four-input LUTs;
the four input ends of the first-stage LUT are respectively connected with a data input port A, B, C, D, the combined logic output end of the first-stage LUT is connected with the first input end of the second-stage LUT, the combined logic output end of the second-stage LUT is connected with the input end of the first time sequence detection register, the output end of the first time sequence detection register is connected with the first input end of the third-stage LUT, the combined logic output end of the third-stage LUT is connected with the first input end of the fourth-stage LUT, the combined logic output end of the fourth-stage LUT is connected with the input end of the second time sequence detection register, the output end of the second time sequence detection register is connected with the first input end of the fifth-stage LUT, the combined logic output end of the fifth-stage LUT is connected with the input end of the third time sequence detection register, and the output end of the third time sequence detection register is connected with the next detection unit;
the input end of the first fan-out correction register is connected to the data input port B, and the output end of the first fan-out correction register is respectively connected to the second input end of the second-stage LUT, the second input end of the third-stage LUT, the second input end of the fourth-stage LUT, the second input end of the fifth-stage LUT and the second input end of the sixth-stage LUT, and is connected to the input end of the first fan-out correction register of the next detection unit;
the input end of the second fan-out correction register is connected to the data input port C, the third input end of the second-stage LUT and the third input end of the third-stage LUT, and the output end of the second fan-out correction register is connected to the third input end of the fourth-stage LUT, the third input end of the fifth-stage LUT and the third input end of the sixth-stage LUT and connected to the next detection unit;
the input end of the third fan-out correction register is connected to the data input port D, the fourth input end of the second-stage LUT, the fourth input end of the third-stage LUT, the fourth input end of the fourth-stage LUT and the fourth input end of the fifth-stage LUT, and the output end of the third fan-out correction register is connected to the third input end of the sixth-stage LUT and connected to the next detection unit.
5. The circuit of claim 4, wherein a first input of a first LUT in a next detection cell is connected to an output of the third timing detection register, a second input of the first LUT in the next detection cell is connected to an output of the first fan-out correction register, a third input of the first LUT in the next detection cell is connected to an output of the second fan-out correction register, and a fourth input of the first LUT in the next detection cell is connected to an output of the third fan-out correction register.
6. The method for detecting the lookup table in the FPGA chip is characterized by comprising the following steps of:
s1: constructing the detection circuit of any one of claims 1 to 5 to form a first detection circuit;
s2: setting clock control signals in the timing detection register and the fan-out correction register;
s3: obtaining an output signal of the first detection circuit based on the clock control signal and an input signal of a data input port;
s4: judging whether a lookup table in the detection circuit is qualified or not according to the output signal of the first detection circuit.
7. The method for detecting a lookup table in an FPGA chip as claimed in claim 6, further comprising, after S3:
exchanging the 2i-1 level LUT with the 2i level LUT to form a second detection circuit, obtaining an output signal of the second detection circuit based on the clock control signal and the input signal of the data input port, and judging whether a lookup table in the second detection circuit is qualified or not according to the output signal of the second detection circuit, wherein i is more than or equal to 2 and less than or equal to N.
8. The method for detecting a look-up table in an FPGA chip as defined in claim 7, further comprising:
and obtaining ideal output results of the first detection circuit and the second detection circuit under the condition that the lookup tables are qualified in advance.
9. The method for detecting a lookup table in an FPGA chip as claimed in claim 8, wherein said S3 includes:
1bit of data is respectively input into N input ends of a first stage LUT of a first detection unit in the first detection circuit, rising edge clock control signals are respectively input into the N-1 time sequence detection registers and the N-1 fan-out correction registers, and output signals of the first detection circuit are obtained at the output end of a last detection unit.
10. The method for detecting a look-up table in an FPGA chip according to claim 8 or 9, wherein S4 comprises:
comparing the output signal of the first detection circuit or the output signal of the second detection circuit with ideal output results respectively, and if the output signals are different, judging that the detection circuits contain LUTs with unqualified functions;
and performing CRC (cyclic redundancy check) on the output signal of the first detection circuit and the output signal of the second detection circuit respectively, and judging that the detection circuit comprises a LUT with delay faults if the CRC value is abnormal.
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