CN102176673A - LUT4 (look up table), logical unit of FPGA (field programmed gate array) and logical block of FPGA - Google Patents

Abstract

The invention discloses a LUT4, an FPGA logic unit and an FPGA logic block. The 4-input look-up table LUT4 includes: two 3-input look-up tables LUT3 and four 2-to-1 multiplexers, the two LUT3s are C-LUT3 and S-LUT3, the four 2-to-1 multiplexers The devices are FMUX, CMUX, SMUX and F4MUX; the outputs of data input ports A0, A1, and A2(0) selected by CMUX respectively enter the three input ports of C-LUT3; data input ports A0, A1(0) and A3 (1) The output selected by SMUX and the output of A2(0) selected by CMUX respectively enter the three input ports of S-LUT3; the output of data input port A3(1) and logic '0' selected by FMUX Enter the control port of F4MUX, the output (0) of S-LUT3 is output from the output port F4 of the LUT4 after being selected by F4MUX; in the FPGA logic unit, Fmux, Smux and Cmux are the control bits of FMUX, SMUX and CMUX respectively. The LUT4, FPGA logic unit and FPGA logic block of the present invention can increase logic density.

Description

4-input look-up tables, FPGA logic cells, and FPGA logic blocks

technical field

The present invention relates to the technical field of semiconductor and microelectronics, in particular to a 4-input look-up table (Look Up Table, referred to as LUT) LUT4, a field programmable gate array (Field Programmed Gate array, referred to as FPGA) logic unit based on the LUT4, and An FPGA logic block based on the FPGA logic unit described above.

Background technique

Compared with Application Specific Integrated Circuits (ASIC for short), FPGA's low R&D cost and short development cycle make it an important core technology for realizing modern digital circuits and systems, and its market share is also increasing year by year. Increase. As the basic unit used for logic implementation in FPGA, the design of logic unit and the logic block formed by it directly affects the speed and area utilization of FPGA to a large extent.

Existing literature proves that: LUT4 can maximize the utilization of FPGA chip area. At present, the most typical FPGA logic unit in academia and industry is composed of a traditional LUT4 and a D-type flip-flop.

Modern commercial FPGAs also include some embedded IP cores for special purposes, such as multiplier blocks and memory blocks. Xilinx's Virtex series and Altera's Cyclone series provide users with a wealth of memory module resources. Nevertheless, for some applications that require a large amount of storage resources, for a certain FPGA chip, the internal memory module resources are limited after all, so these memory modules are still not enough.

In addition, for applications that consume more logic resources and small-capacity storage resources, if a large-capacity memory module is used to implement a small-capacity memory, it will cause waste of the remaining storage resources of the memory module. suitable for such applications.

Because an existing 4-input LUT will not reduce the logic density for any 4-input logic, but for any 3-input or 2-input logic, since the 4-input LUT has only one output, it can only implement a 3-input or 2-input logic. 2-input logic, and LUT4 based on 3-input LUT needs to have 2 outputs, so two 3-input or 2-input logics can be realized, so the existing 4-input LUT logic density is low. In the process of realizing the present invention, the inventor realized that the prior art has the following defects: the existing LUT4 has low logic density.

Contents of the invention

(1) Technical problems to be solved

In view of the above problems, the present invention proposes a LUT4 based on two LUT3s, an FPGA logic unit based on the LUT4 and an FPGA logic block based on the FPGA logic unit. Compared with the conventional LUT4, this LUT4 has improved logic density.

(2) Technical solution

According to one aspect of the present invention, a 4-input look-up table LUT4 is provided. The LUT4 includes: two 3-input look-up tables LUT3 and four 2-to-1 multiplexers, the two LUT3s are C-LUT3 and S-LUT3, and the four 2-to-1 multiplexers are FMUX, CMUX, SMUX and F4MUX. Outputs of the data input ports A0, A1, and A2(0) selected by the CMUX respectively enter the three input ports of the C-LUT3. The outputs of data input ports A0, A1(0) and A3(1) selected by SMUX, and the output of A2(0) selected by CMUX respectively enter the three input ports of S-LUT3. The output of the data input port A3 (1) and logic '0' selected by FMUX enters the control port of F4MUX, and the output (0) of S-LUT3 is output from the output port F4 of the LUT4 after being selected by F4MUX. In the FPGA logic unit, Fmux, Smux, and Cmux are the control bits of FMUX, SMUX, and CMUX, respectively.

Preferably, in this technical solution LUT4, the output of A2(0) after CMUX selection enters one of the three input ports of C-LUT3 respectively: the outputs of A2(0) and CI(1) after CMUX selection respectively enter One of the three input ports of C-LUT3. The output of A2(0) after CMUX selection enters one of the three input ports of S-LUT3: the output of A2(0) and CI(1) after CMUX selection enters one of the three input ports of S-LUT3 respectively one. The output (0) of S-LUT3 is output from the output port F4 of the LUT4 after being selected by F4MUX: the output CO (1) of C-LUT3 and the output (0) of S-LUT3 are selected from the output port of LUT4 after being selected by F4MUX F4 output.

Preferably, in this technical solution LUT4, according to the different combinations of control bits Fmux, Smux and Cmux, configure the working mode of LUT4: when Smux=0, Cmux=0, when Fmux=1, its working mode is LUT4; or when Smux =0, Cmux=1, when Fmux=0, its operating mode is carry chain; Or when Smux=0, Cmux=0, when Fmux=0, its operating mode is carry chain head; Or when Smux=1, Cmux= 0, when Fmux=0, its working mode is a multiplier.

According to another aspect of the present invention, a field programmable gate array FPGA logic unit is provided. The FPGA logic unit includes the above LUT4, D-type flip-flop and four 2-to-1 multiplexers BMUX, F5MUX, DMUX0 and DMUX1. The D-type flip-flop includes: a data input port D, a data output port XQ, control input ports CE and SR, a clock input port CK, and a global set reset port GSR. The input ports of the FPGA logic unit include: data input ports A0, A1, A2, A3 and data input ports B, F5I of the 4-input LUT; the output ports of the FPGA logic unit include: the data output port F4 and the data output port of the 4-input LUT XB, XF, XQ. Data input port B(1) and output port CO(0) of C-LUT3 output XB after passing through BMUX; output of data input port F5I(1) and output port F4(0) of LUT4 after passing through F5MUX enters 1 input of DMUX1 Port, F4 enters the 0 input port of DMUX1, and the output of DMUX1 is XF; XF (1) and B (0) are output into the data input port D of the D-type flip-flop after being selected by DMUX0, and the output port of the D-type flip-flop is used as the FPGA The data output port XQ of the logic unit. Bmux, Dmux1 and Dmux0 are the control bits of B5MUX, DMUX1 and DMUX0 respectively.

Preferably, in the FPGA logic unit of the technical solution, CI is used as a dedicated carry chain input port of the FPGA logic unit; CO is used as a dedicated carry chain output port of the FPGA logic unit.

Preferably, in the FPGA logic unit of the technical solution, Fmux, Smux, Cmux, Bmux, Dmux1 and Dmux0 are all 5-pipe storage units.

Preferably, in the FPGA logic unit of this technical solution, in the FPGA logic unit, according to the different combination of control bit Bmux, Dmux1 and Dmux0, configure the signal flow direction of the FPGA logic unit: when Bmux=0, F5mux=0, Dmux0=0, Dmux1 =0/1, the signal flow direction is CO drives XB, B drives D; or when Bmux=0, F5mux=0, Dmux0=1, Dmux1=0/1, the signal flow direction is CO drives XB, LUT4 drives D; or When Bmux=0, F5mux=1, Dmux0=0, Dmux1=0/1, the signal flow is CO drives XB, B drives D; or when Bmux=0, F5mux=1, Dmux0=1, Dmux1=0/1 , the signal flow direction is CO drives XB, LUT4 drives D; or when Bmux=1, F5mux=0, Dmux0=0, Dmux1=0/1, the signal flow direction is B drives XB, B drives D; or when Bmux=1 , F5mux=0, Dmux0=1, Dmux1=0/1, the signal flow direction is B drives XB, LUT drives D; or when Bmux=1, F5mux=1, Dmux0=0, Dmux1=0/1, the signal flow direction B drives XB, B drives D; or when Bmux=1, F5mux=1, Dmux0=1, Dmux1=0/1, the signal flow direction is B drives XB, and LUT4 drives D.

Preferably, in the FPGA logic unit of the present technical solution, the D flip-flop includes: a core register and 4 2-to-1 multiplexers CKPOLMUX, SRSYNCMUX, SRSELMUX, QTYPEMUX; the D flip-flop input includes a data input D, a clock CK, Clock enable CE, set/reset SR and global set/reset GSR, the output is data output Q; SR(0) and logic '0'(1) are output after SRSYNCMUX selection, and the output is OR logic with GSR, The output of the OR logic is output through SRSELMUX to generate S(0) and R(1), which are the set/reset terminals of the core register respectively; CK(1) and ~CK(0) are selected by CKPOLMUX to enter the CK terminal of the core register, and the core The input QL (0) and QF (1) of the register are selected to input Q through QTYPEMUX; the control bits of the 2-to-1 multiplexer CKPOLMUX, SRSYNCMUX, SRSELMUX, and QTYPEMUX are ckpol, srsync, srsel, and qtype, respectively, according to the control bit ckpol , srsync, srsel, different combinations of qtype, D flip-flops are configured as different types of registers or latches.

Preferably, in the FPGA logic unit of this technical solution, in the D flip-flop, according to the control bit ckpol, the D flip-flop is configured as positive edge trigger or negative edge trigger; and/or according to the control bit srsync, the D flip-flop is configured as synchronous or asynchronous; and/or according to the control bit srsel, the D flip-flop is configured as set or reset; and/or according to the control bit qtype, the D flip-flop is configured as a register or a latch.

According to another aspect of the present invention, an FPGA logic block is provided. The logic block includes: a first FPGA logic unit, a second FPGA logic unit, local interconnection, and distributed RAM logic, wherein the first FPGA logic unit and the second FPGA logic unit are the FPGA logic unit above; the FPGA logic The ports of the block include 2 global input ports-G<1:0>, 12 input ports-I<11:0>, 8 output ports-O<7:0>, dedicated carry chain input ports-CI, dedicated Carry chain output port-CO and 1 global set reset port-SR and 1 global write enable port-GWE; local interconnection includes: connections between the global input port of the logic block and the clock port and control input port of the logic unit ; the connection between the logic block input port and the logic cell input port; the feedback connection between the logic cell output port and the logic cell data input port; the connection between logic '0' and logic '1' and logic cell input port; A connection between a logic block output port and a logic cell output port.

Preferably, in the technical solution FPGA logic block, distributed RAM logic comprises: synchronous register, write control module, write multiplexer, read multiplexer, two logics of this distributed RAM and FPGA logic block The unit shares data inputs A0[3:0], A1[3:0], B0, B1, SR, CK, and shares data outputs XF0 and XF1. The synchronization register is used to synchronize the written data, address and write control signal; the write control module is used to control the direction of the written data; the write multiplexer is used to write new data to the location of the storage unit specified by the address; the read The multiplexer is a 4-input LUT for logic cells in FPGA logic blocks. According to the different polarities of controlling ramckpol, the distributed RAM can be configured to write data on the positive or negative edge of the clock. The control bit S1 and the write enable signal WE (the output of the SR after registering) respectively perform AND logic through the AND gates WENAND0 and WENAND1 in the write control module, and the output of the AND logic enters the write multiplexer to control the writing of data ; Control bit S2 controls the writing of data by controlling the transmission gate S2PASS in the write control module; Control bit S3 controls S3MUX0 and S3MUX1 in the synchronous register to control the selection of the write address, and in the write control module and Din1orA4 (B1 through Registered output) through AND gate A4NAND performs AND logic to control B1 as data input or the fifth address; control bit D controls DMUX in the synchronization register to control the selection of the write address, and controls the transmission gate in the write control module DPASS is used to control the writing of data; the control bit ramckpol controls RAMCKPOLMUX; the FPGA logic block has different working modes according to the polarity of the control bits (S1, S2, S3, D).

Preferably, in the FPGA logic block of the technical solution, the connection between the global input port of the logic block and the clock port of the logic unit and the control input port includes: the global input port G<1> is directly connected to the CKs of the two logic units, and the global input port Port G<0> can be connected to SR or CE controlled by control bits. The connection between the logic block input port and the logic unit input port comprises: data input port I<6>, I<0>, I<9>, I<3> and the data input port A0 of the first FPGA logic unit respectively, A1, A2, A3 are directly connected, I<8>, I<2>, I<11>, I<5> are directly connected to A0, A1, A2, A3 of the second FPGA logic unit, and I<7> is directly connected to B0 of the first FPGA logic unit is directly connected, I<1> is directly connected to B1 of the second FPGA logic unit, I<10> is directly connected to CE, and I<4> is directly connected to SR. The feedback connection between the logic unit output port and the logic unit data input port includes: the first FPGA logic unit output F4 is directly connected with the second FPGA logic unit input F5i, the second FPGA logic unit output F4 is connected with the first FPGA logic unit input F5i direct connection. Connections between logic '0' and logic '1' and logic cell input ports include: logic '0' and logic '1' can be connected to the first FPGA logic cell input B0, logic '0' and logic '1' can Connected to the second FPGA logic unit input B1, logic '0' and logic '1' can be connected to the common inputs CE, SR, CE of the two logic units in the FPGA logic block. The connection between the logic block output port and the logic unit output port includes: the output port O(0) is output by the output ports XQ0 and XB0 of the first logic unit, the output port XF1 of the second logic unit is output, and the output port O(1) is output by The output port XF0 of the first logic unit, the output ports XQ1 and XB1 of the second logic unit output, the output port O (2) is output by the output port XQ0 of the first logic unit, the output port XF1 of the second logic unit, and the output port O (3) output by the output port XF0 and XB0 of the first logic unit, the output port XQ1 of the second logic unit, output port O (4) by the output port XQ0 of the first logic unit, the output port XF1 and the second logic unit XB1 output, output port O(5) is output by output port XF0 of the first logic unit, output port XQ1 of the second logic unit, output port O(6) is output by output port XQ0 of the first logic unit, output port XQ0 of the second logic unit The output port XF1 is output, and the output port O(7) is output by the output port XF0 of the first logic unit and the output port XQ1 of the second logic unit.

Preferably, in the FPGA logic block of the technical solution, S1=0; S2=0; S3=0; when D=0, the working mode of the logic block is LUT; or S1=1; S2=0; S3=0; D When =0, the operating mode of the logic block is single-port 16*1RAM; or S1=1; S2=1; S3=0; when D=0, the operating mode of the logic block is single-port (16*1)*2RAM; Or S1=1; S2=0; S3=1; D=0, the working mode of the logic block is single-port 32×1RAM; or S1=1; S2=0; S3=0; D=1, the logic block The working mode is dual-port 16×1RAM.

Preferably, in the FPGA logic block of the technical solution, when the FPGA logic block realizes fast carry chain logic: the carry input port CI of the FPGA logic block is directly connected with the carry input port CI of the first FPGA logic unit, and the carry input port CI of the first FPGA logic unit The carry output port CO is directly connected to the carry input port CI of the second FPGA logic unit, and the carry output port CO of the second FPGA logic unit is output through the carry output port CO of the logic block.

Preferably, in the FPGA logic block of the technical solution, the CO port of the FPGA logic block is connected to the CI port of an adjacent FPGA logic block; and/or the CI port of the FPGA logic block is connected to the CO port of another adjacent FPGA logic block.

Preferably, in the FPGA logic block of the technical solution, when the FPGA logic block implements the shift register chain logic, the input port B of the logic unit passes through the logic block directly or after being registered.

(3) Beneficial effects

1. The LUT4 of the present invention can realize not only one 4-input arbitrary Boolean logic, but also two 3-input Boolean logics. Compared with the conventional LUT4, this LUT4 has improved logic density.

2, in the FPGA logic unit of the present invention, according to the difference of control bit, this FPGA logic unit can be configured as 8 kinds of operating modes, wherein the most commonly used has 4 kinds: LUT4, carry chain, carry chain head and multiplier. The biggest advantage of the FPGA logic unit is that it can increase the logic density.

3. The LUT is used as a distributed RAM in the FPGA logic block of the present invention, which can make up for the shortage of memory module resources for the application of concentrated storage resources, and can improve the utilization rate of resources for the concentrated application of small-capacity storage.

Description of drawings

FIG. 1 is a schematic diagram of a logical structure of an LUT4 according to an embodiment of the present invention;

Fig. 2 is the logic structure schematic diagram of the FPGA logic unit of the embodiment of the present invention;

Fig. 3 is the structural representation of the 5-pipe storage unit that is used to store control bit information in the FPGA logic unit of the embodiment of the present invention;

Fig. 4 is the logic structure schematic diagram of D flip-flop in the FPGA logic unit of the embodiment of the present invention;

Fig. 5 is a schematic diagram of port distribution and layout of the FPGA logic block in an embodiment of the present invention;

Fig. 6 is the schematic diagram of the partial interconnection of FPGA logic block according to the embodiment of the present invention;

Fig. 7 is the logical structural diagram of distributed RAM in the FPGA logic block of the embodiment of the present invention;

Fig. 8 is the connection schematic diagram that FPGA logic block realizes fast carry chain logic of the embodiment of the present invention;

Fig. 9 is the connection schematic diagram that FPGA logic block realizes register chain logic of the embodiment of the present invention;

Fig. 10 is a schematic diagram of the logical structure of the FPGA logic block in the embodiment of the present invention as a single-port 32×1 RAM;

FIG. 11 is a schematic diagram of a logic structure of an FPGA logic block as a dual-port RAM according to an embodiment of the present invention.

Table 1 is four commonly used operating modes of the FPGA logic unit in the embodiment of the present invention;

Table 2 is the signal flow direction of the FPGA logic unit of the embodiment of the present invention;

Table 3 is the working mode of the D flip-flop in the FPGA logic unit of the embodiment of the present invention;

Table 4 is the operating mode realized by the FPGA logic block according to the setting of the control bit in the embodiment of the present invention;

Table 5 shows the signal sources when the FPGA logic block works in LUT mode and single-port RAM mode;

Table 6 shows the signal sources when the FPGA logic block works in LUT mode and dual-port RAM mode.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

1. 4-input LUT (LUT4)

This embodiment first discloses a LUT4, and FIG. 1 is a schematic diagram of a logic structure of the LUT4 according to an embodiment of the present invention. As shown in FIG. 1 , the LUT4 includes: two 3-input look-up tables LUT3 and four 2-to-1 multiplexers. The two LUT3s are C-LUT3 and S-LUT3, and the four 2-to-1 multiplexers are FMUX, CMUX, SMUX and F4MUX. The outputs of the data input ports A0, A1, and A2(0) selected by the CMUX respectively enter the three input ports A, B, and C of the C-LUT3. The outputs of data input ports A0, A1(0) and A3(1) selected by SMUX, and the output of A2(0) selected by CMUX respectively enter the three input ports A, B and C of S-LUT3. The output of the data input port A3 (1) and logic '0' (0) selected by FMUX enters the control port of F4MUX. The output CO(1) of C-LUT3 and the output (0) of S-LUT3 are output from the output port F4 of the LUT4 after being selected by F4MUX. In the LUT4, Fmux, Smux and Cmux are control bits of the FMUX, SMUX and CMUX respectively. For the convenience of description, the abbreviation of the connection with the 0 port of the two-choice multiplexer MUX is 0, and the abbreviation of the connection with the 1 port is 1. For the LUT4 of this embodiment, 4-input logic and 3-input logic can be implemented according to user needs, specifically:

1) When the Smux=0, Cmux=0, and Fmux=0, its working mode is to realize two 3-input logics, and the inputs of the two 3-input logics are A0, A1, A2; or when the Smux =0, Cmux=0, Fmux=1, its working mode is to realize a 4-input logic, the input is A0, A1, A2, A3;

2) When the Smux=0, Cmux=1, and Fmux=0, its working mode is to realize two 3-input logics, and the inputs of the two 3-input logics are A0, A1, CI;

3) When the Smux=0, Cmux=1, and Fmux=1, its working mode is to realize a 4-input logic, and the input is A0, A1, A2, A3;

4) When the Smux=1, Cmux=0, and Fmux=0, its working mode is to implement two 3-input logics, the first 3-input logic input is A0, A1, A2; the second one 3-input logic input is A0, A3, A2;

5) When the Smux=1, Cmux=0, and Fmux=1, its working mode is to realize a 4-input logic, and the input is A0, A1, CI, A3;

6) When the Smux=1, Cmux=1, and Fmux=0, its working mode is to realize two 3-input logics, the first 3-input logic input is A0, A1, CI; the second 3-input logic input The input is A0, A3, CI;

7) When the Smux=1, Cmux=1, and Fmux=1, its working mode is to implement a 4-input logic, and the input is A0, A1, CI, A3.

Further, in the above embodiment, the output of A2(0) selected by CMUX respectively enters one of the three input ports of C-LUT3: the outputs of A2(0) and CI(1) selected by CMUX respectively Enter one of the three input ports of the C-LUT3; the output of the A2(0) selected by the CMUX enters one of the three input ports of the S-LUT3 respectively: A2(0) and CI(1) through The output after CMUX selection enters one of the three input ports of the S-LUT3 respectively; the output (0) of the S-LUT3 is output from the output port F4 of the LUT4 after being selected by the F4MUX: the output CO of the C-LUT3 (1) and the output (0) of S-LUT3 are output from the output port F4 of the LUT4 after being selected by F4MUX.

Table 1 Four commonly used working modes of LUT4 in the embodiment of the present invention

Based on different combinations of control bits of SMUX, CMUX and FMUX, this LUT4 can be configured into 8 modes. Table 1 shows the four most commonly used modes of LUT4 in this embodiment.

Mode 1: Used as an ordinary LUT4, it can implement any four-input Boolean logic. For example, we want to implement a 4-input AND logic y=a·b·c·d, the SRAM storage unit of the LUT4 configuration layer is configured as 80 (hexadecimal), and then the corresponding AND result can be obtained according to the input.

和逻辑单元配置层的SRAM存储单元被配置为96E8(16进制)，CI端口由其他逻辑单元的CO端口驱动，取代I2进入两个LUT3，求和逻辑和进位逻辑分别由S-LUT3和C-LUT3来完成，输入I3不进入LUT3而是去控制F4MUX使SUM输出，CO端口输出给其他逻辑单元的CI端口。比用传统LUT4实现一位全加器节省了一半面积。Mode 2: As a fast carry chain. LUT4 is configured as a one-bit full adder,

and The SRAM storage unit of the logic unit configuration layer is configured as 96E8 (hexadecimal), the CI port is driven by the CO port of other logic units, and replaces I2 into two LUT3s, and the summation logic and carry logic are controlled by S-LUT3 and C-LUT3 respectively. LUT3 to complete, the input I3 does not enter the LUT3 but to control the F4MUX to make the SUM output, and the CO port outputs to the CI port of other logic units. Compared with the traditional LUT4 to realize a full adder, it saves half the area.

Mode 3: It is used in the full-add logic. When the lowest bits of the two addends are added, there is no CI port input at this time, so the CI port is not connected to LUT3.

Mode 4: Used to implement multiplication logic. In this mode, two LUT3s can output the results of I0&I1, I2&I3 through XB and XF at the same time, and one LUT4 can get two partial products at the same time, and then combine with a LUT4 working in mode 2 to accumulate the partial products , to get the final multiplication result. FIG. 3 is a schematic structural diagram of a five-pipe storage unit for storing control bit information in an FPGA logic unit according to an embodiment of the present invention.

To sum up, the LUT4 of this embodiment can flexibly realize the functions of various modes in combination with various subsequent settings, and greatly improve the logic density. However, the LUT4 in this embodiment can only implement combinational logic, but not sequential logic. In order to realize sequential logic, flip-flop devices need to be introduced, which will be a problem to be solved in the FPGA logic unit.

Two, FPGA logic unit

The logic unit is the smallest unit used for logic implementation in FPGA. This embodiment discloses an FPGA logic unit. FIG. 2 is a schematic diagram of a logic structure of an FPGA logic unit according to an embodiment of the present invention. As shown in Figure 2, the FPGA logic unit is composed of a LUT4 in the above embodiment, a D-type flip-flop and four 2-to-1 multiplexers (BMUX, F5MUX, DMUX0 and DMUX1) responsible for data flow direction selection . The ports of the logic unit include data input ports (A0, A1, A2, A3, B, F5I), control input ports (CE, SR), clock input ports (CK), global set reset ports (GSR), and dedicated carry chains Input ports (CI), dedicated carry chain output ports (CO), and data output ports (F4, XB, XF, XQ).

Among them, the LUT4 is composed of four 2-to-1 multiplexers (FMUX, CMUX, SMUX and F4MUX) and two 3-input LUTs (C-LUT3 and S-LUT3). The outputs of the data input ports A0, A1, A2(0) and CI(1) selected by the CMUX respectively enter the three input ports A, B, and C of the C-LUT3. The output of data input port A0, A1(0) and A3(1) after SMUX selection and the output of A2(0) and CI(1) after CMUX selection enter the three input ports A and B of S-LUT3 respectively , C. The output of data input A3 and logic '0' after FMUX selection enters the control port of F4MUX. After the output CO(1) of C-LUT3 and the output (0) of S-LUT3 are selected by F4MUX, the output port of LUT4 is F4. Fmux, Smux and Cmux are the control ports of FMUX, SMUX and CMUX respectively, all of which are 5-tube storage units.

Wherein, the data input port B(1) and the output port CO(0) of the C-LUT3 output XB after passing through the BMUX. The output of the data input port F5I(1) and the output port F4(0) of the 4-LUT after passing through F5MUX enters the 1 input port of DMUX1, F4 enters the 0 input port of DMUX1, and the output of DMUX1 is XF. After XF(1) and B(0) are selected by DMUX0, the output enters DFF data input port D. Bmux, Dmux1 and Dmux0 are the control ports of B5MUX, DMUX1 and DMUX0 respectively, all of which are 5-tube storage units. Data input port B is the control port of F5MUX.

Further, in the above embodiment, the CI is used as a dedicated carry chain input port of the FPGA logic unit; the CO is used as a dedicated carry chain output port of the FPGA logic unit. There are a lot of addition logic in many logic applications, such a logic unit can not only realize the basic sum logic, but also provide carry for high-order addition, so the fast carry chain is very large in practical applications.

Table 2 The signal flow direction of the FPGA logic unit of the embodiment of the present invention

Wherein, the D flip-flop can be configured as different types of registers or latches. The DFF ports include a data input port D, a control input port (CE, SR), a clock input port (CK), a global set reset port (GSR), and a data output port (XQ).

Table 2 lists the different signal flow directions of bypass input B and LUT output according to different combinations of control bits Bmux, F5mux, Dmux0 and Dmux1 polarity. For example when Bmux='1' and Dmux0='1', XB is driven by B and register input D is driven by LUT output. The signal flow will be related to the implementation of subsequent FPGA logic blocks, which will be described in detail in subsequent embodiments.

Table 3 The working mode of the D flip-flop in the FPGA logic unit of the embodiment of the present invention

Note: Register element symbols (beginning with F) without _1 are positive edge triggers, those with _1 are negative edge triggers, and latch element symbols (beginning with L) without _1 are high level triggers , with _1 is a low-level trigger.

FIG. 4 is a schematic diagram of a logic structure of a D flip-flop in an FPGA logic unit according to an embodiment of the present invention. Referring to Figure 4, the D flip-flop includes a core register and four 2-to-1 multiplexers CKPOLMUX, SRSYNCMUX, SRSELMUX, and QTYPEMUX. According to different combinations of their control bits ckpol, srsync, srsel, and qtype, the D flip-flop can are configured as different types of registers or latches. The D flip-flop inputs include D (data input), CK (clock), CE (clock enable), SR (set/reset) and GSR (global set/reset), and the output is Q (data output). SR(0) and logic '0'(1) are output after being selected by SRSYNCMUX. This output is ORed with GSR, and the output of OR logic is output by SRSELMUX to generate S(0) and R(1), which are the core register settings respectively. bit/reset terminal. CK(1) and ~CK(0) are selected to enter the CK end of the core register through CKPOLMUX. The input QL(0) and QF(1) of the core register select the input Q through QTYPEMUX.

Table 3 is a table of working modes of the D flip-flop in the FPGA logic unit of the embodiment of the present invention. As shown in Table 3, according to different combinations of control bits ckpol, srsync, srsel, and qtype, D flip-flops can be configured as different types of registers or latches. This provides great flexibility for the user. The user can choose the type of register according to his own application, such as a register with asynchronous setting or a register with synchronous setting.

Control bit ckpol: According to the polarity of the control bit ckpol, the D flip-flop can be configured as a positive edge trigger or a negative edge trigger. Negative edge trigger. The two D flip-flops in the logic block share a clock input, and its polarity can be configured separately. The CE signal is active high, and the two D contacts in the logic block share a clock enable. If the configured D flip-flop does not use CE, its default state is valid, for example, the CE of FDC is high by default.

Control bit srsync: The SR signal is active high, and can be configured as synchronous or asynchronous according to the polarity of the control bit srsync.

Control bit srsel: It can be configured as set or reset according to the control bit srsel, such as srsync='0' and srsel='0' of FDCE, which is a register with asynchronous reset and clock enable. The two D flip-flops in the logic block share the SR signal. If the configured D flip-flop does not use the SR signal, its default state is invalid, for example, the SR of FDE is low by default.

Control bit qtype: According to the polarity of the control bit qtype, the D flip-flop can be configured as a register or a latch, such as LD's qtpye='0', which is a latch.

The biggest advantage of the FPGA logic unit in this embodiment is that the logic density can be increased. Moreover, by adding D flip-flops and four other multiplexers, the timing logic of the FPGA logic unit is realized, which can be applied in the logic block.

3. FPGA Logic Block

This embodiment discloses an FPGA logic block. The logic block includes: two FPGA logic units as described in the above embodiments—the first FPGA logic unit and the second FPGA logic unit, local interconnection and distributed RAM logic.

FIG. 5 is a schematic diagram of port distribution and layout of an FPGA logic block according to an embodiment of the present invention. As shown in Figure 5, the ports of the FPGA logic block include 2 global input ports-G<1:0>, 12 input ports-I<11:0>, 8 output ports-O<7:0>, Dedicated carry chain input port-CI, dedicated carry chain output port-CO, 1 global set reset port-SR and 1 global write enable port-GWE. The input and output ports of the logic block are evenly distributed around the rectangular logic block, and the input and output ports of the logic unit are evenly connected to the same type of input and output ports around the logic block, which is conducive to improving the routing rate.

In the FPGA logic block of this embodiment, the local interconnection includes: the connection between the global input port of the logic block and the clock port of the logic unit and the control input port; the connection between the input port of the logic block and the input port of the logic unit; the output port of the logic unit Feedback connection to logic cell data input port; connection between logic '0' and logic '1' and logic cell input port; connection between logic block output port and logic cell output port.

FIG. 6 is a schematic diagram of local interconnection of FPGA logic blocks according to an embodiment of the present invention.

As shown in Figure 6, the connection between the global input port of the logic block and the clock port and control input port of the logic unit includes: the global input port G<1> is directly connected to the CK of the two logic units, and the global input port G<0> It can be connected to SR or CE controlled by the control bit.

As shown in Figure 6, the connection between the logic block input port and the logic unit input port includes: data input port I<6>, I<0>, I<9>, I<3> are respectively connected with the first FPGA logic unit The data input ports A0, A1, A2, A3 are directly connected, and I<8>, I<2>, I<11>, I<5> are directly connected to A0, A1, A2, A3 of the second FPGA logic unit respectively , I<7> is directly connected to B0 of the first FPGA logic unit, I<1> is directly connected to B1 of the second FPGA logic unit, I<10> is directly connected to CE, and I<4> is directly connected to SR.

As shown in Figure 6, the feedback connection between the logic unit output port and the logic unit data input port includes: the first FPGA logic unit output F4 is directly connected with the second FPGA logic unit input F5i, and the second FPGA logic unit output F4 is connected with the second FPGA logic unit output F4 An FPGA logic unit input is directly connected to the F5i.

As shown in Figure 6, the connections between logic '0' and logic '1' and logic cell input ports include: logic '0' and logic '1' can be connected to the first FPGA logic cell input B0, logic '0' The sum logic '1' can be connected to the second FPGA logic unit input B1, and the logic '0' and logic '1' can be connected to the common inputs CE, SR, CE of the two logic units in the FPGA logic block.

As shown in Figure 6, the connection between the logic block output port and the logic unit output port includes: the output port O (0) is output by the output ports XQ0 and XB0 of the first logic unit, the output port XF1 of the second logic unit, and the output Port O(1) is output by the output port XF0 of the first logic unit, the output ports XQ1 and XB1 of the second logic unit, and the output port O(2) is output by the output port XQ0 of the first logic unit, the output port of the second logic unit XF1 output, the output port O(3) is output by the output port XF0 and XB0 of the first logic unit, the output port XQ1 of the second logic unit is output, the output port O(4) is output by the output port XQ0 of the first logic unit, the second logic unit The output ports XF1 and XB1 of the unit are output, the output port O(5) is output by the output port XF0 of the first logic unit, the output port XQ1 of the second logic unit is output, and the output port O(6) is output by the output port XQ0 of the first logic unit , the output port XF1 of the second logic unit is output, and the output port O(7) is output by the output port XF0 of the first logic unit and the output port XQ1 of the second logic unit.

FIG. 7 is a logical structure diagram of a distributed RAM in an FPGA logic block according to an embodiment of the present invention. The two logic units of the distributed RAM and the FPGA logic block share data inputs A0[3:0], A1[3:0], B0, B1, SR, CK, and share data outputs XF0 and XF1. The faceted RAM mainly includes a synchronous register, a write control module, a write multiplexer, and a read multiplexer. The synchronization register is used to synchronize the written data B0 and B1, addresses A0[3:0] and A1[3:0] and the write control signal WE. The write control module is used to control the direction of written data. The write multiplexer is used to write new data to the memory location specified by the address. The read multiplexer is the 4-input LUT of the logic cell in the FPGA logic block, so the read time is consistent with the propagation delay of the LUT. The logic block has different working modes according to the polarity of the control bits (S1, S2, S3, D), as shown in Table 4. For example, when S1='0', the logic block is used as a LUT; when S1='1 'When logic blocks are used as distributed RAM. When the control bit ramckpol=‘0’, the RAM writes new data at the positive edge of the clock, and when ramckpol=‘1’, the RAM writes new data at the negative edge of the clock.

FIG. 8 is a schematic diagram of the connection of FPGA logic blocks implementing fast carry chain logic according to an embodiment of the present invention. As shown in Figure 8, the CO port of each logic unit is directly connected to the CI port of the logic unit on the adjacent upper side, and the CO port of the second logic unit in the top logic block of the FPGA chip is connected to the CI port of the adjacent right bottom logic unit. The CI port is directly connected to form a fast carry chain logic.

FIG. 9 is a schematic diagram of the connection of FPGA logic blocks implementing register chain logic according to an embodiment of the present invention. When Bmux='1', the bypass signal B directly passes through the logic block from XB. When Dmux0='0', the bypass signal B enters the register and outputs through XQ. If XQ enters the adjacent logic block with the same configuration from B, a register chain is formed. Its uses are quite extensive. Table 4 The working modes realized by the FPGA logic block in this embodiment according to the setting of the control bits

Table 4 shows the working modes realized by the FPGA logic block according to the settings of the control bits in the embodiment of the present invention. It can be configured as single-port RAM and dual-port RAM. A logic block can be configured as a 16×1, (16×1)×2, 32×1 single-port RAM or a 16×1 dual-port RAM. Single-port RAM has a synchronous write port and an asynchronous read port. Dual-port RAM has a synchronous write port and two asynchronous read ports, and any read and write operations can be performed simultaneously or independently. Synchronous reads of distributed RAMs using registers of other logic blocks are also possible.

Controlled by the global write enable signal (GWE) and the local write enable signal (WE), the write operation of the distributed RAM is triggered by the clock edge, which can be configured as a positive edge trigger or a negative edge trigger. In order to ensure that the RAM content is not damaged after initialization, GWE is invalid during the configuration process of the FPGA chip. The GWE is released after configuration. When GWE and WE are valid at the same time, new content is written into the storage unit selected by the address along the clock edge. The read time of the distributed RAM is equal to the logical transfer delay of the LUT. The distributed RAM content is initialized during FPGA configuration. Once the FPGA chip is powered on, all distributed RAM storage units are cleared, and then written to user-defined initial values. If not defined by the user, the default initial value is zero.

Single-port RAM has three working modes: 16×1, (16×1)×2, 32×1. The 16×1 mode includes a 16-bit RAM storage cell array, which includes a decoder with a 4-bit address, One data input and one data output. The (16×1)×2 mode includes two 16-bit RAM memory cell arrays. Each array includes a decoder with a 4-bit address, a data input and a data output, and the read operations of the two arrays are independent. The 32×1 mode includes a 32-bit RAM memory cell array, which includes a decoder with a 5-bit address, a data input and a data output.

Table 5 shows the signal sources when the FPGA logic block works in LUT mode and single-port RAM mode. FIG. 10 is a schematic diagram of a logic structure of an FPGA logic block as a single-port 32×1 RAM according to an embodiment of the present invention. As shown in Figure 5 and Figure 10, in this mode, the bypass input B0 of LC0 is used as the data input, the bypass input B1 of the second logic unit LC1 in the FPGA logic block is used as the fifth address bit, and the SR signal is used as the WE signal .

Table 5 Signal sources of FPGA logic blocks working in LUT mode and single-port RAM mode

RAM signal Function LUT mode signal DIN0 and DIN1 data input B0 and B1 A[3:0] address A0[3:0] or A1[3:0] A4 (for 32×1 only) address B1 WE write enable SR WCLK clock CK SPOs single port output XF0 or XF1

Dual-port 16×1 RAM consists of two arrays of 16-bit RAM memory cells. Each port includes a 4-bit address decoder. One port has a data input and a data output, and the other port includes a data output specified by another set of addresses.

Table 6 Signal sources when the FPGA logic block works in LUT mode and dual-port RAM mode

Table 6 shows the signal sources when the FPGA logic block works in LUT mode and dual-port RAM mode. FIG. 11 is a schematic diagram of a logic structure of an FPGA logic block as a dual-port RAM according to an embodiment of the present invention. As shown in Table 6 and Figure 11, in this mode, A0[3:0] is the read and write address of the first port and the write address of the second port, A1[3:0] is the second port dedicated read address. Based on the simultaneous read and write capabilities of dual-port RAM, its data processing speed is twice as fast as that of single-port RAM.

The application of distributed RAM must be determined according to timing requirements and resource utilization. 16×1 RAMs can be cascaded to form larger RAM storage arrays in depth and width. Since the logic blocks used to form a large-capacity RAM are scattered, the address lines will have a large fan-out and a long reading and writing time. One way to solve this problem is to use a pipeline design, where the data and address outputs are registered outputs, which can increase the operating frequency by reducing the fan-out of the address lines. When logically mapping the distributed RAM, the control bits S1, S2, S3, and D are used to configure the control circuit to transmit data and addresses. For example, the bypass signal B1 is used as a data input in the single-port (16×1)×2 mode, and as the fifth address bit in the single-port 32×1 mode. The write multiplexer is used to send data to the specified address. As shown in FIG. 11 , in order to maintain the write capability of the 5-tube memory unit, the size of the write enable NMOS transistor M1 must be consistent with the size of the N-type transfer transistor M2 of the 5-tube memory unit. The read multiplexer is shared with the LUT mode, so the read time of the distributed RAM is consistent with the logic delay of the LUT.

In the FPGA logic block of the present invention, using the LUT as a distributed RAM can make up for the shortage of memory module resources for applications with concentrated storage resources, and can improve resource utilization for applications with small-capacity storage. The biggest advantage of distributed RAM is that it can shorten the delay between storage and its driving logic, mainly because logic blocks can be used as both logic resources and storage resources. Since the distributed dual-port RAM has the ability to read asynchronously, its twice the data processing speed can save one clock cycle. In short, using LUT as a distributed RAM, in exchange for a large performance gain of FGPA at a small area cost.

Four: Application of multiple logic block connections

This embodiment provides an example in which multiple logic blocks are connected to each other to realize various functions. In the following, three specific applications are taken as examples.

1) When the FPGA logic block realizes fast carry chain logic: the carry input port CI of the FPGA logic block is directly connected with the carry input port CI of the first FPGA logic unit, and the carry output port CO of the first FPGA logic unit is connected with The carry input port CI of the second FPGA logic unit is directly connected, and the carry output port CO of the second FPGA logic unit is output through the carry output port CO of the logic block;

2) When a plurality of logic blocks are used in combination, the CO port of the FPGA logic block is connected to the CI port of the FPGA logic block on the adjacent upper side; the CO port of the PGA logic block at the top of a certain column of logic blocks and the bottom of the adjacent column on the right The CI port of the FPGA logic block at the end is connected;

3) When the FPGA logic block implements the shift register chain logic, the input port B of the logic unit passes through the logic block output directly or after being registered, and this output can enter the input port B of the logic unit in the logic block on the right side through the wiring channel .

It can be seen from the above embodiments that through the above method, the connection of multiple logic blocks can be realized, thereby realizing complex logic functions.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (22)

1. input look-up table LUT4 is characterized in that this LUT4 comprises: two 3 input look-up table LUT3 and four 2 select 1 multiplexer, and these two LUT3 are C-LUT3 and S-LUT3, and these four 2 are selected 1 multiplexer is FMUX, CMUX, SMUX and F4MUX;

Data-in port A0, A1, and the output after A2 (0) the process CMUX selection enters three input ports of C-LUT3 respectively;

Output after data-in port A0, A1 (0) select through SMUX with A3 (1), and the output after A2 (0) the process CMUX selection enters three input ports of S-LUT3 respectively;

Output after data-in port A3 (1) selects through FMUX with logic ' 0 ' enters the control port of F4MUX, and the output of S-LUT3 (0) is selected the output port F4 output of back from this LUT4 through F4MUX;

Among the described LUT4, Fmux, Smux and Cmux are respectively described FMUX, the control bit of SMUX and CMUX.

2. 4 input look-up tables according to claim 1 is characterized in that,

One of three input ports that output after described A2 (0) selects through CMUX enters C-LUT3 respectively are: the output after A2 (0) selects through CMUX with CI (1) enters one of described three input ports of described C-LUT3 respectively;

One of three input ports that output after described A2 (0) selects through CMUX enters S-LUT3 respectively are: the output after A2 (0) selects through CMUX with CI (1) enters one of described three input ports of described S-LUT3 respectively;

The output of described S-LUT3 (0) selects the back to be output as from the output port F4 of this LUT4 through F4MUX: the output CO (1) of C-LUT3 and the output (0) of S-LUT3 are selected the output port F4 output of back from described LUT4 through F4MUX.

3. LUT4 according to claim 2 is characterized in that, for described LUT4, and according to control bit Fmux, the various combination of Smux and Cmux, dispose the mode of operation of described LUT4:

As described Smux=0, Cmux=0, during Fmux=1, its mode of operation is LUT4; Or

As described Smux=0, Cmux=1, during Fmux=0, its mode of operation is a carry chain; Or

As described Smux=0, Cmux=0, during Fmux=0, its mode of operation is the carry begin chain; Or

As described Smux=1, Cmux=0, during Fmux=0, its mode of operation is a multiplier.

4. an on-site programmable gate array FPGA logical block is characterized in that, this fpga logic unit comprises that the described LUT4 of claim 2, D flip-flop and four 2 select 1 multiplexer BMUX, F5MUX, DMUX0 and DMUX1;

Described D flip-flop comprises: data-in port D, data-out port XQ, control input end mouth CE and SR, input end of clock mouth CK, overall set-reset port GSR;

The input port of described fpga logic unit comprises: the data-in port A0 of described 4 input LUT, A1, A2, A3 and data-in port B, F5I; The output port of described fpga logic unit comprises: the data-out port F4 of described 4 input LUT and data-out port XB, XF, XQ;

Wherein, the output port CO (0) of data-in port B (1) and C-LUT3 exports XB through behind the BMUX; Output behind output port F4 (0) the process F5MUX of data-in port F5I (1) and LUT4 enters 1 input port of DMUX1, and F4 enters 0 input port of DMUX1, and DMUX1 is output as XF; XF (1) and B (0) select back output to enter the data-in port D of D flip-flop through DMUX0, and the output port of described D flip-flop is as the data-out port XQ of described fpga logic unit;

Bmux, Dmux1 and Dmux0 are respectively B5MUX, the control bit of DMUX1 and DMUX0.

5. fpga logic according to claim 4 unit is characterized in that,

Described CI is as the special-purpose carry chain input port of described fpga logic unit; Described CO is as the special-purpose carry chain output port of described fpga logic unit.

6. fpga logic according to claim 4 unit is characterized in that, described Fmux, and Smux, Cmux, Bmux, Dmux1 and Dmux0 are 5 transistor memory units.

7. according to claim 4 or 5 described fpga logic unit, it is characterized in that, in the described fpga logic unit, according to control bit Bmux, the various combination of Dmux1 and Dmux0, the signal flow that disposes described fpga logic unit to:

Work as Bmux=0, F5mux=0, Dmux0=0, during Dmux1=0/1, described signal flow is to being CO driving XB, B drives D; Or

Work as Bmux=0, F5mux=0, Dmux0=1, during Dmux1=0/1, described signal flow is to being CO driving XB, LUT4 drives D; Or

Work as Bmux=0, F5mux=1, Dmux0=0, during Dmux1=0/1, described signal flow is to being CO driving XB, B drives D; Or

Work as Bmux=0, F5mux=1, Dmux0=1, during Dmux1=0/1, described signal flow is to being CO driving XB, LUT4 drives D; Or

Work as Bmux=1, F5mux=0, Dmux0=0, during Dmux1=0/1, described signal flow is to being B driving XB, B drives D; Or

Work as Bmux=1, F5mux=0, Dmux0=1, during Dmux1=0/1, described signal flow is to being B driving XB, LUT4 drives D; Or

Work as Bmux=1, F5mux=1, Dmux0=0, during Dmux1=0/1, described signal flow is to being B driving XB, B drives D; Or

Work as Bmux=1, F5mux=1, Dmux0=1, during Dmux1=0/1, described signal flow is to being B driving XB, LUT4 drives D.

8. according to claim 4 or 5 described fpga logic unit, it is characterized in that described d type flip flop comprises: core register and 42 select 1 multiplexer CKPOLMUX, SRSYNCMUX, SRSELMUX, QTYPEMUX;

This d type flip flop input comprises data input D, clock CK, and clock enables CE, and set/reset SR and overall set/reset GSR are output as data output Q;

SR (0) and logic ' 0 ' (1) are selected back output through SRSYNCMUX, and this output and GSR carry out or logic, and output process SRSELMUX output described or logic produces S (0) and R (1), is respectively the set/reset end of core register;

CK (1) and～CK (0) selects to enter the CK end of core register through CKPOLMUX, the input QL (0) of core register and QF (1) select to import Q through QTYPEMUX;

Described 2 select 1 multiplexer CKPOLMUX, SRSYNCMUX, and SRSELMUX, the control bit of QTYPEMUX is respectively ckpol, srsync, srsel, qtype is according to control bit ckpol, srsync, srsel, the various combination of qtype, d type flip flop are configured to dissimilar registers or latch.

9. fpga logic according to claim 8 unit is characterized in that, in the described d type flip flop,

According to control bit ckpol, d type flip flop is configured to just along triggering or the negative edge triggering; And/or

According to control bit srsync, d type flip flop is configured to synchronous or asynchronous; And/or

According to control bit srsel, d type flip flop is configured to set or resets; And/or

According to control bit qtype, d type flip flop is configured to register or latch.

10. a fpga logic piece is characterized in that, this logical block comprises: the first fpga logic unit, the second fpga logic unit, local interlinkage, and distributed RAM logic, wherein the first fpga logic unit and the second fpga logic unit are as claim 4 or 5 described fpga logic unit;

The port of this fpga logic piece comprises 2 overall input port-G＜1:0 〉, 12 input port-I＜11:0,8 output port-O＜7:0, special-purpose carry chain input port-CI, special-purpose carry chain output port-CO and 1 overall set-reset port-SR and 1 global write enable port-GWE;

Described local interlinkage comprises: being connected between logical block overall situation input port and logical block clock port and the control input end mouth; Being connected between logical block input port and the logical block input port; The logical block output port is connected with feedback between the logical block data input port; Connection between logic ' 0 ' and logic ' 1 ' and the logical block input port; Being connected between logical block output port and the logical block output port.

11. fpga logic piece according to claim 10, it is characterized in that: described distributed RAM logic comprises: SYN register, write control module, and write multiplexer, read multiplexer, two logical block shared data input A0[3:0 of this distributed RAM and fpga logic piece], A1[3:0], B0, B1, SR, CK, shared data output XF0 and XF1;

The data that described SYN register is used for writing synchronously, address and write control signal; The described control module of writing is used for controlling the trend that writes data; The described multiplexer of writing is used for new data are write the position of address designated memory locations; Described read multiplexer be in the fpga logic piece logical block 4 the input LUT;

Opposed polarity according to control ramckpol, distributed RAM can be configured to clock just along or negative edge write data, control bit S1 with write enable signal WE (SR is through the output after depositing) respectively in writing control module through carrying out and logic with door WENAND0 and WENAND1, all enter with the output of logic and to write writing of multiplexer control data; Control bit S2 comes writing of control data by control transmission door S2PASS in writing control module; Control bit S3 controls the selection that S3MUX0 and S3MUX1 control write address in SYN register, and in writing control module and Din1orA4 (B1 is through the output after depositing) be data input or the 5th address by carrying out controlling B1 with logic with door A4NAND; Control bit D controls the selection that DMUX controls write address in SYN register, and control transmission door DPASS comes writing of control data in writing control module; Control bit ramckpol controls RAMCKPOLMUX; Described fpga logic piece according to control bit (S1, S2, S3, the D) difference of polarity has different mode of operations.

12. fpga logic piece according to claim 10 is characterized in that:

Being connected between described logical block overall situation input port and logical block clock port and the control input end mouth comprises: overall input port G＜1〉directly link to each other overall input port G＜0 with the CK of two logical blocks〉control and can be connected with SR or CE by control bit;

Being connected between logical block input port and the logical block input port comprises: data-in port I＜6 〉, I＜0 〉, I＜9 〉, I＜3〉respectively with the data-in port A0 of the first fpga logic unit, A1, A2, A3 directly connects, I＜8 〉, I＜2 〉, I＜11 〉, I＜5〉respectively with the A0 of the second fpga logic unit, A1, A2, A3 directly connects, I＜7〉directly be connected with the B0 of the first fpga logic unit, I＜1〉B1 of the second fpga logic unit directly connects I＜10〉directly be connected I＜4 with CE〉directly be connected with SR;

The logical block output port is connected with feedback between the logical block data input port and comprises: output F4 in the first fpga logic unit directly is connected with second fpga logic unit input F5i, and output F4 in the second fpga logic unit imports F5i with the first fpga logic unit and directly is connected;

Connection between logic ' 0 ' and logic ' 1 ' and the logical block input port comprises: logic ' 0 ' can be connected with first fpga logic unit input B0 with logic ' 1 ', logic ' 0 ' can be connected with second fpga logic unit input B1 with logic ' 1 ', logic ' 0 ' and logic ' 1 ' can with the common input CE of two logical blocks in the fpga logic piece, SR, CE connects;

Being connected between logical block output port and the logical block output port comprises: output port O (0) is by the output port XQ0 and the XB0 of first logical block, the output port XF1 output of second logical block, output port O (1) is by the output port XF0 of first logical block, the output port XQ1 of second logical block and XB1 output, output port O (2) is by the output port XQ0 of first logical block, the output port XF1 output of second logical block, output port O (3) is by the output port XF0 and the XB0 of first logical block, the output port XQ1 output of second logical block, output port O (4) is by the output port XQ0 of first logical block, the output port XF1 of second logical block and XB1 output, output port O (5) is by the output port XF0 of first logical block, the output port XQ1 output of second logical block, output port O (6) is by the output port XQ0 of first logical block, the output port XF1 output of second logical block, output port O (7) is by the output port XF0 of first logical block, and the output port XQ1 of second logical block exports.

13. fpga logic piece according to claim 11 is characterized in that: in this fpga logic piece,

S1=0; S2=0; S3=0; During D=0, the mode of operation of described logical block is LUT; Or

S1=1; S2=0; S3=0; During D=0, the mode of operation of described logical block is single port 16 * 1RAM; Or

S1=1; S2=1; S3=0; During D=0, the mode of operation of described logical block is single port (16 * 1) * 2RAM; Or

S1=1; S2=0; S3=1; During D=0, the mode of operation of described logical block is single port 32 * 1RAM; Or

S1=1; S2=0; S3=0; During D=1, the mode of operation of described logical block is dual-port 16 * 1RAM.

14. fpga logic piece according to claim 13 is characterized in that: when the mode of operation of described logical block is single port 16 * 1RAM, single port (16 * 1) * 2RAM, when single port 32 * 1RAM or dual-port 16 * 1RAM:

During ramckpol=' 0 ', just along writing new data, during ramckpol=' 1 ', RAM writes new data in the clock negative edge to RAM at clock.

15. fpga logic piece according to claim 14, it is characterized in that: when the mode of operation of described fpga logic piece is described single port 16 * 1RAM, single port (16 * 1) * 2RAM, single port 32 * 1RAM, GWE is the global write enable signal of distributed RAM

The RAM signal is DIN0 and DIN1; Function is the data inputs; The logical block signal is B0 and B1;

The RAM signal is A[3:0]; Function is the address; The logical block signal is A0[3:0] or A1[3:0];

The RAM signal is the A4 for 32 * 1 uses; Function is the address; The logical block signal is B1;

The RAM signal is WE; Function enables for writing; The logical block signal is SR;

The RAM signal is WCLK; Function is a clock; The logical block signal is CK;

The RAM signal is SPO; Function is single port output; The logical block signal is XF0 or XF1.

16. fpga logic piece according to claim 13 is characterized in that: when the mode of operation of described fpga logic piece is described dual-port 16 * 1RAM:

The RAM signal is DIN; Function is the data inputs; The logical block signal is B0;

The RAM signal is A[3:0]; Function is read address or single two-port RAM write address for single port RAM; The logical block signal is A0[3:0];

The RAM signal is DPRA[3:0]; Function is the two-port RAM write address; The logical block signal is A1[3:0];

The RAM signal is WE; Function enables for writing; The logical block signal is SR;

The RAM signal is WCLK; Function is a clock; The logical block signal is CK;

The RAM signal is SPO; Function is single port RAM output; The logical block signal is XF0;

The RAM signal is DPO; Function is two-port RAM output; The logical block signal is XF1.

17. fpga logic piece according to claim 13 is characterized in that, when the mode of operation of described fpga logic piece is LUT4:

The output port F4 of the first fpga logic unit directly is connected with the second fpga logic unit input port F5I, and the output port F4 of the second fpga logic unit directly is connected with the input port F5I of the first fpga logic unit.

18. according to each described fpga logic piece among the claim 10-17, it is characterized in that: the local interlinkage of fpga logic piece inside all adopts the part interconnection pattern and is equally distributed, fpga logic piece input/output port is evenly distributed on around the logical block, and the input/output port of fpga logic unit is connected to fpga logic piece input/output port of the same type all around equably.

19. according to each described fpga logic piece among the claim 10-17, it is characterized in that: CK, CE and SR port are shared in the described first fpga logic unit and the second fpga logic unit.

20. fpga logic piece according to claim 10 is characterized in that: when described fpga logic piece is realized high-speed carry chain logic:

The carry input mouth CI of described fpga logic piece directly is connected with the carry input mouth CI of the first fpga logic unit, the carry output port CO of the first fpga logic unit directly is connected with the carry input mouth CI of the second fpga logic unit, and the carry output port CO of the second fpga logic unit is by the carry output port CO output of logical block.

21. fpga logic piece according to claim 20 is characterized in that: the CO port of described fpga logic piece links to each other with the CI port of adjacent fpga logic piece; And/or the CO port of the adjacent fpga logic piece with another of the CI port of described fpga logic piece links to each other.

22. fpga logic piece according to claim 10 is characterized in that: when described fpga logic piece was realized the shift register chain logic, the logical block input port B directly or after being deposited was passed logical block.

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