CN114783981A - Adapter board and package test system - Google Patents

Abstract

The application relates to an adapter plate and a package test system. The adapter plate comprises a substrate, a transmission structure, a test wire and a resistor; the transmission structure penetrates through the substrate, the test line is embedded in the substrate, one end of the test line is electrically connected with the transmission structure, the other end of the test line protrudes out of the surface of the substrate, and the resistor is embedded in the substrate and electrically connected with the test line and used for increasing the impedance of the test line so as to reduce the influence of the test line on a transmission structure signal. The packaging test system comprises a first chip, a second chip and an adapter plate which are arranged in a stacked mode; the adapter plate is located between the first chip and the second chip, the transmission structure is used for communicating the first chip and the second chip, and the test line is used for measuring signals of the transmission structure. Through the mode, on one hand, the impedance of the test line is increased to reduce the influence of the test line on the transmission structure signal; on the other hand, the distance between the resistor and the transmission structure is reduced, and the interference of the test line to the transmission structure signal is further reduced.

Description

Adapter board and package test system

technical field

The present application relates to the field of communication technologies, and in particular, to an adapter board and a packaging and testing system.

Background technique

Integrated fan-out package (InFO for short) is a packaging technology that directly interconnects a lower-level system on chip (System on chip) with an upper-level memory chip (Dynamic Random Access Memory, DRAM). Before the chips in the integrated fan-out package structure can be mass-produced, the signals need to be tested. Testing a large number of high-speed signals at the same time can get more reliable test results. When the memory chip is interconnected with the system-on-chip, the upper-layer memory chip is in a normal working state. However, the current testing method cannot simultaneously test a large number of high-speed signals of the memory chip when the memory chip is interconnected with the system-on-chip.

SUMMARY OF THE INVENTION

The present application provides an adapter board and a package testing system, which are used to meet the testing requirements of an integrated fan-out package.

The application provides an adapter board, including:

substrate;

a transmission structure that penetrates the substrate;

a test line, the test line is embedded in the substrate, one end of the test line is electrically connected to the transmission structure, and the other end protrudes from the surface of the substrate; and

A resistor, which is embedded in the substrate and is electrically connected to the test line, is used for increasing the impedance of the test line to reduce the influence of the test line on the signal of the transmission structure.

Optionally, the resistor is located on a side of the test line close to the transmission structure.

Optionally, the transmission structure is one of a via hole and a metal wire.

Optionally, the substrate is further provided with a plurality of ground holes, and the ground holes are located between the transmission structure and the transmission structure, between the test line and the test line, and between the transmission structure and the transmission structure. between the test lines.

Optionally, the line width of the test line is less than 40um.

Optionally, the distance between adjacent test lines is less than 40um.

Optionally, the base plate includes a first plate and a second plate arranged in layers, the area of the first plate is smaller than that of the second plate, and the first plate is located within the range of the second plate, so that The first board and the second board form an avoidance step; wherein the transmission structure penetrates the first board and the second board, and the test wire is embedded in the second board.

The embodiment of the present application also provides a packaging and testing system, including:

stacking the first chip and the second chip; and

an adapter board; the adapter board is located between the first chip and the second chip, the transmission structure is used for connecting the first chip and the second chip, and the test line is used for measuring the signal of the transmission structure.

Optionally, the adapter board further includes a first pad and a second pad, the first pad is located on one side surface of the substrate and is electrically connected to one end of the transmission structure, the first pad is Two pads are located on the surface of the substrate away from the first pad and are electrically connected to the other end of the transmission structure; the first pad is electrically connected to the first chip, and the second pad is electrically connected to the transmission structure. The second chip is electrically connected.

Optionally, the first chip is one of a memory chip and a system-on-chip, and the second chip is the other of the memory chip and the system-on-chip.

In the adapter board provided by the embodiment of the present application, by electrically connecting the resistor to the test line, the impedance of the test line is increased to reduce the influence of the test line on the transmission structure signal; The distance between the resistance and the transmission structure further reduces the interference of the test line to the signal of the transmission structure.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort.

1 is an exploded schematic diagram of a packaging and testing system provided by an embodiment of the present application;

2 is a schematic cross-sectional view of an embodiment of the packaging and testing system shown in FIG. 1;

3 is a schematic cross-sectional view of another embodiment of the packaging and testing system shown in FIG. 1;

4 is a schematic cross-sectional view of a package structure in the related art;

5 is a schematic cross-sectional view of an adapter plate in the packaging and testing system described in FIG. 2;

FIG. 6 is a schematic diagram of the interface of the packaging and testing system described in FIG. 2 with the circuit board and the functional device;

7 is a schematic cross-sectional view of an adapter board in the packaging and testing system shown in FIG. 6;

FIG. 8 is a schematic cross-sectional view of the adapter plate shown in FIG. 7 along the A-A direction.

Detailed ways

The present application will be further described in detail below with reference to the accompanying drawings and embodiments. It is particularly pointed out that the following examples are only used to illustrate the present application, but do not limit the scope of the present application. Similarly, the following embodiments are only some of the embodiments of the present application, but not all of the embodiments, and all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor a separate or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

Please refer to FIG. 1 , which is an exploded schematic diagram of a packaging and testing system provided by an embodiment of the present application. Embodiments of the present application provide a packaging and testing system 100 , which may include a first chip 10 , a second chip 20 and an adapter board 30 . in. The first chip 10 and the second chip 20 are stacked and arranged, and the adapter board 30 is located between the first chip 10 and the second chip 20. The adapter board 30 is used for connecting the first chip 10 and the second chip 20, and can detect the The transmission quality of the signal between one chip 10 and the second chip 20 .

It should be noted that the terms "first", "second" and "third" in this application are only used for description purposes, and should not be interpreted as indicating or implying relative importance or indicating the indicated technical features. quantity. Thus, a feature defined as "first", "second", "third" may expressly or implicitly include at least one of that feature. In the description of the present application, "a plurality of" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

Wherein, the first chip 10 may be one of a memory chip and a system-on-chip (also known as a system-on-chip), and the second chip 20 may be the other of a memory chip and a system-on-chip. On the one hand, the adapter board 30 is used to connect the memory chip and the SoC, and on the other hand, the adapter board 30 is used to detect the transmission quality of the signal between the memory chip and the SoC.

The technical terms and technical terms involved in this application are explained and explained here:

() InFO: (Integrated fan out package), an integrated fan-out package, a packaging technology that directly interconnects the lower-level system-on-chip with the upper-level memory chip.

(2) POP: (Packaging on Packaging), that is, stacking assembly, also known as stack packaging. POP is a package formed by stacking two or more packages.

(3) BGA: (Ball Grid Array), namely ball pin grid array packaging technology, high-density surface mounting packaging technology. At the bottom of the package, the pins are spherical and arranged in a lattice-like pattern, hence the name BGA.

(4) PCB: (Printed Circuit Board), the Chinese name is printed circuit board, also known as printed circuit board, is an important electronic component, a support body for electronic components, and a carrier for electrical connection of electronic components. Because it is made using electronic printing, it is called a "printed" circuit board.

(5) FPC: (Flexible Printed Circuit), that is, a flexible circuit board, which is a printed circuit board with high reliability and excellent flexibility made of polyimide or polyester film as the base material . It has the characteristics of high wiring density, light weight, thin thickness and good bendability.

(6) Die: the bare chip, the product form before the bare chip in each package (or chip) after the semiconductor components are manufactured. For example, a POP includes a bottom package and a top package, the bottom package is a packaged chip, and the bare chip is located in the bottom package.

(7) EMMI: (Emission Microscope), the low-light microscope, is a very useful and highly efficient analytical tool. It mainly detects photons emitted from the inside of the chip.

(8) SOCKET: DUT socket, used to fix and connect the DUT to the main board of the electronic equipment system, and can quickly put in, take out and fix the chip.

(9) MLO: (Multi-layer organic), multi-layer organic sheet.

(10) SLP: (substrate-like PCB), like a carrier board.

(11) SOC: (System on chip), an integrated system on a chip, also known as a system-on-chip.

(12) RDL: (Redistribution layer), redistribution layer.

(13) DRAM: (Dynamic Random Access Memory), dynamic random access memory, also known as memory chip, the main function principle is to use the amount of stored charge in the capacitor to represent whether a binary bit (bit) is 1 or 0.

Please refer to FIGS. 2 to 5 . FIG. 2 is a schematic cross-sectional view of an embodiment of the packaging and testing system shown in FIG. 1 , FIG. 3 is a cross-sectional schematic view of another embodiment of the packaging and testing system shown in FIG. 1 , and FIG. 4 is a related art FIG. 5 is a schematic cross-sectional view of the packaging structure in the packaging and testing system described in FIG. 2 .

Optionally, the first chip 10 and the second chip 20 may be part of an InFO package (as shown in FIG. 2 ), or may be a part of a POP package (as shown in FIG. 3 ), which is not limited herein.

Taking the InFO package as an example, before the InFO package is packaged, the first chip 10 and the second chip 20 are disposed separately. After the device is encapsulated, the first chip 10 and the second chip 20 are electrically connected (as shown in FIG. 4 ). Specifically, the first chip 10 can be electrically connected to the second chip 20 through pins. Generally, during testing, if the first chip 10 and the second chip 20 are separated and then tested, the InFO package cannot work normally. In this embodiment, the first chip 10 is a system-on-chip, and the second chip 20 is a memory chip.

Therefore, it is necessary to provide a new interposer board 30, wherein the interposer board 30 is located between the first chip 10 and the chip, so that the interposer board 30 can effectively electrically connect the first chip 10 and the second chip 20, so that the InFO package for efficient testing. At the same time, it is avoided that the first chip 10 and the second chip 20 pass the test in a separated state, and there is a problem after the first chip 10 and the second chip 20 are packaged.

Referring to FIG. 5 , the adapter board 30 may include a substrate 31 , a transmission structure 32 , a test line 33 and a resistor 34 . The substrate 31 is located between the first chip 10 and the second chip 20 , the transmission structure 32 penetrates the substrate 31 , and one end of the transmission structure 32 is electrically connected to the first chip 10 and the other end is electrically connected to the second chip 20 . The test line 33 is embedded in the substrate 31 , and one end of the test line 33 is electrically connected to the transmission structure 32 , and one end of the test line 33 away from the transmission structure 32 protrudes from the surface of the substrate 31 , and the test line 33 is used to lead out the transmission structure 32 . signal of. The resistor 34 is embedded in the substrate 31 and is electrically connected to the test line 33 for increasing the impedance of the test line 33 to reduce the influence of the test line 33 on the transmission structure 32 .

Specifically, the substrate 31 may be one of a printed circuit board, a flexible circuit board, a multi-layer organic board, and a carrier-like board, which is not specifically limited herein. Specifically, the substrate 31 may include a first surface 31 a and a second surface 31 b disposed opposite to each other, the first surface 31 a faces the first chip 10 and is attached to the first chip 10 , and the second surface 31 b faces the second chip 20 and is attached to the first chip 10 . The second surface 31b is attached.

Please refer to FIG. 6 and FIG. 7 , FIG. 6 is a schematic diagram of the interface of the packaging and testing system described in FIG. 2 cooperating with circuit boards and functional devices, and FIG. 7 is a cross-sectional schematic diagram of the adapter board in the packaging and testing system shown in FIG. 6 . Optionally, the InFO package may further include a circuit board 200 and a functional device 300 fixed on the circuit board 200 . The first chip 10 is fixed on the circuit board 200 and is electrically connected to the circuit board 200 , and the functional device 300 is connected to the second chip. 20 adjacent settings.

Optionally, the base plate 31 may include a first plate 311 and a second plate 312 arranged in layers, the area of the first plate 311 is smaller than that of the second plate 312, and the first plate 311 is located within the range of the second plate 312, such that The first plate 311 and the second plate 312 form an avoidance step 310 . Wherein, the avoidance step 310 can effectively avoid the functional device 300 on the circuit board 200 to prevent the large size of the substrate 31 from affecting the setting of the functional device 300 . The first surface 31a is located on the surface of the first plate 311 away from the second plate 312 , and the second surface 31b is located at the surface of the second plate 312 away from the first plate 311 .

Optionally, the thickness of the base plate 31 may be 2 mm to ensure that the base plate 31 has sufficient structural strength to prevent probes from external testing equipment from damaging the adapter board 30 or causing the base plate 31 to deform. Specifically, the thickness of the first plate 311 may be 1 mm, and the thickness of the second plate 312 may be 1 mm.

Please refer to FIG. 8 . FIG. 8 is a schematic cross-sectional view of the adapter plate shown in FIG. 7 along the direction A-A. The substrate 31 is further provided with a plurality of ground holes 313, and the ground holes 313 are located between the transmission structure 32 and the transmission structure 32, between the test line 33 and the test line 33, and between the transmission structure 32 and the test line 33, so as to reduce the test Signal crosstalk between the lines 33 , between the transmission structures 32 , and between the transmission structures 32 and the test lines 33 to improve the test accuracy of the packaging and testing system 100 . Specifically, when the ground hole 313 is located between the transmission structures 32, the ground hole 313 penetrates the first plate 311 and the second plate 312; when the ground hole 313 is located between the test line 33 and the test line 33, the ground hole 313 penetrates the second plate 312 ; when the ground hole 313 is located between the transmission structure 32 and the test line 33 , the ground hole 313 can penetrate through the second plate 312 .

The substrate 31 also has a plurality of ground wires 314 , and the ground wires 314 are used to connect the ground holes 313 and the ground plane of the substrate 31 and to ground the ground holes 314 . The ground wire 314 is located between the transmission structure 32 and the transmission structure 32 , between the test wire 33 and the test wire 33 , and between the transmission structure 32 and the test wire 33 , so as to reduce the distance between the test wires 33 and the transmission structure 32 And the signal crosstalk between the transmission structure 32 and the test line 33 , so as to improve the test accuracy of the package test system 100 .

The transmission structure 32 penetrates through the substrate 31 , and the substrate 31 is located between the first chip 10 and the second chip 20 , so that one end of the transmission structure 32 is electrically connected to the first chip 10 and the other end is electrically connected to the second chip 20 . The interconnection of the first chip 10 and the second chip 20 . The number of transmission structures 32 may be one, two or three, which are not specifically limited herein. Specifically, the transmission structure 32 penetrates the first plate 311 and the second plate 312 .

Please continue to refer to FIG. 7 , optionally, the adapter board 30 further includes a first pad 35 and a second pad 36 , the first pad 35 is located on the first surface 31 a and is electrically connected to one end of the transmission structure 32 , The second pad 36 is located on the second surface 31 b and is electrically connected to the other end of the transmission structure 32 . In other words, the first pad 35 is located on one side surface of the substrate 31 and is electrically connected to one end of the transmission structure 32 , and the second pad 36 is located on the surface of the substrate 31 away from the first pad 35 and is electrically connected to the other end of the transmission structure 32 . sexual connection. Wherein, the first pad 35 is electrically connected to the first chip 10, such as by welding, and the second pad 36 is electrically connected to the second chip 20, thereby making the first chip 10 and the second chip 20 communicate with each other, thereby enabling the transmission of signals can be efficiently transmitted in the transmission structure 32 .

In this embodiment, the transmission structure 32 is a via hole, that is, a metallized hole. Specifically, the substrate 31 is provided with a through hole penetrating the substrate 31 , and the surface of the through hole is plated with a metal surface layer, so that the through hole has electrical conductivity. Understandably, the metal surface layer of the via hole enables the via hole to effectively transmit electrical signals, and the via hole designed in the hollow structure of the via hole can effectively dissipate heat, thereby improving the reliability of the adapter board 30 . In other embodiments, the transmission structure 32 may also be a metal wire. Specifically, the metal wire is embedded in the substrate 31 , and one end of the metal wire is electrically connected to the first pad 35 , and the other end of the metal wire is electrically connected to the second pad 36 . Electrical connection. In other words, the transmission structure 32 can be one of a via hole and a metal line, which is not specifically limited herein.

The test wire 33 is embedded in the substrate 31 , one end of the test wire 33 is electrically connected to the transmission structure 32 such as a via hole, and the other end of the test wire 33 protrudes from the surface of the substrate 31 and can be electrically connected to an external test device . It can be understood that the test wire 33 can be used to acquire the electrical signal on the transmission structure 32 and transmit the electrical signal transmitted by the transmission structure 32 to the external test equipment.

Optionally, the adapter board 30 further includes a third pad 37 . The third pad 37 is fixed on the surface of the substrate 31 and is electrically connected to one end of the test wire 33 protruding from the surface of the substrate 31 . The probes of the external test equipment are connected to the third pads 37 by welding, so as to realize the electrical connection between the external test equipment and the test wire 33 . In this embodiment, the third pad 37 is located on the second surface 31b. In other embodiments, the third pad 37 may also be located on the first surface 31a, or located on both the first surface 31a and the second surface 31b, which is not limited herein.

Optionally, the test wire 33 may include a vertically connected first wire 331 and a second wire 332, wherein the first wire 331 is parallel to the second surface 31b of the substrate 31 and embedded in the second plate 312, and the second wire 332 An end of the second wire 332 which is perpendicular to the second surface 31 b and away from the first wire 331 is electrically connected to the third pad 37 on the second surface 31 b , so that the test wires 33 are regularly arranged in the substrate 31 .

Optionally, the number of test lines 33 is at least two, and two adjacent test lines 33 are arranged in parallel and spaced apart. element.

In this embodiment, the line width of each test line 33 is less than 40um, and the line spacing between two adjacent test lines 33 is less than 40um. Specifically, the adapter board 30 can adopt the MLO process, the SLP process, the packaging substrate 31 manufacturing process, etc., so that the minimum line width of the test lines 33 can be 1 mil (that is, 25.4um), and between two adjacent test lines 33 The line spacing can be achieved to 1mil to meet the test of high I/O (Input/Output) density chips. Compared with the adapter board 30 manufactured by the traditional PCB process, the test line 33 of the adapter board 30 provided in the embodiment of the present application has a smaller line width and line spacing. On the one hand, the area of the adapter board 30 can be effectively reduced, and on the other hand the wiring It is more flexible, and it is convenient for the test line 33 to be routed.

Further, because the line width and line spacing of the test lines 33 of the adapter board 30 are smaller, the routing of the test lines 33 is more flexible, the smaller the space the test lines 33 occupy on the substrate 31, and the more ground holes 313 can be arranged. , in order to reduce the crosstalk between the signals and improve the accuracy of the test.

It can be understood that increasing the total resistance of the test line 33 (ie increasing the impedance of the test line 33 ) helps to reduce the influence of the test line 33 on the signal transmission of the transmission structure 32 and obtain more accurate test data. The electronics are embedded in the substrate 31 and electrically connected to the test line 33 for increasing the impedance of the test line 33 to reduce the influence of the test line 33 on the signal of the transmission structure 32 .

In this embodiment, the resistor 34 is embedded in the second plate 312 and disposed close to the transmission structure 32 . The resistor 34 can divide the first wire 331 into an interference segment 3311 and a connection end 3312, wherein one end of the interference segment 3311 is connected to the transmission structure 32, the other end is connected to the resistor 34, one end of the connection end 3312 is connected to the resistor 34, and the other end is connected to the Two wires 332 . When calculating the impedance matching of the test line 33 , the impedance of the interference section 3311 is usually not considered, that is, the smaller the resistance of the interference section 3311 is, the smaller the impedance matching interference of the interference section 3311 to the test line 33 is. The resistance value of the wire is proportional to the length of the wire, that is, the shorter the interference section 3311 is, the smaller the influence of the test wire 33 on the transmission structure 32 is.

In the adapter board 30 provided by the embodiment of the present application, by electrically connecting the resistor 34 to the test line 33, the impedance of the test line 33 is increased to reduce the influence of the test line 33 on the signal of the transmission structure 32; In the substrate 31 , the distance between the resistor 34 and the transmission structure 32 is reduced, thereby further reducing the interference of the test line 33 to the signal of the transmission structure 32 .

The above descriptions are only part of the embodiments of the present application, and are not intended to limit the protection scope of the present application. Any equivalent device or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related The technical field is similarly included in the scope of patent protection of this application.

Claims (10)

1. An interposer, comprising:

a substrate;

a transmission structure penetrating through the substrate;

the test wire is embedded in the substrate, one end of the test wire is electrically connected with the transmission structure, and the other end of the test wire protrudes out of the surface of the substrate; and

the resistor is embedded in the substrate and electrically connected with the test line, and is used for increasing the impedance of the test line so as to reduce the influence of the test line on the transmission structure signal.

2. The patch panel of claim 1, wherein the resistor is located on a side of the test line proximate the transmission structure.

3. The interposer as recited in claim 1, wherein the transmission structure is one of a via and a metal line.

4. The interposer as claimed in claim 1, wherein the substrate further comprises a plurality of ground holes, and the ground holes are located between the transmission structure and the transmission structure, between the test line and the test line, and between the transmission structure and the test line.

5. The interposer as recited in claim 1, wherein the test lines have a line width of less than 40 um.

6. The interposer as recited in claim 1, wherein a distance between adjacent test lines is less than 40 um.

7. The interposer as recited in claim 1, wherein the substrate comprises a first sheet and a second sheet stacked together, the first sheet having a smaller area than the second sheet and being located within the second sheet such that the first sheet and the second sheet form an avoidance step; the transmission structure penetrates through the first plate and the second plate, and the test wire is embedded in the second plate.

8. A package test system, comprising:

stacking a first chip and a second chip; and

the interposer as recited in any one of claims 1-7; the adapter plate is located between the first chip and the second chip, the transmission structure is used for communicating the first chip with the second chip, and the test wire is used for measuring signals of the transmission structure.

9. The package test system of claim 8, wherein the interposer further comprises a first pad and a second pad, the first pad being located on a side surface of the substrate and electrically connected to one end of the transmission structure, the second pad being located on a surface of the substrate away from the first pad and electrically connected to the other end of the transmission structure; the first bonding pad is electrically connected with the first chip, and the second bonding pad is electrically connected with the second chip.

10. The package test system according to claim 8, wherein the first chip is one of a memory chip and a system-on-chip, and the second chip is the other of the memory chip and the system-on-chip.

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