CN114759080A - Semiconductor device and preparation method thereof - Google Patents

Abstract

The application provides a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. And the energy band is adjusted by virtue of the higher doping concentration of the P-type heavily doped layer to reduce the concentration of two-dimensional electron gas at the channel below the grid, and the depletion region below the grid is enlarged, so that the electric field peak value below the grid is relieved, and the withstand voltage of the device is improved. The extension part of the first P-type lightly doped layer at least covers the side surface of the P-type heavily doped layer, so that the electric field on the side surface of the gate can be effectively modulated by the extension part, the electric field intensity or the electric field peak value on the side surface of the gate is reduced, and the voltage resistance of the device is improved.

Description

A kind of semiconductor device and preparation method thereof

technical field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device and a preparation method thereof.

Background technique

Due to the limitations of the first- and second-generation semiconductor materials represented by Si and GaAs, the third-generation wide-bandgap semiconductor materials have been rapidly developed due to their excellent properties. As one of the cores of third-generation semiconductor materials, GaN material is special compared to Si, GaAs and SiC in its polarization effect. Taking advantage of this particularity, AlGaN/GaN high electron mobility transistors have been developed, and AlGaN/GaN HEMTs are GaN-based microelectronic devices fabricated on the basis of AlGaN/GaN heterojunction materials. AlGaN/GaN heterojunctions form a high-density two-dimensional electron gas (2DEG) at the interface of the heterojunction through spontaneous polarization and piezoelectric polarization. This two-dimensional electron gas has high mobility , so that the AlGaN/GaN HEMTs have very low on-resistance.

In the existing GaN devices, in order to improve the device performance, a P-type layer is often introduced under the gate, but when the doping concentration of the P-type layer is too low, the threshold value of the device is often low, and when the doping concentration of the P-type layer is too low. When the concentration is too high, the interfacial electric field of the Schottky structure formed by the gate metal and the P-type layer will be very high under the gate forward bias, thus limiting the gate forward withstand voltage, and considering the device's There is gate leakage current in the gate, which will affect the reliability of the device.

SUMMARY OF THE INVENTION

The purpose of the present application is to provide a semiconductor device and a preparation method thereof in view of the above-mentioned deficiencies in the prior art, so that the semiconductor device can reduce the gate leakage current while increasing the gate threshold value, and effectively improve the gate side surface leakage. Electric field modulation effect.

To achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

In one aspect of the embodiments of the present application, a semiconductor device is provided, including a substrate and a semiconductor layer disposed on the substrate, the semiconductor layer includes a source region, a drain region and a gate region, and the gate region of the semiconductor layer is in sequence A stacked P-type heavily doped layer and a first P-type lightly doped layer are provided, the first P-type lightly doped layer includes a continuous body portion and an extension portion, and the body portion is located on the top surface of the P-type heavily doped layer, The extension part covers at least the side surface of the P-type heavily doped layer, source metal and drain metal are respectively provided in the source region and drain region of the semiconductor layer, and gate metal is provided on the main body.

Optionally, the extension portion includes a continuous first modulation portion and a second modulation portion, the first modulation portion covers the side surface of the P-type heavily doped layer, and the second modulation portion is located on the surface of the semiconductor layer and faces the source region and/or the drain. polar region extension.

Optionally, a groove corresponding to the second modulation part is provided on the surface of the semiconductor layer, the groove is located on the side of the P-type heavily doped layer close to the source region and/or the drain region, and the second modulation part at least partially corresponds to located in the groove.

Optionally, the second modulation part includes a first sub-section and a second sub-section which are continuously arranged in a direction away from the P-type heavily doped layer, the first sub-section is located in the groove, and the second sub-section is located outside the groove.

Optionally, a second P-type lightly doped layer is further disposed between the P-type heavily doped layer and the semiconductor layer.

Optionally, the extension part covers at least the side surface of the P-type heavily doped layer and the side surface of the second P-type lightly doped layer.

Optionally, the first P-type lightly doped layer, the second P-type lightly doped layer and the P-type heavily doped layer are all P-type gallium nitride layers.

In another aspect of the embodiments of the present application, a method for fabricating a semiconductor device is provided. The method includes: forming a semiconductor layer on a substrate, where the semiconductor layer includes a source region, a drain region and a gate region; A stacked P-type heavily doped layer and a first P-type lightly doped layer are sequentially formed, wherein the first P-type lightly doped layer includes a continuous body portion and an extension portion, and the body portion is located at the edge of the P-type heavily doped layer. On the top surface, the extension part covers at least the side surface of the P-type heavily doped layer; a source metal and a drain metal are respectively formed in the source region and the drain region of the semiconductor layer; and a gate metal is formed on the body part.

Optionally, the extension portion includes a continuous first modulation portion and a second modulation portion, the first modulation portion covers the side surface of the P-type heavily doped layer, and the second modulation portion is located on the surface of the semiconductor layer and faces the source region and/or the drain. polar region extension.

Optionally, sequentially forming the stacked P-type heavily doped layer and the first P-type lightly doped layer in the gate region of the semiconductor layer includes: forming a P-type heavily doped layer in the gate region of the semiconductor layer; Etch the semiconductor layer on the side of the P-type heavily doped layer close to the source region and/or the drain region to form a groove; a first P-type lightly doped layer is formed on the P-type heavily doped layer, wherein the second P-type lightly doped layer is formed on the P-type heavily doped layer. The modulation part is at least partially located in the groove correspondingly.

The beneficial effects of this application include:

The application provides a semiconductor device and a preparation method thereof. The semiconductor device includes a substrate and a semiconductor layer disposed on the substrate, and a gate includes a P-type heavily doped layer, a first The P-type lightly doped layer and the gate metal, wherein the gate metal forms a Schottky contact with the first P-type lightly doped layer. Since the doping concentration of the first P-type lightly doped layer is low, the Schottky contact can be increased. The Teky barrier reduces the Schottky electric field strength, thereby increasing the gate forward withstand voltage and reducing the gate leakage current. And in order to consume the two-dimensional electron gas (2DEG) at the channel under the gate, so as to reduce the concentration of 2DEG at the channel under the gate, the energy can be adjusted by the higher doping concentration of the P-type heavily doped layer. The band is adjusted to achieve that, due to the arrangement of the P-type heavily doped layer, the depletion region under the gate can be enlarged, thereby reducing the electric field peak under the gate and improving the withstand voltage of the device. The first P-type lightly doped layer includes a continuous body portion and an extension portion. The body portion covers the top surface of the P-type heavily doped layer to facilitate Schottky contact with the gate metal, and the extension portion covers at least the P-type heavy doped layer. The side surface of the doped layer, thus, the electric field at the side of the gate can be effectively modulated by the extension portion, thereby reducing the electric field intensity or the peak value of the electric field at the side of the gate, and helping to improve the withstand voltage of the device.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following drawings will briefly introduce the drawings that need to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

1 is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of the present application;

FIG. 2 is one of the schematic diagrams of the preparation state of a semiconductor device provided by an embodiment of the present application;

FIG. 3 is the second schematic diagram of the preparation state of a semiconductor device provided by the embodiment of the present application;

FIG. 4 is the third schematic diagram of the preparation state of a semiconductor device provided by the embodiment of the present application;

FIG. 5 is the fourth schematic diagram of the preparation state of a semiconductor device provided by the embodiment of the present application;

6 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

FIG. 7 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application;

FIG. 8 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present application;

FIG. 9 is a schematic structural diagram of still another semiconductor device according to an embodiment of the present application.

Icon: 100-substrate; 110-semiconductor layer; 120-P-type heavily doped layer; 130-recess; 140-first P-type lightly doped layer; 141-body part; 142-extension part; 143-th 144-second modulation part; 145-first sub-section; 146-second sub-section; 150-second P-type lightly doped layer; 160-passivation layer; 170-dielectric layer; 180-source pole metal; 190 - drain metal; 200 - gate metal.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of the present application, but not all of the embodiments. The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending on" another element, it can be directly on or extending directly to the other element elements, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending over" another element, it can be directly on or directly on the other element Extends over another element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending directly on" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is also to be understood that terms used herein are to be construed to have the same meaning as they have in the context of this specification and related art, and not to be construed in an idealized or overly formal sense unless explicitly defined as such herein.

In one aspect of the embodiments of the present application, a semiconductor device is provided, as shown in FIG. 7 to FIG. 9 , including a substrate 100 and a semiconductor layer 110 disposed on the substrate 100 , and the semiconductor layer 110 includes a source region and a drain region and the gate region, the source metal 180 in ohmic contact with the semiconductor layer 110 is arranged in the source region, the drain metal 190 in ohmic contact with the semiconductor layer 110 is arranged in the drain region, and the gate is correspondingly arranged in the gate region, thereby , the source metal 180 and the drain metal 190 cooperate with the gate to form a transistor device.

Please continue to refer to FIG. 7 to FIG. 9 , the gate includes a P-type heavily doped layer 120 , a first P-type lightly doped layer 140 and a gate metal 200 , which are sequentially stacked on the gate region of the semiconductor layer 110 , wherein the gate The metal 200 forms a Schottky contact with the first P-type lightly doped layer 140. Since the doping concentration of the first P-type lightly doped layer 140 is low, the Schottky barrier can be increased, and the Schottky electric field strength can be reduced. Thereby, the gate leakage current is reduced while the gate forward withstand voltage is increased. And in order to consume the two-dimensional electron gas (2DEG) at the channel under the gate, so as to reduce the concentration of 2DEG at the channel under the gate, the higher doping concentration of the P-type heavily doped layer 120 can be used to The energy band is adjusted to achieve that, due to the arrangement of the P-type heavily doped layer 120 , the depletion region under the gate can be enlarged, thereby reducing the electric field peak under the gate and improving the withstand voltage of the device.

As shown in FIG. 6 to FIG. 9 , the first P-type lightly doped layer 140 includes a continuous body portion 141 and an extension portion 142 , and the body portion 141 covers the top surface of the P-type heavily doped layer 120 , which is convenient to realize with the gate metal 200 . Schottky contact, and the extension portion 142 covers at least the side surface of the P-type heavily doped layer 120. Therefore, the electric field at the side of the gate can be effectively modulated by the extension portion 142, thereby reducing the electric field intensity or peak value of the electric field at the side of the gate. , which helps to improve the withstand voltage of the device.

In some embodiments, the substrate 100 may be a silicon carbide substrate 100, a gallium nitride substrate 100, a silicon substrate 100, a sapphire substrate 100, a diamond substrate 100, etc., which are not limited in this application, and can be determined according to Make a reasonable choice according to actual needs.

In some embodiments, the semiconductor layer 110 is formed by epitaxial growth on the substrate 100 , the semiconductor layer 110 may include a plurality of active semiconductor layers 110 , and at an interface of at least two active semiconductor layers 110 of the plurality of active semiconductor layers 110 A two-dimensional electron gas (2DEG) can be formed there, so as to serve as a current path between the source metal 180 and the drain metal 190 when the transistor device is turned on.

Depending on the range covered by the extension portion 142 , corresponding to electric field modulation that can achieve different effects, for ease of description, the embodiments of the present application will be described below with reference to FIGS. 6 to 9 .

In an embodiment, referring to FIG. 7 , the stacked P-type heavily doped layer 120 , the first P-type lightly doped layer 140 and the gate metal 200 are sequentially arranged in the gate region of the semiconductor layer 110 , wherein, for In terms of the first P-type lightly doped layer 140, the first P-type lightly doped layer 140 includes a continuous body portion 141 and an extension portion 142, and the body portion 141 covers the top surface of the P-type heavily doped layer 120, so as to facilitate the The gate metal 200 realizes Schottky contact, and the extension 142 covers one side of the P-type heavily doped layer 120 close to the source region and the other side of the P-type heavily doped layer 120 close to the drain region. The electric field on the sides of the gate close to the source region and the drain region can be effectively modulated by the extension portion 142, thereby reducing the electric field intensity or the peak value of the electric field on the sides of the gate close to the source region and the drain region, which helps to improve the device performance. Pressure resistant. In addition, when the extension portion 142 covers a side of the P-type heavily doped layer 120 close to the source region, the electric field on the side is modulated; and when the extension portion 142 covers the P-type heavily doped layer 120 and is close to the drain region When one side is on the side, the electric field on the side is modulated correspondingly.

In an embodiment, referring to FIG. 8 , the stacked P-type heavily doped layer 120 , the first P-type lightly doped layer 140 and the gate metal 200 are sequentially arranged in the gate region of the semiconductor layer 110 , wherein, for In terms of the first P-type lightly doped layer 140, the first P-type lightly doped layer 140 includes a continuous body portion 141 and an extension portion 142, and the body portion 141 covers the top surface of the P-type heavily doped layer 120, so as to facilitate the The gate metal 200 realizes Schottky contact, and the extension parts 142 are divided into two groups. For one set of extension parts 142: the first modulation part 143 covers the side of the P-type heavily doped layer 120 close to the source region, the second modulation part 144 is continuous with the first modulation part 143, and the second modulation part 144 is made of semiconductor The surface of the layer 110 extends toward the source region for a certain length; for another group of extension parts 142: the first modulation part 143 covers the side of the P-type heavily doped layer 120 close to the drain region, and the second modulation part 144 is connected to the first modulation part 143. The modulation part 143 is continuous and the second modulation part 144 extends from the surface of the semiconductor layer 110 to the drain region for a certain length, so that the electric field peak on the side of the gate can not only be relieved by the first modulation part 143 in the two groups, but also The electric field within a certain distance around the gate can be further effectively modulated by means of the second modulation part 144 in the two groups extending outward for a certain length, thereby expanding the range of electric field modulation.

In addition, when the first modulating portion 143 and the second modulating portion 144 of the extension portion 142 are located on the side of the P-type heavily doped layer 120 close to the source region, the electric field on the side is modulated accordingly; and when the extension portion 142 When the first modulation part 143 and the second modulation part 144 are located on the side of the P-type heavily doped layer 120 close to the drain region, the electric field on the side is modulated accordingly.

In one embodiment, please refer to FIG. 3 , by etching the semiconductor layer 110 on opposite sides of the P-type heavily doped layer 120 , the P-type heavily doped layer 120 and the source region and the P-type heavily doped layer 120 are etched respectively. A groove 130 is formed on the semiconductor layer 110 between the impurity layer 120 and the drain region, and the groove 130 is close to the P-type heavily doped layer 120, so that the gate is formed by etching a certain depth to form the groove 130. The barrier layers on both sides of the pole become thinner, thereby reducing the concentration of 2DEG at the channel below the groove 130, and assisting in realizing electric field modulation on both sides of the gate. In addition, the groove 130 may be formed only on one side of the gate by etching, so as to correspondingly realize modulation of the electric field on the side.

In an embodiment, please refer to FIG. 3 and FIG. 8 in combination, the stacked P-type heavily doped layer 120 , the first P-type lightly doped layer 140 and the gate metal 200 are sequentially disposed in the gate region of the semiconductor layer 110 , wherein, for the extension part 142 of the first P-type lightly doped layer 140 , each group of extension parts 142 includes a first modulation part 143 continuous with the body part 141 and a second modulation part 143 continuous with the first modulation part 143 part 144, for the second modulation part 144 of one group of extension parts 142: the second modulation part 144 is continuous with the first modulation part 143 and the second modulation part 144 is filled in the groove of the surface of the semiconductor layer 110 close to the source region 130; for the second modulation part 144 of the other group of extension parts 142: the second modulation part 144 is continuous with the first modulation part 143 and the second modulation part 144 is filled in the concave surface of the semiconductor layer 110 near the drain region Therefore, on the basis of alleviating the electric field peak on the side of the gate by means of the first modulation part 143 in the two groups, the second modulation part 144 in the two groups can be combined with the groove 130 to adjust the surrounding of the gate. The electric field achieves more efficient modulation. In addition, the groove 130 can be combined with the second modulation part 144 only on one side of the gate, so as to correspondingly realize the modulation of the electric field on the side.

In one embodiment, please refer to FIG. 3 , FIG. 5 and FIG. 6 , the stacked P-type heavily doped layer 120 , the first P-type lightly doped layer 140 and the gate are sequentially arranged in the gate region of the semiconductor layer 110 The pole metal 200 , wherein, for the extension parts 142 of the first P-type lightly doped layer 140 , each group of extension parts 142 includes a first modulation part 143 continuous with the body part 141 and a modulation part 143 continuous with the first modulation part 143 . The second modulation part 144, the second modulation part 144 in each group includes a first sub-section 145 continuous with the first modulation part 143 and a second sub-section 146 continuous with the first sub-section 145, for one group of the first sub-section 145 For the two modulation parts 144: the first sub-part 145 is filled in the groove 130 on the surface of the semiconductor layer 110 close to the source region, and the second sub-part 146 is located outside the groove 130 and extends toward the source region for a certain length; For another set of second modulation parts 144: the first sub-part 145 is filled in the groove 130 on the surface of the semiconductor layer 110 close to the drain region, and the second sub-part 146 is located outside the groove 130 and extends toward the drain region for a certain amount Therefore, on the basis of alleviating the electric field peak on the side of the gate by means of the first modulation part 143 in the two groups, the grooves 130 (first order), The consumption of the 2DEG around the gate by the second sub-section 146 (second order) also changes in a second order, that is, the first order closer to the gate realizes more consumption, and the second order slightly further away from the gate realizes slightly more consumption. The consumption is lower, so that the concentration of 2DEG gradually increases from the gate to the source region and the drain region, thereby avoiding the possibility of a sudden increase in the electric field at the edge of the first P-type lightly doped layer 140 Introduced new electric field peaks. In addition, in the same way, the first sub-section 145 and the second sub-section 146 can also be provided only on one side of the gate, so as to correspondingly realize the modulation of the electric field on the side.

In an embodiment, please refer to FIG. 3 and FIG. 9 in combination, the difference from the previous embodiment is that a second P-type lightly doped layer is further provided between the P-type heavily doped layer 120 and the semiconductor layer 110 150 , the first modulation part 143 covers the side surface of the P-type heavily doped layer 120 and also covers the side surface of the second P-type lightly doped layer 150 correspondingly. The electric field at the gate edge increases under high voltage. The low doping concentration of the second P-type lightly doped layer 150 can reduce the electric field strength, make avalanche breakdown less likely to occur at the corners, and increase the gate withstand voltage.

In some embodiments, the first P-type lightly doped layer 140 , the second P-type lightly doped layer 150 and the P-type heavily doped layer 120 are all P-type gallium nitride layers.

In addition, as shown in FIG. 6 to FIG. 9 , a passivation layer 160 and a dielectric layer 170 stacked in sequence may also be disposed between the gate electrode and the source metal 180 and between the gate electrode and the drain metal 190 .

Another aspect of the embodiments of the present application provides a method for fabricating a semiconductor device, as shown in FIG. 1 , the method includes:

S010: forming a semiconductor layer 110 on the substrate 100, where the semiconductor layer 110 includes a source region, a drain region and a gate region.

As shown in FIG. 2 , first, a semiconductor layer 110 is deposited on the substrate 100 by a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or atomic layer deposition (ALD). The semiconductor layer 110 includes a source region, a drain region and a region and gate region, it should be known that the source region, the drain region and the gate region are respectively the regions corresponding to the subsequent formation of the source metal 180, the drain metal 190 and the gate, which belong to the pre-divided virtual regions. They are spaced apart from each other, and the gate region is located between the source region and the drain region.

S020: A stacked P-type heavily doped layer 120 and a first P-type lightly doped layer 140 are sequentially formed in the gate region of the semiconductor layer 110, wherein the first P-type lightly doped layer 140 includes a continuous body portion 141 and the extension portion 142 , the body portion 141 is located on the top surface of the P-type heavily doped layer 120 , and the extension portion 142 at least covers the side surface of the P-type heavily doped layer 120 .

As shown in FIG. 2 , a whole P-type layer is first epitaxially grown in the gate region of the semiconductor layer 110 , and then only a part of the P-type layer is left in the gate region as the P-type heavily doped layer 120 by etching.

As shown in FIG. 4 and FIG. 5 , the entire P-type layer is then epitaxially formed, and a part of the P-type layer is reserved in the gate region by etching as the first P-type lightly doped layer 140 , the first P-type lightly doped layer. 140 includes a continuous body portion 141 and an extension portion 142 , the body portion 141 is located on the top surface of the P-type heavily doped layer 120 , and the extension portion 142 at least covers the side surface of the P-type heavily doped layer 120 . In this way, the electric field on the side of the gate can be effectively modulated by the extension portion 142, thereby reducing the electric field intensity or the peak value of the electric field on the side of the gate, and helping to improve the withstand voltage of the device.

S030: A source metal 180 and a drain metal 190 are formed on the source region and the drain region of the semiconductor layer 110, respectively.

As shown in FIG. 6 , continue to fabricate the source metal 180 and the drain metal 190 on the semiconductor layer 110. During fabrication, the two can usually be fabricated in the same step, for example: coating the surface of the semiconductor layer 110 with a photoresist layer, A first window and a second window are formed on the photoresist layer through processes such as exposure and development, wherein the first window is located in the source region, and the second window is located in the drain region. Then, a source metal 180 and a drain metal 190 are formed in the source region and the drain region respectively through processes such as metal evaporation and metal lift-off.

S040 : The gate metal 200 is formed on the body portion 141 .

A gate metal 200 is formed in the gate region of the semiconductor layer 110 , and the gate metal 200 is in Schottky contact with the first P-type lightly doped layer 140 . Similarly, the gate metal 200 can also be formed by a process such as photolithography, evaporation, and metal stripping.

As shown in FIG. 4 to FIG. 6 , the extension part 142 includes a continuous first modulation part 143 and a second modulation part 144 , the first modulation part 143 covers the side surface of the P-type heavily doped layer 120 , and the second modulation part 144 is located in the semiconductor The layer 110 is surface and extends towards the source region and/or the drain region.

As shown in FIG. 3 , after the P-type heavily doped layer 120 is formed on the semiconductor layer 110 , grooves 130 may be formed by etching on both sides of the P-type heavily doped layer 120 , and then the P-type heavily doped layer 120 may be formed by etching. The first P-type lightly doped layer 140 is formed on the semiconductor layer 120 , so that the second modulation part 144 extending on the semiconductor layer 110 can be at least partially filled in the groove 130 . Correspondingly, for example, as shown in FIG. 8 , the second modulation part 144 is completely filled in the groove 130 ; for example, as shown in FIG. 5 , the first sub-section 145 of the second modulation part 144 is filled in the groove 130 , and the second modulation part 144 The second sub-portion 146 of the portion 144 is located outside the groove 130 .

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (10)

1. The semiconductor device is characterized by comprising a substrate and a semiconductor layer arranged on the substrate, wherein the semiconductor layer comprises a source region, a drain region and a gate region, a stacked P-type heavy doping layer and a first P-type light doping layer are sequentially arranged in the gate region of the semiconductor layer, the first P-type light doping layer comprises a continuous body part and an extension part, the body part is positioned on the top surface of the P-type heavy doping layer, the extension part at least covers the side surface of the P-type heavy doping layer, a source metal and a drain metal are respectively arranged in the source region and the drain region of the semiconductor layer, and a gate metal is arranged on the body part.

2. The semiconductor device according to claim 1, wherein the extension portion comprises a continuous first modulation portion covering a side surface of the P-type heavily doped layer and a second modulation portion located on the surface of the semiconductor layer and extending toward the source region and/or the drain region.

3. The semiconductor device according to claim 2, wherein a groove corresponding to the second modulation part is formed in the surface of the semiconductor layer, the groove is located on a side of the P-type heavily doped layer close to the source region and/or the drain region, and the second modulation part is at least partially located in the groove.

4. The semiconductor device according to claim 3, wherein the second modulation portion comprises a first sub-portion and a second sub-portion which are continuously arranged in a direction away from the P-type heavily doped layer, the first sub-portion is located in the groove, and the second sub-portion is located outside the groove.

5. The semiconductor device according to any one of claims 1 to 4, wherein a second P-type lightly doped layer is further provided between the P-type heavily doped layer and the semiconductor layer.

6. The semiconductor device of claim 5, wherein the extension covers at least a side of the P-type heavily doped layer and a side of the second P-type lightly doped layer.

7. The semiconductor device of claim 1, wherein the first P-type lightly doped layer, the second P-type lightly doped layer, and the P-type heavily doped layer are all P-type gallium nitride layers.

8. A method of fabricating a semiconductor device, the method comprising:

forming a semiconductor layer on a substrate, the semiconductor layer including a source region, a drain region and a gate region;

sequentially forming a P-type heavily doped layer and a first P-type lightly doped layer which are stacked in a gate region of the semiconductor layer, wherein the first P-type lightly doped layer comprises a continuous body part and an extension part, the body part is positioned on the top surface of the P-type heavily doped layer, and the extension part at least covers the side surface of the P-type heavily doped layer;

forming a source metal and a drain metal in a source region and a drain region of the semiconductor layer, respectively;

a gate metal is formed on the body portion.

9. The method for manufacturing a semiconductor device according to claim 8, wherein the extension portion comprises a first modulation portion and a second modulation portion which are continuous, the first modulation portion covers a side surface of the P-type heavily doped layer, and the second modulation portion is located on the surface of the semiconductor layer and extends toward the source region and/or the drain region.

10. The method for manufacturing a semiconductor device according to claim 9, wherein the forming of the stacked P-type heavily doped layer and the first P-type lightly doped layer in sequence in the gate region of the semiconductor layer comprises:

forming a P-type heavily doped layer in a gate region of the semiconductor layer;

etching the semiconductor layer on one side of the P-type heavily doped layer close to the source region and/or the drain region to form a groove;

and a first P-type lightly doped layer is formed on the P-type heavily doped layer, wherein at least part of the second modulation part is correspondingly positioned in the groove.

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