CN114744024B - A kind of semiconductor device and preparation method thereof - Google Patents

Abstract

The present application provides a semiconductor device and a preparation method thereof, and relates to the technical field of semiconductors. The method includes removing the substrate between the drain metal and the backside metal, and filling the area where the substrate is removed with a first medium having a lower dielectric constant layer, thereby effectively reducing the source-drain parasitic capacitance Cds generated between the drain metal and the backside metal. At the same time, the present application effectively simplifies the process steps by integrating the process of forming the first dielectric layer with a lower dielectric constant and the original process of forming the source through hole, and when the semiconductor device is a GaN device, in view of the GaN device's Generally speaking, the thickness of the substrate is thicker. Therefore, when the first dielectric layer is disposed on the substrate, more materials with low dielectric constant can be filled between the drain metal and the back metal, which is conducive to better performance. It reduces the source-drain parasitic capacitance Cds generated between the drain metal and the backside metal.

Description

A kind of semiconductor device and preparation method thereof

technical field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device and a preparation method thereof.

Background technique

For RF devices, drain efficiency is a key measure, and the main factor affecting drain efficiency is the parasitic capacitance Cds between source and drain. The smaller the Cds, the higher the drain efficiency.

In GaN devices, in order to reduce the occupied area of the device, source through holes are usually used to lead out multiple source metals on the front side of the device to the back side metal on the back side of the device. The vertical direction of the device has overlapping regions, thereby increasing the Cds of the device, resulting in lower drain efficiency and affecting the performance of the device.

SUMMARY OF THE INVENTION

The purpose of the present application is to provide a semiconductor device and a preparation method thereof in view of the above-mentioned deficiencies in the prior art, so as to reduce the increase of Cds due to the introduction of back metal and improve the drain efficiency.

To achieve the above purpose, the technical solutions adopted in the embodiments of the present application are as follows:

In one aspect of the embodiments of the present application, a method for fabricating a semiconductor device is provided. The method includes: forming a semiconductor layer on a front surface of a substrate; forming a source metal, a drain metal and a gate metal in an active region of the semiconductor layer; A first through hole and a primary through hole are formed on the backside of the substrate respectively by etching, wherein the drain metal covers the first through hole in the orthographic projection of the substrate; the first through hole is filled with a first dielectric layer, The dielectric constant of the first dielectric layer is smaller than the dielectric constant of the substrate; the semiconductor layer is etched in the primary through hole to form a secondary through hole extending through the source metal, and the primary through hole is connected with the secondary through hole to form a source through hole A hole is formed on the backside of the substrate, which is interconnected with the source metal through the source through hole, and the backside metal covers the first dielectric layer.

Optionally, the first through hole portion extends to the semiconductor layer.

Optionally, there are a plurality of first through holes, and the plurality of first through holes are spaced and distributed in the orthographic projection of the drain metal on the substrate.

Optionally, filling the first through hole with the first dielectric layer includes: filling the first through hole with a first dielectric layer that is flush with the backside of the substrate.

Optionally, the first dielectric layer is a thermally conductive first dielectric layer.

Optionally, the material of the first dielectric layer is one of polyimide and polyphenylene ether.

Optionally, after the semiconductor layer is formed on the front surface of the substrate, the method further includes: respectively forming a drain pad connected to the drain metal and a gate pad connected to the gate metal in an inactive region of the semiconductor layer.

Optionally, after respectively forming a drain pad connected to the drain metal and a gate pad connected to the gate metal in the inactive region of the semiconductor layer, the method further includes: forming respectively on the backside of the substrate by etching The second through hole and the third through hole passing through the substrate, wherein the orthographic projection of the drain pad on the substrate covers the second through hole, and the orthographic projection of the gate pad on the substrate covers the third through hole; The second through hole and the third through hole are filled with a second dielectric layer, and the dielectric constant of the second dielectric layer is smaller than that of the substrate; the back metal also covers the second through hole and the third through hole in the third through hole respectively. Two dielectric layers.

In another aspect of the embodiments of the present application, a semiconductor device is provided, including a substrate and a semiconductor layer disposed on the front surface of the substrate, and a source metal, a drain metal and a gate metal are respectively disposed in an active region of the semiconductor layer; A first through hole is opened on the backside of the substrate, the drain metal covers the first through hole on the orthographic projection of the substrate, and the first through hole is filled with a first dielectric layer, and the dielectric constant of the first dielectric layer The dielectric constant is smaller than the dielectric constant of the substrate; source through holes that penetrate the substrate and the semiconductor layer in sequence are provided on the back of the substrate, and a back metal interconnected with the source metal through the source through holes is arranged on the back of the substrate, and the back metal covers the first dielectric layer.

Optionally, a drain pad and a gate pad are arranged in the passive area of the semiconductor layer, the drain pad is connected to the drain metal, and the gate pad is connected to the gate metal; a through lining is provided on the backside of the substrate. The second through hole and the third through hole at the bottom, the orthographic projection of the drain pad on the substrate covers the second through hole, and the orthographic projection of the gate pad on the substrate covers the third through hole; The third through holes are respectively filled with a second dielectric layer, and the dielectric constant of the second dielectric layer is smaller than the dielectric constant of the substrate; the back metal also covers the second dielectric layer in the second through hole and in the third through hole, respectively .

The beneficial effects of this application include:

The present application provides a semiconductor device and a method for fabricating the same. By removing the substrate between the drain metal and the backside metal, and filling a first dielectric layer with a lower dielectric constant in the region where the substrate is removed, the method can effectively Reduce the source-drain parasitic capacitance Cds generated between the drain metal and the backside metal. At the same time, the present application effectively simplifies the process steps by integrating the process of forming the first dielectric layer with a lower dielectric constant and the original process of forming the source through hole, and when the semiconductor device is a GaN device, in view of the GaN device's Generally speaking, the thickness of the substrate is thicker. Therefore, when the first dielectric layer is disposed on the substrate, more materials with low dielectric constant can be filled between the drain metal and the back metal, which is conducive to better performance. It reduces the source-drain parasitic capacitance Cds generated between the drain metal and the backside metal.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following drawings will briefly introduce the drawings that need to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a flowchart of a semiconductor device and a preparation method thereof provided by an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application;

3 is a cross-sectional view of A-A in FIG. 2 according to an embodiment of the present application;

Fig. 4 is another cross-sectional view of A-A in Fig. 2 provided by the embodiment of the application;

Fig. 5 is another cross-sectional view of A-A in Fig. 2 provided by the embodiment of the application;

6 is a cross-sectional view of B-B in FIG. 2 according to an embodiment of the present application;

Fig. 7 is another cross-sectional view of B-B in Fig. 2 provided by an embodiment of the present application;

FIG. 8 is a cross-sectional view of C-C in FIG. 2 according to an embodiment of the present application.

Icons: 100-substrate; 110-active area; 120-inactive area; 130-source metal; 140-drain metal; 150-gate metal; 160-gate pad; 170-drain pad ; 180-semiconductor layer; 181-buffer layer; 190-source field plate; 210-first passivation layer; 220-second passivation layer; 230-protective layer; 240-backside metal; 250-source via ; 260 - the first dielectric layer; 270 - the second dielectric layer.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is a part of the embodiments of the present application, but not all of the embodiments. The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending on" another element, it can be directly on or extending directly to the other element elements, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending directly onto" another element, there are no intervening elements present. Also, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "extending over" another element, it can be directly on or directly on the other element Extends over another element, or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or "extending directly on" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It is also to be understood that terms used herein should be construed to have the same meaning as they have in the context of this specification and related art, and not to be construed in an idealized or overly formal sense unless explicitly defined as such herein.

In one aspect of the embodiments of the present application, a method for fabricating a semiconductor device is provided, as shown in FIG. 1 , the method includes:

S010: A semiconductor layer is formed on the front surface of the substrate.

As shown in FIG. 3 , a substrate 100 is first provided, and the substrate 100 may be a substrate for carrying semiconductor integrated circuit components, such as GaN, GaAs, SiC, and the like. Then, a semiconductor layer 180 is deposited on the substrate 100. The deposition method can be performed by chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), which is not limited in this application. It can be selected reasonably according to actual needs.

The semiconductor layer 180 may be a stack composed of multiple active semiconductor layers 180 , and the specific setting may be reasonably selected according to the device type, for example, according to an insulated gate field effect transistor (MIS FET), a high electron mobility transistor (HEMT) etc., and this application does not limit it.

A two-dimensional electron gas is formed at the interface of at least two heterojunction layers in the multilayer active semiconductor layer 180, and the two-dimensional electron gas in a part of the region is removed by processes such as etching and ion implantation. source region 110 and inactive region 120 .

S020 : forming source metal, drain metal and gate metal in the active region of the semiconductor layer.

As shown in FIG. 3 , in the active region 110 of the semiconductor layer 180 , spaced source metal 130 and drain metal 140 may be formed on the surface of the semiconductor layer 180 on the side of the semiconductor layer 180 away from the substrate 100 by processes such as photolithography, evaporation, and lift-off. and the gate metal 150, wherein the gate metal 150 is located between the source metal 130 and the drain metal 140, and an active device with gate control function can be formed by means of the two-dimensional electron gas in the semiconductor layer 180. In addition, as shown in FIG. 2 , multiple active devices may be formed in the active region 110 on the same wafer, which is not limited in the present application.

S030 : respectively forming a first through hole and a primary through hole through the substrate on the backside of the substrate by etching, wherein the orthographic projection of the drain metal on the substrate covers the first through hole.

As shown in FIG. 3 , a first through hole and a primary through hole through the substrate 100 are simultaneously formed on the backside of the substrate 100 by etching, wherein the first through hole is located directly under the drain metal 140 and the primary through hole is located at the source directly below the pole metal 130 .

S040: A first dielectric layer is filled in the first through hole, and the dielectric constant of the first dielectric layer is smaller than the dielectric constant of the substrate.

As shown in FIG. 3 , the first dielectric layer 260 is filled in the first through hole, and based on the position of the first through hole, the first dielectric layer 260 is also located directly under the drain metal 140 . The dielectric constant of the first dielectric layer 260 is smaller than the dielectric constant of the substrate 100 , in other words, the first dielectric layer 260 is a low dielectric layer with a relatively low dielectric constant, such as the relative dielectric constant of the first dielectric layer 260 5 to 1. In this way, the source-drain parasitic capacitance Cds generated between the backside metal 240 and the drain metal 140 can be easily reduced.

S050: Etch the semiconductor layer in the primary through hole to form a secondary through hole extending through the source metal, and the primary through hole communicates with the secondary through hole to form a source through hole.

As shown in FIG. 3 , the semiconductor layer 180 is continuously etched in the primary through hole, so that a secondary through hole is formed on the semiconductor layer 180, and the secondary through hole is connected to the bottom of the source metal 130, thereby, The entirety of the primary via and the secondary via is communicated as the source via 250 .

S060 : forming a backside metal interconnected with the source metal through the source through hole on the backside of the substrate, and the backside metal covers the first dielectric layer.

As shown in FIG. 3 , the backside metal 240 covering the first dielectric layer 260 is formed on the backside of the substrate 100 by evaporation, and the backside metal 240 can be connected to the source metal 130 through the source through hole 250 to realize the connection between the source metal and the source metal. 130 leads.

To sum up, by removing the substrate 100 between the drain metal 140 and the backside metal 240, and filling the first dielectric layer 260 with a lower dielectric constant in the region where the substrate 100 is removed, the drain metal can be effectively reduced The source-drain parasitic capacitance Cds generated between 140 and the backside metal 240. At the same time, the present application effectively simplifies the process steps by integrating the process of forming the first dielectric layer 260 with a lower dielectric constant and the process of forming the source through hole 250, and when the semiconductor device is a GaN device, in view of the GaN device Due to the characteristics of the device, generally the thickness of the substrate 100 is relatively thick. Therefore, when the first dielectric layer 260 is disposed on the substrate 100 , more low-dielectric constant can be filled between the drain metal 140 and the back metal 240 . The material helps to better reduce the source-drain parasitic capacitance Cds generated between the drain metal 140 and the backside metal 240 .

For example, when the GaN device is a GaN HEMT device, the thickness of the substrate 100 is usually greater than the thickness of the barrier layer. Therefore, when the first dielectric layer 260 is disposed on the substrate 100, the drain metal 140 and the back surface can be better reduced The source-drain parasitic capacitance Cds generated between the metals 240 .

Referring to FIG. 3 , when the first through hole and the first dielectric layer 260 are located on the substrate 100 , the semiconductor layer 180 above the substrate 100 can be avoided, for example, electrical properties such as source-drain conduction can be avoided, and the semiconductor device can be guaranteed. of normal work.

Referring to FIG. 4 , in an embodiment, the first through hole may also extend into the semiconductor layer 180 , so that more low-k materials can be filled between the drain metal 140 and the backside metal 240 , which helps to better reduce the source-drain parasitic capacitance Cds generated between the drain metal 140 and the backside metal 240 . For example, as shown in FIG. 4 , the semiconductor layer 180 includes a buffer layer 181 , a channel layer and a barrier layer sequentially formed on the front surface of the substrate 100 . The channel layer and the barrier layer form a heterojunction with a two-dimensional electron gas. The first through hole provided on the bottom 100 can also extend to the buffer layer 181 , thereby, while obtaining a lower source-drain parasitic capacitance Cds, it can also effectively avoid the difference between the first through hole and the first dielectric layer 260 . The mass junction affects the normal operation of the semiconductor device.

Referring to FIG. 5 , there may also be a plurality of first through holes disposed directly under the drain metal 140 , and the plurality of first through holes are spread on the substrate 100 in a spaced manner. In this way, more low-dielectric constant materials can be filled between the drain metal 140 and the back metal 240, and at the same time, the monomer size of the first through hole can be prevented from being too large, thereby reducing the structural stability of the device caused by the opening. Impact.

Referring to FIG. 3 , when the first through hole is filled with the first dielectric layer 260 through S040 , the first dielectric layer 260 filled in the first through hole can be made flush with the backside of the substrate 100 , thereby obtaining A relatively flat surface is convenient for the subsequent evaporation of the backside metal 240 on the backside of the substrate 100 , which can reduce the impact on the backside metal 240 .

In one embodiment, the first dielectric layer 260 is a thermally conductive first dielectric layer 260 , that is, the first dielectric layer 260 has a relatively low dielectric constant and also has good thermal conductivity. While the source-drain parasitic capacitance Cds is relatively low, the thermal conductivity of the first dielectric layer 260 can also be used to effectively improve the heat dissipation performance of the device.

In order to make the first dielectric layer 260 have the characteristics of high thermal conductivity, low dielectric constant, and insulation, in one embodiment, the material of the first dielectric layer 260 is one of polyimide and polyphenylene ether.

In one embodiment, as shown in FIG. 2 to FIG. 5 , a first passivation layer 210 , a second passivation layer 220 and a protective layer 230 (not shown in FIG. 2 ) may also be sequentially formed on the semiconductor layer 180 . , wherein a gate window can be opened on the first passivation layer 210 to facilitate setting the gate metal 150 through the gate window; For the source window and the drain window of the three, the source metal 130 is easily arranged through the source window, and the drain metal 140 is arranged through the drain window. In order to improve the electric field modulation effect of the gate metal 150 on the surrounding gate, a source field plate 190 (not shown in FIG. 2 ) may also be arranged above the gate metal 150 , and the gate metal 150 and the source field plate 190 can pass through The first passivation layer 210 is insulated, and the source field plate 190 is located between the second passivation layer 220 and the protective layer 230 .

In one embodiment, after forming the semiconductor layer 180 on the front surface of the substrate 100 by S010, the method further includes:

S021 : a drain pad 170 connected to the drain metal 140 and a gate pad 160 connected to the gate metal 150 are respectively formed in the inactive region 120 of the semiconductor layer 180 .

As shown in FIG. 2 , a drain pad 170 and a gate pad 160 are formed in the inactive region 120 of the semiconductor layer 180 , wherein the drain pad 170 is connected to the drain metal 140 , and the gate pad 160 is connected to the gate The electrode metal 150 is connected, so that the drain metal 140 and the gate metal 150 can be led out to the passive area 120 through the drain pad 170 and the gate pad 160, which is convenient for wire bonding and testing.

S021 and S020 can be prepared in the same process step, which is not limited in this application.

S022 : respectively forming a second through hole and a third through hole through the substrate 100 on the back surface of the substrate 100 by etching, wherein the drain pad 170 covers the second through hole on the orthographic projection of the substrate 100 , and the gate solder The orthographic projection of the disk 160 on the substrate 100 covers the third through hole.

As shown in FIG. 6 , a second through hole penetrating through the substrate 100 may be correspondingly formed on the substrate 100 of the inactive region 120 by etching, and the second through hole is located directly under the drain pad 170 .

As shown in FIG. 8 , a third through hole penetrating the substrate 100 may be correspondingly formed on the substrate 100 of the inactive region 120 by etching, and the third through hole is located directly under the gate pad 160 .

S022 and S030 can be performed in the same process step, in other words, the first through hole, the primary through hole, the second through hole and the third through hole can be formed in different regions of the substrate 100 through the same etching step, thereby further simplified process.

S023 : the second through holes and the third through holes are filled with a second dielectric layer 270 , and the dielectric constant of the second dielectric layer 270 is smaller than the dielectric constant of the substrate 100 .

As shown in FIG. 6 , the second dielectric layer 270 may be filled in the second through hole, and based on the position of the second through hole, the second dielectric layer 270 located therein is also located directly under the drain pad 170 . As shown in FIG. 8 , the second dielectric layer 270 may be filled in the third through hole, and based on the position of the third through hole, the second dielectric layer 270 located therein is also located directly under the gate pad 160 .

S023 and S040 may be performed in the same process step, that is, the first dielectric layer 260 and the second dielectric layer 270 may be the same dielectric layer, thereby effectively simplifying the process steps.

S023 should be performed before S060, so that when the backside metal 240 is evaporated on the backside of the substrate 100, the backside metal 240 covers the first dielectric layer 260 and also covers the second through hole and the third through hole. the second dielectric layer 270. And since the dielectric constant of the second dielectric layer 270 is smaller than the dielectric constant of the substrate 100 , the source-drain parasitic capacitance Cds generated between the drain pad 170 and the back metal 240 and the gate pad 160 and the gate pad 160 can be effectively reduced. The gate-source parasitic capacitance Cgs generated between the backside metals 240 .

Referring to FIG. 7 , there may also be a plurality of second through holes disposed directly under the drain pad 170 , and the plurality of second through holes are tiled on the substrate 100 in a spaced manner. Therefore, more low-dielectric constant materials can be filled between the drain pad 170 and the backside metal 240, and at the same time, the monomer size of the second through hole can be prevented from being too large, thereby reducing the structural stability of the device due to the opening. effects of sex. Similarly, the third through hole can also be set with reference to the second through hole, and also has corresponding effects, which will not be repeated here.

Another aspect of the embodiments of the present application provides a semiconductor device, which can be prepared by the above method, which is not limited in the present application. As shown in FIG. 3 , the semiconductor device includes a substrate 100 and a semiconductor layer 180 disposed on the front surface of the substrate 100 . A source metal 130 , a drain metal 140 and a gate metal 150 are respectively disposed in the active region 110 of the semiconductor layer 180 . A first through hole penetrating the substrate 100 is opened on the back side of the substrate 100, the drain metal 140 covers the first through hole in the orthographic projection of the substrate 100, and the first through hole is filled with a first dielectric layer 260, the first The dielectric constant of the dielectric layer 260 is smaller than the dielectric constant of the substrate 100 ; source through holes 250 penetrating the substrate 100 and the semiconductor layer 180 in sequence are provided on the back of the substrate 100 , and source through holes 250 are provided on the back of the substrate 100 The backside metal 240 interconnected with the source metal 130 covers the first dielectric layer 260 .

To sum up, by removing the substrate 100 between the drain metal 140 and the backside metal 240, and filling the first dielectric layer 260 with a lower dielectric constant in the region where the substrate 100 is removed, the drain metal can be effectively reduced The source-drain parasitic capacitance Cds generated between 140 and the backside metal 240. And when the semiconductor device is a GaN device, in view of the characteristics of the GaN device, the thickness of the substrate 100 is usually thick. Therefore, when the first dielectric layer 260 is disposed on the substrate 100, the drain metal 140 and the backside metal 240 Filling more materials with low dielectric constant between them helps to better reduce the source-drain parasitic capacitance Cds generated between the drain metal 140 and the backside metal 240 .

As shown in FIGS. 6 to 8 , a drain pad 170 and a gate pad 160 are provided in the inactive region 120 of the semiconductor layer 180 , the drain pad 170 is connected to the drain metal 140 , and the gate pad 160 is connected to The gate metal 150 is connected; a second through hole and a third through hole are opened on the back side of the substrate 100 penetrating the substrate 100 , the drain pad 170 covers the second through hole on the orthographic projection of the substrate 100 , and the gate pad 160 The orthographic projection of the substrate 100 covers the third through hole; the second through hole and the third through hole are filled with a second dielectric layer 270 respectively, and the dielectric constant of the second dielectric layer 270 is smaller than that of the substrate 100 ; The back metal 240 also covers the second dielectric layer 270 in the second through hole and in the third through hole, respectively. Therefore, the source-drain parasitic capacitance Cds generated between the drain pad 170 and the backside metal 240 and the gate-source parasitic capacitance Cgs generated between the gate pad 160 and the backside metal 240 can be effectively reduced.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (10)

1. A method of fabricating a semiconductor device, the method comprising:

forming a semiconductor layer on the front side of the substrate;

forming a source metal, a drain metal and a gate metal in an active region of the semiconductor layer;

respectively forming a first through hole and a primary through hole which penetrate through the substrate on the back surface of the substrate through etching, wherein the first through hole is covered by the orthographic projection of the drain metal on the substrate;

filling a first dielectric layer in the first through hole, wherein the dielectric constant of the first dielectric layer is smaller than that of the substrate;

etching the semiconductor layer in the primary through hole to form a secondary through hole penetrating to the source metal, wherein the primary through hole is communicated with the secondary through hole to form a source through hole;

and forming back metal interconnected with the source metal through the source through hole on the back of the substrate, wherein the back metal covers the first dielectric layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first via hole partially extends in the semiconductor layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the first through holes are a plurality of through holes, and the plurality of first through holes are distributed at intervals in an orthographic projection of the drain metal on the substrate.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the filling of the first via hole with the first dielectric layer comprises:

and filling a first dielectric layer which is flush with the back surface of the substrate in the first through hole.

5. The method for manufacturing a semiconductor device according to claim 1, wherein the first dielectric layer is a heat conductive dielectric layer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the first dielectric layer is one of polyimide and polyphenylene oxide.

7. The method for manufacturing a semiconductor device according to claim 1, wherein after the forming of the semiconductor layer on the front surface of the substrate, the method further comprises:

and a drain bonding pad connected with the drain metal and a gate bonding pad connected with the gate metal are respectively formed in the passive region of the semiconductor layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein after a drain pad connected to the drain metal and a gate pad connected to the gate metal are formed in the inactive region of the semiconductor layer, respectively, the method further comprises:

forming a second through hole and a third through hole which penetrate through the substrate on the back surface of the substrate through etching, wherein the second through hole is covered by the orthographic projection of the drain electrode bonding pad on the substrate, and the third through hole is covered by the orthographic projection of the grid electrode bonding pad on the substrate;

filling a second dielectric layer in the second through hole and the third through hole, wherein the dielectric constant of the second dielectric layer is smaller than that of the substrate;

the back metal also covers the second medium layers in the second through hole and the third through hole respectively.

9. The semiconductor device is characterized by comprising a substrate and a semiconductor layer arranged on the front surface of the substrate, wherein a source electrode metal, a drain electrode metal and a grid electrode metal are respectively arranged on an active region of the semiconductor layer;

a first through hole penetrating through the substrate is formed in the back surface of the substrate, the orthographic projection of the drain metal on the substrate covers the first through hole, a first dielectric layer is filled in the first through hole, and the dielectric constant of the first dielectric layer is smaller than that of the substrate;

and a source electrode through hole which sequentially penetrates through the substrate and the semiconductor layer is formed in the back surface of the substrate, back surface metal which is interconnected with the source electrode metal through the source electrode through hole is arranged on the back surface of the substrate, and the first dielectric layer is covered by the back surface metal.

10. The semiconductor device according to claim 9, wherein a drain pad and a gate pad are provided in a passive region of the semiconductor layer, the drain pad being connected to the drain metal, and the gate pad being connected to the gate metal;

forming a second through hole and a third through hole which penetrate through the substrate on the back of the substrate, wherein the second through hole is covered by the orthographic projection of the drain electrode bonding pad on the substrate, and the third through hole is covered by the orthographic projection of the grid electrode bonding pad on the substrate;

second dielectric layers are respectively filled in the second through holes and the third through holes, and the dielectric constant of the second dielectric layers is smaller than that of the substrate;

the back metal also covers the second medium layers in the second through hole and the third through hole respectively.

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