CN114721622B - Adder based on memristor, driving method and electronic equipment - Google Patents

Abstract

The application provides an adder based on a memristor, a driving method and electronic equipment, wherein the adder based on the memristor comprises the following components: the array comprises a 1T1R array and N peripheral circuits, wherein the 1T1R array comprises a first 1T1R sub-array, a second 1T1R sub-array, a third 1T1R sub-array, a fourth 1T1R sub-array and a fifth 1T1R sub-array which are sequentially arranged, the first 1T1R sub-array, the second 1T1R sub-array, the third 1T1R sub-array and the fourth 1T1R sub-array respectively comprise N1T 1R units, the fifth 1T1R sub-array comprises N+1 1T1R units, and each 1T1R unit comprises a memristor and a MOS tube. The memristor-based adder provided by the application can realize nonvolatile calculation results, carry operation is realized through CCAU, the calculation time delay is reduced, and in addition, the main body area of the adder is smaller and easy to integrate.

Description

Adder based on memristor, driving method and electronic device

Technical Field

The present invention relates to the field of electronic technology, and in particular to an adder based on a memristor, a driving method and an electronic device.

Background technique

Existing computer systems are mainly designed using the von Neumann structure. The von Neumann structure has the characteristics of separation of storage and computing, which leads to bottlenecks such as "storage wall" and "power consumption wall", which seriously restricts the development of computing system performance. Memristor is a basic circuit element that describes the relationship between charge and flux. Its resistance state changes with the change of external stimulus (voltage or current), and the resistance state remains unchanged when the stimulus is removed. The memristor logic proposed based on the characteristics of memristors can realize the integration of storage and computing. The new computing system designed using memristor logic is expected to break through the bottleneck of the von Neumann structure.

Adders are basic circuits in digital systems and are the basis for building complex logic units such as multipliers. Building adders with advantages in terms of latency, area, and non-volatility of calculation results is of great significance for designing high-performance computing systems. For example, methods for designing N-bit adders using IMPs have been studied, but the operation of N-bit adders is still relatively complex. Adders based on threshold gates and MeMOS cannot achieve storage and computing integration, and their structures are more difficult to integrate than IMP-based adders. Lauren Guckert et al. proposed MAD and proposed an adder based on MAD, which has a small latency but a complex structure. There is no adder that can achieve storage and computing integration while being easy to integrate, having low latency, and having a small integration area.

Summary of the invention

In order to solve the above problems, the embodiments of the present disclosure provide an adder based on a memristor, a driving method and an electronic device.

In a first aspect, an embodiment of the present application provides an adder based on a memristor, comprising:

A 1T1R array and N peripheral circuits, wherein the 1T1R array comprises a first 1T1R subarray, a second 1T1R subarray, a third 1T1R subarray, a fourth 1T1R subarray and a fifth 1T1R subarray which are arranged in sequence, wherein the first 1T1R subarray, the second 1T1R subarray, the third 1T1R subarray and the fourth 1T1R subarray respectively comprise N 1T1R units, the fifth 1T1R subarray comprises N+1 1T1R units, each 1T1R unit comprises a memristor and a MOS tube, and the bottom electrode of the memristor is connected to the source or drain of the MOS tube;

The drain or source of the MOS transistor in each 1T1R unit of each 1T1R sub-array is connected to the word line of the corresponding column, and the gate of the MOS transistor in each 1T1R unit of each 1T1R sub-array is connected to the gate control line of the corresponding column;

The top electrodes of the memristors in the i-th 1T1R unit of the first 1T1R subarray and the i-th 1T1R unit of the second 1T1R subarray are connected to the i-th first bit line, the top electrodes of the memristors in the i-th 1T1R unit of the third 1T1R subarray, the i-th 1T1R unit of the fourth 1T1R subarray and the i-th 1T1R unit of the fifth 1T1R subarray are connected to the i-th second bit line, the top electrode of the memristor in the N+1-th 1T1R unit of the fifth 1T1R subarray is connected to the third bit line, the second end of the i-th first bit line is connected to the first end of the i-th second bit line through the switch module, 1≤i≤N;

The second end of the i-th peripheral circuit is connected to the first end of the i-th first bit line, the first end of the i-th peripheral circuit is connected to the second end of the i+1-th second bit line, 1≤i≤N-1, and the first end of the N-th peripheral circuit is connected to the first end or the second end of the third bit line.

In a second aspect, an embodiment of the present application provides a method for driving an adder, comprising:

Determine the logical value of the memristor in the i+1th 1T1R cell of the third 1T1R subarray according to the logical value of the memristor in the i-th 1T1R cell of the first 1T1R subarray, the logical value of the memristor in the i-th 1T1R cell of the second 1T1R subarray, and the logical value of the memristor in the i-th 1T1R cell of the third 1T1R subarray, 1≤i≤N-1; and determine the logical value of the memristor in the N+1th 1T1R cell of the fifth 1T1R subarray according to the logical value of the memristor in the N-th 1T1R cell of the first 1T1R subarray, the logical value of the memristor in the N-th 1T1R cell of the second 1T1R subarray, and the logical value of the memristor in the N-th 1T1R cell of the third 1T1R subarray;

Determine the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray according to the logic value of the memristor in the i-th 1T1R unit of the first 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the second 1T1R subarray, 1≤i≤N;

Determine the logic value of the memristor in the i-th 1T1R unit of the fifth 1T1R subarray according to the logic value of the memristor in the i-th 1T1R unit of the third 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray, 1≤i≤N;

The final result is determined according to the logic value of the memristor in the N+1 1T1R units of the fifth 1T1R subarray, wherein the logic value of the memristor is determined by the resistance state of the memristor, the high resistance state of the memristor represents the logic value 0, and the low resistance state of the memristor represents the logic value 1.

In a third aspect, an embodiment of the present application provides an electronic device storing a computer program, which, when running on a processor, executes the driving method of the adder provided in the second aspect.

The memristor-based adder provided in the embodiment of the present application retains the main structure of the 1T1R array, is easy to integrate, and has a small area. At the same time, the calculation results are directly stored in the memristor and are non-volatile. Through the combination of the memristor and the peripheral circuit, the alignment work is omitted while the carry operation is realized, thereby reducing the calculation delay.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solution of the present invention, the following will briefly introduce the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and should not be regarded as limiting the scope of protection of the present invention. In each of the drawings, similar components are numbered similarly.

FIG1 shows a schematic diagram of a structure of a memristor-based adder provided in an embodiment of the present invention;

FIG2A shows a schematic structural diagram of a 1T1R unit provided in an embodiment of the present invention;

FIG2B shows another schematic structural diagram of a 1T1R unit provided in an embodiment of the present invention;

FIG3 shows a schematic structural diagram of a CCAU provided by an embodiment of the present invention;

FIG4 is a schematic diagram showing a process of generating a pulse _Di by a delay line provided in an embodiment of the present invention;

FIG5 is a schematic diagram showing a process of attenuating a pulse _Di to generate a pulse _Pi provided by an embodiment of the present invention;

FIG6 is a diagram showing switching voltages corresponding to the high resistance state and the low resistance state of the memristor provided in an embodiment of the present invention;

FIG7A shows a schematic diagram of a MAGIC OR gate provided by an embodiment of the present invention;

FIG7B shows a schematic diagram of a MAGIC NAND gate provided by an embodiment of the present invention;

FIG7C shows another schematic diagram of a MAGIC OR gate provided by an embodiment of the present invention;

FIG7D shows another schematic diagram of a MAGIC NAND gate provided by an embodiment of the present invention;

FIG8A shows a schematic structural diagram of a 1T1R array provided in an embodiment of the present invention;

FIG8B shows another schematic diagram of the structure of a 1T1R array provided in an embodiment of the present invention;

FIG9 is a schematic flow chart showing a method for driving an adder provided by an embodiment of the present invention;

FIG10A is a schematic diagram showing the first application of a driving voltage in the process of implementing an XOR operation provided by an embodiment of the present invention;

FIG. 10B is a schematic diagram showing a second application of a driving voltage in the process of implementing an XOR operation provided by an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

The components of the embodiments of the present invention generally described and shown in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present invention, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present invention belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present invention.

Example 1

Referring to Figure 1, Figure 1 is a schematic diagram of the structure of a memristor-based adder provided in this embodiment. As shown in Figure 1, the memristor-based adder includes:

A 1T1R array and N peripheral circuits, wherein the 1T1R array comprises a first 1T1R subarray, a second 1T1R subarray, a third 1T1R subarray, a fourth 1T1R subarray and a fifth 1T1R subarray which are arranged in sequence, wherein the first 1T1R subarray, the second 1T1R subarray, the third 1T1R subarray and the fourth 1T1R subarray respectively comprise N 1T1R units, the fifth 1T1R subarray comprises N+1 1T1R units, each 1T1R unit comprises a memristor and a MOS tube, and the bottom electrode of the memristor is connected to the source or drain of the MOS tube;

The drain or source of the MOS transistor in each 1T1R unit of each 1T1R sub-array is connected to the word line of the corresponding column, and the gate of the MOS transistor in each 1T1R unit of each 1T1R sub-array is connected to the gate control line of the corresponding column;

The top electrodes of the memristors in the i-th 1T1R unit of the first 1T1R subarray and the i-th 1T1R unit of the second 1T1R subarray are connected to the i-th first bit line, the top electrodes of the memristors in the i-th 1T1R unit of the third 1T1R subarray, the i-th 1T1R unit of the fourth 1T1R subarray and the i-th 1T1R unit of the fifth 1T1R subarray are connected to the i-th second bit line, the top electrode of the memristor in the N+1-th 1T1R unit of the fifth 1T1R subarray is connected to the third bit line, the second end of the i-th first bit line is connected to the first end of the i-th second bit line through the switch module, 1≤i≤N;

The second end of the i-th peripheral circuit is connected to the first end of the i-th first bit line, the first end of the i-th peripheral circuit is connected to the second end of the i+1-th second bit line, 1≤i≤N-1, and the first end of the N-th peripheral circuit is connected to the first end or the second end of the third bit line.

Specifically, referring to FIG. 1 , the main body of the memristor is a 1T1R array structure, including five 1T1R sub-arrays, wherein A ₁ , A ₂ .. . _AN represent numbers of the 1st to Nth 1T1R units of the first 1T1R sub-array, B ₁ , B ₂ .. . _AN represent numbers of the 1st to Nth 1T1R units of the second 1T1R sub-array, C ₁ , C ₂ .. . _CN represent numbers of the 1st to Nth 1T1R units of the third 1T1R sub-array, L ₁ , L ₂ .. . _{. NL} represent numbers of the 1st to Nth 1T1R units of the fourth 1T1R sub-array, and S ₁ , S ₂ .. . _SN and CN ₊₁ represent numbers of the 1st to N+1st 1T1R units of the fifth 1T1R sub-array.

Please refer to FIG2A, which shows a schematic diagram of the structure of the 1T1R unit provided by the present embodiment, wherein the 1T1R unit includes a memristor M and a MOS transistor as a switch, the MOS transistor is used to control the gating of the memristor connected in series therewith, and the top electrode of the memristor M is connected to the corresponding bit line WL _i . Please refer to FIG1, in the 1T1R array structure, the bit line WL ₁ is separated into a first bit line WL _1-1 and a second bit line WL _1-2 by a switch module 1, the bit line WL ₂ is separated into a first bit line WL _2-1 and a second bit line WL _2-2 by a switch module 2, ... the bit line WL _N is separated into a first bit line WL _N-1 and a second bit line WL _N-2 by a switch module N, and the bit line WL _N+1 is the third bit line WL _N+1 .

In summary, the bit line WL _i in the 1T1R array is separated into a first bit line WL _i- 1 and a second bit line WL _{i- 2} by a switch module i. The switch module i for connecting the first bit line WL _{i- 1} and the second bit line WL _{i- 2} may be a MOS tube, that is, the first bit line WL _{i- 1} and the second bit line WL _{i- 2} may be controlled by the MOS tube for gating. Since the MOS tube has no substrate, the second end of the first bit line WL _{i- 1} may be connected to the source or drain of the MOS tube, and correspondingly, the first end of the second bit line WL _{i- 2} may be connected to the drain or source of the MOS tube. Please refer to Figure 1 again. In the 1T1R array structure, the top electrodes of the memristors in the 1T1R cells A _i and 1T1R cells B _i are connected to the first bit line WL _i-1 , the top electrodes of the memristors in the 1T1R cells C _i , 1T1R cells L _i and 1T1R cells S _i are connected to the second bit line WL _i-2 , 1≤i≤N, and the top electrode of the 1T1R cell C _N+1 is connected to the third bit line WL _N+1 .

Please refer to FIG. 2A again. The bottom electrode of the memristor M is connected to the source of the MOS transistor. The gate of the MOS transistor is connected to the gate control line G _m , 1≤m≤5. The drain of the MOS transistor is connected to the word line BL _k , 1≤k≤5. Please refer to FIG. 1. In the 1T1R array structure, the gate and drain of the MOS transistor in each 1T1R unit of the first 1T1R sub-array are respectively connected to the gate control line G ₁ and the word line BL ₁ , the gate and drain of the MOS transistor in each 1T1R unit of the second 1T1R sub-array are respectively connected to the gate control line G ₂ and the word line BL ₂ , the gate and drain of the MOS transistor in each 1T1R unit of the third 1T1R sub-array are respectively connected to the gate control line G ₃ and the word line BL ₃ , and the gate and drain of the MOS transistor in each 1T1R unit of the fourth 1T1R sub-array are respectively connected to the gate control line G ₄ and the word line BL ₄ , the gate and drain of the MOS tube in each 1T1R unit of the fifth 1T1R sub-array are connected to the gate control line _G5 and the word line _BL5 respectively. Please refer to FIG2B. Since the MOS tube is not provided with a substrate, the structure of the 1T1R unit can also be as shown in FIG2B, wherein the top electrode of the memristor M is connected to the drain of the MOS tube, and correspondingly, the source of the MOS tube is connected to the bit line WL _i of the corresponding row, the bottom electrode of the memristor M is connected to the word line BL _k of the corresponding column, and the gate of the MOS tube is connected to the gate control line G _m of the corresponding column. The 1T1R unit used in this embodiment is the 1T1R unit structure shown in FIG2A. The 1T1R unit structure shown in FIG2B can achieve the same function. Which 1T1R unit structure to use can be selected according to actual needs and is not limited here.

Please refer to Figure 1. In the 1T1R array structure shown in Figure 1, the 1T1R unit _Ai , 1T1R unit _Bi , 1T1R unit _Ci , the i-th MOS tube used as a switch, the first bit line WL _i-1 and the peripheral circuit connected to the first end of the first bit line WL _i-1 included in each dotted box together constitute CCAU _i , 1≤i≤N, CCAU is the carry calculation and alignment unit (CCAU).

Please refer to FIG3 , which is a schematic diagram of the structure of the CCAU provided in the present embodiment. The difference between FIG3 and the CCAU in FIG1 is that each MOS transistor used as a switch is omitted in FIG3 , because when the CCAU is formed, each MOS transistor used as a switch is in an on state, and the MOS transistor in the on state specifically includes a MOS transistor used to connect the first bit line WL _i-1 and the second bit line WL _i-2 , and each MOS transistor in the 1T1R unit A _i , 1T1R unit B _i and 1T1R unit C _i , 1≤i≤N, therefore, for the convenience of description, the above-mentioned each MOS transistor is omitted in FIG3 , and in addition, compared with FIG1 , the specific composition of the peripheral circuit is also expanded in FIG3 .

In this embodiment, the first end of the i-th peripheral circuit is connected to the second end of the second bit line WL _(i+1)-2 , and is used to output a high level or a low level to the second bit line WL _(i+1)-2 . The first end of the N-th peripheral circuit is connected to the first end or the second end of the third bit line WL _N+1 , and is used to output a high level or a low level to the third bit line WL _N+1 , 1≤i≤N. In addition, in the CCAU, the first end of the peripheral circuit is the output end of the CCAU, so it can be seen that the output end of the i-th CCAU is used to output a high level or a low level to the second bit line WL _(i+1)-2 , and the output end of the N-th CCAU is used to output a high level or a low level to the third bit line WL _N+1 .

Optionally, the peripheral circuit provided in this embodiment is composed of:

In a specific embodiment, each peripheral circuit includes an inverter and a voltage divider resistor, the voltage divider resistor is connected to the input end of the inverter, the output end of the inverter is the first end of the peripheral circuit, the input end of the inverter is the second end of each peripheral circuit, the resistance state of the memristor includes a high resistance state and a low resistance state, and the resistance value of the voltage divider resistor is equal to the resistance value corresponding to the memristor in the low resistance state.

Specifically, the peripheral circuit includes an inverter and a voltage-dividing resistor, as shown in FIG3 , the voltage-dividing resistor is a fixed resistor R, the resistance of the fixed resistor R is equal to the resistance corresponding to the memristor in the low resistance state, it should be noted that the memristors used in this embodiment are the same, and each memristor includes a high resistance state and a low resistance state. One end of the fixed resistor R is connected in series with the input end of the inverter, the voltage V ₀ is the voltage input to the inverter through the fixed resistor R, the input voltage _UR is the actual input voltage of the voltage V ₀ to the inverter after voltage division, and the voltage division is completed by the fixed resistor R and each memristor in the 1T1R unit A _i , 1T1R unit B _i and 1T1R unit C _i .

The input end of the inverter is the second end of the peripheral circuit, and the output end of the inverter is the first end of the peripheral circuit. Because the first end of the peripheral circuit is the output end of the CCAU, the output end of the inverter is the output end of the CCAU. The voltage V ₀ is input to the inverter through the fixed resistor R to input the voltage _UR to the inverter. The inverter determines whether the output of the output end is a high level or a low level according to the size of the input voltage _UR , so that the output end of the CCAU outputs a high level or a low level to the bit line corresponding to the output end.

Optionally, the inverter provided in this embodiment is composed of:

The inverter includes a PMOS tube and an NMOS tube, the gate of the PMOS tube is connected to the gate of the NMOS tube and serves as the input end of the inverter, the drain of the PMOS tube is connected to the drain of the NMOS tube and serves as the output end of the inverter, the source of the PMOS tube is connected to the power supply end, and the source of the NMOS tube is grounded.

Specifically, the inverter includes a PMOS tube and an NMOS tube. The gates of the PMOS tube and the NMOS tube are connected together as the input end of the inverter. The drains of the PMOS tube and the NMOS tube are connected together as the output end of the inverter. As shown in FIG. 3 , the source and substrate of the PMOS tube are connected to the power supply end. The power supply end inputs a high level of 3.3V to the source of the PMOS tube. The source and substrate of the NMOS tube are grounded.

It should be noted that the high level of the inverter, i.e., the high level inputted by the power supply end to the source of the PMOS tube, adopts a pulse with an amplitude of 3.3V. Please refer to FIG4. The pulses _D1 , _D2 , _D3 ... _DN shown in FIG4 represent pulses with an amplitude of 3.3V adopted by the high level of the inverter. The pulses _D1 , _D2 , _D3 ... _DN are generated by a delay line. The pulses _D1 , _D2 , _D3 ... _DN can be represented by pulses _Di in the text, 1≤i≤N. Delay _Ts represents that the delay between two adjacent control signals is _Ts .

The voltage _V0 input to the inverter through the fixed resistor R can be defined as the driving voltage of CCAU. The driving voltage of CCAU adopts a pulse _Pi with an amplitude of _V0 . _P1 , _P2 ... _PN as shown in Figure 1 are the numbers of the pulses _Pi adopted by the driving voltages of each CCAU. Pulse _Pi is generated by attenuation of pulse _Di. Please refer to Figure 5, which is a schematic diagram of generating pulse Pi by attenuating pulse _Di through the voltage divider of resistors _R1 and _R2 , 1≤i≤N, and T _pulse represents the high level time of pulse _Di.

In specific implementation, the driving voltage V ₀ of CCAU needs to be adjusted by the pulse P _i obtained by attenuating the pulse D _i , so that V ₀ and the on-voltage V _{GS-th (N)} of the NMOS tube in the inverter satisfy: As a prerequisite for CCAU to perform its function. In addition, before CCAU works, the resistance state of each carry memristor needs to be initialized to a high resistance state. In this embodiment, the carry memristor includes the memristor in the 1T1R unit _Ci , 2≤i≤N+1, that is, the carry memristor includes the memristor in the 2nd to Nth 1T1R units of the third 1T1R subarray, and the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray.

Please refer to FIG. 6. In this embodiment, FIG. 6 shows a switching voltage diagram corresponding to the high resistance state and the low resistance state of the memristor, wherein V _read is a small voltage that keeps the state of the memristor unchanged. The read operation is defined as applying a voltage V _read to the memristor and obtaining a current passing through it. A large current corresponds to a low resistance state (LRS), and a small current corresponds to a high resistance state (HRS). The low resistance state of the memristor can represent a logical value of 1, and the high resistance state of the memristor can represent a logical value of 0. V _set is a threshold voltage for switching the memristor from a high resistance state to a low resistance state, and V _reset is a threshold voltage for switching the memristor from a low resistance state to a high resistance state. The set operation is defined as the memristor switching from a high resistance state to a low resistance state. Therefore, the above initialization of the resistance state of each carry memristor to a high resistance state before the CCAU works is to initialize the logic value of each carry memristor to 0. Applying a positive voltage with an amplitude exceeding V _set can perform a set operation on the memristor, and applying a negative voltage with an amplitude exceeding V _reset can perform a reset operation on the memristor.

In this embodiment, each CCAU works sequentially and individually. Sequentially means that the 1st to Nth CCAUs work in order from 1 to N, and individually means that when a certain CCAU works, the other CCAUs do not work. For example, when the 1st CCAU works, the 2nd to Nth CCAUs do not work.

In specific implementation, before the 1st to Nth CCAUs work, it is necessary to select the gate control line _G1 , the gate control line _G2 and the gate control line _G3 to turn on the MOS tubes in the 1T1R units included in the CCAU, so that the bottom electrode of the memristor in each 1T1R unit in the CCAU is grounded. In addition, before the Nth CCAU works, it is also necessary to select the gate control line _G5 to ground the bottom electrode of the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray. For the specific contents of each 1T1R unit in the CCAU, please refer to the relevant description of the CCAU composition above, and will not be repeated here to avoid repetition.

Specifically, before the i-th CCAU works, it is also necessary to select the MOS tube between the first bit line WL _i-1 and the second bit line WL _i-2 to connect the first bit line WL _i-1 with the second bit line WL _i-2 , thereby connecting the top electrodes of the memristors in each 1T1R unit in the i-th CCAU to achieve the selection of the memristors in each 1T1R unit in the i-th CCAU, 1≤i≤N-1.

In this embodiment, the specific working process of CCAU includes: applying a pulse _Di to the inverter, and inputting a pulse _Pi obtained by attenuating the pulse _Di into a fixed resistor R, so as to apply a driving voltage _V0 to CCAU through the fixed resistor R. In addition, according to process control, when the inverter is working, only one of the PMOS tube and the NMOS tube can be turned on at the same time, that is, when the PMOS tube is turned on, the NMOS tube is not turned on, and when the NMOS tube is turned on, the PMOS tube is not turned on.

When the number of low-resistance memristors in each 1T1R unit in CCAU does not exceed 1, the input voltage of the inverter The NMOS tube is turned on, and the output voltage of the inverter is 0. That is, the voltage output by the output end of CCAU to the corresponding bit line is 0. In fact, the voltage output to the carry memristor whose top electrode is connected to the corresponding bit line is 0. The corresponding bit line here refers to the bit line correspondingly connected to the output end of CCAU. The following description is consistent with this. Because 0<V _set , the resistance state of the carry memristor whose top electrode is connected to the corresponding bit line remains unchanged, that is, the logic value of the carry memristor remains unchanged.

When the number of low-resistance memristors in CCAU exceeds 1, the input voltage of the inverter The P tube is turned on, and the output voltage of the inverter is a high level of 3.3V, that is, the output end of CCAU outputs a high level of 3.3V to the corresponding bit line, and actually outputs a high level of 3.3V to the carry memristor whose top electrode is connected to the corresponding bit line. 3.3V>V _set , so the resistance state of the carry memristor whose top electrode is connected to the corresponding bit line is switched from a high resistance state to a low resistance state, that is, the logic value of the carry memristor changes from 0 to 1, which is equivalent to completing the carry calculation.

It should be noted that when the i-th CCAU is working, only the MOS tube between the first bit line WL _i-1 and the second bit line WL _i-2 in the i-th row is selected, and other MOS tubes are not selected. This is to prevent the output end of the i-th CCAU from outputting a high level of 3.3V to the corresponding connected bit line. In addition to the carry memristor with the top electrode connected to the corresponding bit line, other memristors with the top electrode connected to the corresponding bit line also perform a set operation, thereby causing calculation errors, 1≤i≤N. In addition, in order to ensure that the resistance state of the memristor in each 1T1R unit in the CCAU is not changed, it is also necessary to satisfy V ₀ <V _set . Therefore, the constraints of the voltages involved in the entire CCAU are:

It is additionally noted that Table 1 is a table showing the voltage division of the CCAU when the number of low-resistance memristors included in the CCAU is different.

Table 1. Voltage division in CCAU under different input conditions

combination Number of memristors in low resistance state Input voltage _UR The output voltage operate 1 0 V ₀ 0 - 2 1 V ₀ /2 0 - 3 2 V ₀ /3 3.3V set 4 3 V ₀ /4 3.3V set

Table 1 shows the values of the input voltage _UR and output voltage of the corresponding inverter when the number of low-resistance memristors in each 1T1R unit in the CCAU is 0, 1, 2, and 3, respectively, and whether the carry memristor performs a set operation.

It should be noted that the time for CCAU to perform the i-th carry operation is (i-1)T _s to (i-1)T _s +T _pulse , and the carry operation is the above-mentioned set operation. T _s is the delay between two adjacent control signals, which must satisfy:

_Ts ＝ _Tpulse + _Tbuffer

T _pulse is the high level time of pulse _Di , which should be large enough to complete any step in the carry operation, which is determined by the memristor used. T _buffer is the buffer time. In the 1T1R array, the opening and closing of the switch and the transmission of the control signal all require time, so there is a buffer time between each operation. Therefore, the buffer time T _buffer should be greater than the sum of the delay time of the switch opening, the switch closing and the control signal. A switch can be set at the output end of the inverter to control the output action time of each CCAU. The design of pulse _Di and pulse _Pi achieves the same effect, but avoids increasing the area and power consumption of the switch. In addition, during the time of executing the i-th carry operation, there is a non-zero voltage only in the i-th CCAU that is working, and the power consumption of other CCAUs that are not working is 0, which greatly reduces the power consumption of the entire system, 1≤i≤N.

In this embodiment, the function of the memristor-based adder is to calculate Z=X+Y, where X and Y are two N-bit binary addends, and Z is the N+1-bit binary final result. The carry from the i-th bit to the i+1-th bit in the calculation process can be defined as _Qi+1 , 1≤i≤N. In order to reduce the calculation delay, the advantages of parallel computing should be fully utilized. In this embodiment, the process of calculating Z=X+Y includes two parts, which are as follows:

In the first part, the carry number _{Qi+1 to} the next digit _is calculated by the addend _Xi , the addend _Yi and the carry number Qi. In the second part, the final result number _Zi is calculated in parallel by the addend _Xi , the addend Yi and the carry number _Qi . The parallel calculation process of the second part includes two sub-steps. The first sub-step is to calculate the intermediate variable number _Oi in parallel by the addend _Xi and the addend _Yi , and the second sub-step is to calculate the final result number _Zi in parallel by the intermediate variable number _Oi and the carry number _Qi , 1≤i≤N.

Please refer to Figure 1. Based on the 1T1R array structure shown in Figure 1, when calculating Z=X+Y, the memristor in the 1T1R unit _Ai corresponds to storing the addend _Xi , the memristor in the 1T1R unit _Bi corresponds to storing the addend _Yi , the memristor in the 1T1R unit _Ci corresponds to storing the carry number _Qi , the memristor in the 1T1R unit _Li corresponds to storing the intermediate variable number _Oi , and the memristor in the 1T1R unit _Si corresponds to storing the final result number _Zi , 1≤i≤N, and the memristor in the 1T1R unit CN ₊₁ is used to store the carry number QN ₊₁ , and the N+1th bit of the carry number _Qi is the N+1th bit of the final result Z, wherein the logic value represented by the memristor corresponds to the number stored in the memristor.

The calculation process of the first part is implemented by CCAU, that is, the 1T1R unit A _i corresponding to the memristor storing the addend _Xi , the 1T1R unit B _i corresponding to the memristor storing the addend _Yi , and the 1T1R unit C _i corresponding to the memristor storing the carry number _Qi are connected to the first end of the first bit line WL _i-1 to form CCAU, so as to implement the carry calculation, 1≤i≤N. Before implementing the carry calculation by CCAU, each carry memristor needs to be initialized to a high impedance state, that is, the logic value of the carry memristor is initialized to 0. For details, please refer to the above description of the carry memristor. In addition, the memristors in the 1T1R unit A _i and the 1T1R unit B _i are used to store addends _Xi and _Yi , respectively. Therefore, the resistance states of the memristors in the 1T1R unit A _i and the 1T1R unit B _i need to be switched to resistance states corresponding to the addends stored therein. For example, if the addend stored in the memristor in the 1T1R unit A ₁ is 1, the resistance state of the memristor in the 1T1R unit A ₁ needs to be switched to a low resistance state. If the addend stored in the memristor in the 1T1R unit A ₁ is 0, the resistance state of the memristor in the 1T1R unit A ₁ needs to be switched to a high resistance state. After completing the above steps, carry calculation can be realized through CCAU. For the specific process, please refer to the above description of the CCAU working process. In order to avoid repetition, it will not be repeated here.

The calculation process of the second part is implemented by MAGIC logic gates, which are memristor-aided logic gates (MAGIC). In the first sub-step, the MAGIC logic gates are used to implement the _XOR operation (XOR) of addend _Xi and addend Yi to obtain the intermediate variable number _Oi , that is, _Oi = _Xi XOR _Yi . In the second sub-step, the MAGIC logic gates are used to implement the XOR operation (XOR) of the intermediate variable number _Oi and the carry number _Qi to obtain the final result number _Zi , that is, _Zi = _Oi XOR _Qi .

Specifically, the MAGIC logic gate is based on the MAGIC OR gate and the MAGIC NAND gate, and realizes the XOR operation through two steps of applying the driving voltage. At the same time, the MAGIC logic gate has two forms. The first form is that the top electrodes of the memristors in the 1T1R units constituting the MAGIC logic gate are connected together. Please refer to Figures 7A and 7B, which respectively show the MAGIC OR gate and the MAGIC NAND gate in which the top electrodes of the memristors are connected together, wherein IN ₁ and IN ₂ represent the 1T1R units used as inputs in the XOR operation, OUT represents the 1T1R units used as outputs in the XOR operation, and the MOS tubes in each 1I1T unit have been omitted. Before applying the driving voltage twice to realize the XOR operation, the memristors in each 1T1R unit used as inputs in the calculation process need to be initialized, that is, the memristors in the 1T1R unit IN ₁ and the 1T1R unit IN ₂ are initialized to a high impedance state.

After initialization is completed, the first step of applying a driving voltage is shown in FIG. 7A , so that the bottom electrode of the memristor in the 1T1R unit OUT is grounded, and a driving voltage V _OR is applied to the bottom electrodes of the memristors in the 1T1R unit IN ₁ and the 1T1R unit IN _2. The second step of applying a driving voltage is shown in FIG. 7B , so that the bottom electrodes of the memristors in the 1T1R unit IN ₁ and the 1T1R unit IN ₂ are grounded, and a driving voltage V _NAND is applied to the bottom electrode of the memristor in the 1T1R unit OUT. Through the above two steps of applying driving voltages, the logical value of the memristor in the 1T1R unit OUT is obtained by either OR operation according to the logical values of the memristors in the 1T1R unit IN ₁ and the 1T1R unit IN ₂ .

Another form of the MAGIC logic gate is that the bottom electrodes of the memristors in the 1T1R unit constituting the MAGIC logic gate are connected together, please refer to Figures 7C and 7D, Figures 7C and 7D respectively show a MAGIC OR gate and a MAGIC NAND gate in which the bottom electrodes of the memristors are connected together. For the numbers in the figures, please refer to the above explanations of the numbers in Figures 7A and 7B. In addition, for the MAGIC OR gate and the MAGIC NAND gate in which the bottom electrodes of the memristors are connected together, it is only necessary to symmetrically modify the application steps of the driving voltage twice to realize the XOR operation. The application steps of the two driving voltages can refer to the specific steps of realizing the XOR operation by connecting the MAGIC NAND gate and the MAGIC OR gate together through the top electrodes of the memristors. In order to avoid repetition, they are not described here.

In order to realize multiple XOR operations in parallel, one row or one column of memristors can be enabled at one time in the 1T1R array. According to the preparation process, there are two types of 1T1R arrays. In different 1T1R arrays, the driving voltage application scheme is modified according to the different forms of MAGIC logic gates to realize multiple XOR operations in parallel.

Please refer to FIG8A . The 1T1R array shown in FIG8A can realize one-time selection of a column of memristors to realize multiple OR operations and exemplify them. In FIG8A , OR-1, OR-2…OR-N are numbers of N OR operations. The gates of 1T1R unit _A1 , 1T1R unit _A2 …1T1R unit _AN are connected to the gate control line _G1 , the gates of 1T1R unit _B1 , 1T1R unit _B2 …1T1R unit _NB are connected to the gate control line _G2 , and the gates of 1T1R unit _L1 , 1T1R unit _L2 …1T1R unit _NL are connected to the gate control line _G3 . The top electrodes of the memristors in the 1T1R cell _A1 , 1T1R cell _B1 and 1T1R cell _L1 are connected to the bit line _WL1 , the top electrodes of the memristors in the 1T1R cell _A2 , 1T1R cell _B2 and 1T1R cell _L2 are connected to the bit line _WL2 … The top electrodes of the memristors in the 1T1R cell _AN , 1T1R cell _NB and 1T1R cell _NL are connected to the bit line _WLN .

A high level is applied to the gate control line _G1 , the gate control line _G2 and the gate control line _G3 to turn on the MOS tubes in each column of the 1T1R unit, thereby turning on the memristors in each column of the 1T1R unit. A high level pulse with an amplitude of _VOR is applied to the word line _BL1 and the word line _BL2 to realize N parallel OR operations, that is, the logic value of the memristor in the 1T1R unit L _i is obtained by performing an OR operation based on the logic value of the memristor in the 1T1R unit A _i and the logic value of the memristor in the 1T1R unit B _i , 1≤i≤N.

Please refer to FIG. 8B . The 1T1R array shown in FIG. 8B can realize one-time gating of a row of memristors. Similarly, multiple OR operations are realized and exemplified. In FIG. 8B , OR-1, OR-2…OR-N are numbers of N OR operations. The gates of 1T1R unit A ₁ , 1T1R unit A ₂ …1T1R unit _AN are connected to the gate control line G ₁ , the gates of 1T1R unit B ₁ , 1T1R unit B ₂ …1T1R unit _NB are connected to the gate control line G ₂ , and the gates of 1T1R unit L ₁ , 1T1R unit L ₂ …1T1R unit _NL are connected to the gate control line G ₃ . The top electrodes of the memristors in the 1T1R cell _A1 , 1T1R cell _B1 and 1T1R cell _L1 are connected to word line _BL3 , the top electrodes of the memristors in the 1T1R cell _A2 , 1T1R cell _B2 and 1T1R cell _L2 are connected to word line _BL2 , ... the top electrodes of the memristors in the 1T1R cell _AN , 1T1R cell _NB and 1T1R cell _NL are connected to word line _BLN .

A high level is applied to the gate control line _G1 , the gate control line _G2 and the gate control line _G3 to turn on the MOS tubes in each column of the 1T1R unit, thereby turning on the memristors in each column of the 1T1R unit. A high level pulse with an amplitude of _VOR is applied to the bit line _WL3 to realize N parallel OR operations, that is, the logic value of the memristor in the 1T1R unit L _i is obtained by performing an OR operation based on the logic value of the memristor in the 1T1R unit A _i and the logic value of the memristor in the 1T1R unit B _i , 1≤i≤N.

It should be noted that, in the two 1T1R arrays shown in FIG8A and FIG8B , the parallelization of multiple XOR operations through MAGIC logic gates can refer to the specific process of implementing multiple OR operations in parallel through the above two 1T1R arrays. In addition, the 1T1R array structure used by the adder in this embodiment is composed of the 1T1R array shown in FIG8A , and the 1T1R array structure of the adder formed by the 1T1R array shown in FIG8B can achieve the same effect, and its specific use can be selected according to actual needs, and is not limited here.

It should be noted that the prerequisite for parallel computing is that all inputs and outputs are aligned. In the memristor-based adder described in Example 1, the top electrodes of all memristors constituting each MAGIC logic gate are connected together, which requires that in the 1T1R array, the memristors constituting the MAGIC logic gate must be in the same row. Therefore, for parallel computing, all memristors constituting the MAGIC logic gate for XOR operation must be in the same row. In the second sub-step, the final result number _Zi is calculated in parallel by the carry number _Qi and the intermediate variable number _Oi , because the carry number Q ₊₁ is calculated by the carry number _Qi of the previous bit and the addend _Xi and the addend _Yi . Therefore, in the calculation process of the first part, not only the calculation of the carry number _Qi+1 must be completed, but also the carry number Qi ₊₁ must be moved to the same column as the addend Xi ₊₁ and the addend Yi ₊₁ , where 1≤i≤N.

For example, assuming that the time to complete the calculation and alignment of a carry Q _out according to the implementation scheme of a one-bit full adder is T _QOUT , then in this embodiment, the first part of the delay T ₁ =N×T _QOUT . The second part of the delay T ₂ is at least the time T _ZOUT of a one-bit full adder to calculate the final result Zout. Therefore, the main delay of the adder is in the first part, and the optimization potential is also mainly in the first part. It is urgent to use fewer steps to complete the calculation and alignment of the carry number Qi _+1. In the embodiment, CCAU is used to calculate the carry number Qi ₊₁ , and the carry number Qi ₊₁ does not need to be in the same row as the addend _Xi , the addend _Yi and the carry number _Qi , and the alignment is directly achieved, which saves the time required for alignment, wherein 1≤i≤N.

The memristor-based adder described in Example 1 stores calculation results directly in the memristor and is non-volatile. The main body of the adder adopts a 1T1R array structure, which has a small area and is easy to integrate. CCAU is used to implement carry during the calculation process, which eliminates alignment work and reduces latency.

Example 2

Referring to FIG. 9 , FIG. 9 is a driving method of an adder provided in this embodiment, and the method can be used to drive the memristor-based adder described in the above-mentioned embodiment 1. The steps of the driving method of the adder are described in detail below:

Step S901, determining the logical value of the memristor in the i+1th 1T1R cell of the third 1T1R subarray according to the logical value of the memristor in the i-th 1T1R cell of the first 1T1R subarray, the logical value of the memristor in the i-th 1T1R cell of the second 1T1R subarray, and the logical value of the memristor in the i-th 1T1R cell of the third 1T1R subarray, 1≤i≤N-1; and determining the logical value of the memristor in the N+1th 1T1R cell of the fifth 1T1R subarray according to the logical value of the memristor in the N-th 1T1R cell of the first 1T1R subarray, the logical value of the memristor in the N-th 1T1R cell of the second 1T1R subarray, and the logical value of the memristor in the N-th 1T1R cell of the third 1T1R subarray.

Specifically, referring to the description in Embodiment 1, the i-th 1T1R unit of the first 1T1R subarray can be represented as 1T1R unit A _i , the i-th 1T1R unit of the second 1T1R subarray can be represented as 1T1R unit B _i , and the i-th 1T1R unit of the third 1T1R subarray can be represented as 1T1R unit C _i . In Embodiment 1, when calculating Z=X+Y, the memristor in the 1T1R unit A _i stores the addend _Xi correspondingly, the memristor in the 1T1R unit B _i stores the addend _Yi correspondingly, and the memristor in the 1T1R unit C _i stores the carry number _Qi correspondingly. It can be seen that the content of step S901 corresponds to the first part of the process of calculating Z=X+Y in Embodiment 1, that is, calculating the carry number _Qi+1 to the next bit through the addend _Xi , _the addend _Yi and the carry number Qi , 1≤i≤N, and the calculation process is as follows:

First, the carry number Q ₂ is calculated by the addend X ₁ , the addend Y ₁ and the carry number Q ₁ , and the carry number Q ₃ is calculated by the addend X ₂ , the addend Y ₂ and the carry number Q ₂ . ... and the carry number Q _N+1 is calculated by the addend X _N , the addend Y _N and the carry number Q _N .

In summary, the calculated carry number _Qi+1 corresponds to the logic value of the memristor in the i+1th 1T1R unit of the third 1T1R subarray described in step S901, and the carry number QN ₊₁ corresponds to the logic value of the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray described in step S901. 1≤i≤N-1. For the specific content of the calculation process of the first part, please refer to the relevant description of the CCAU working process in Example 1. To avoid repetition, it will not be repeated here.

Step S902: Determine the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray according to the logic value of the memristor in the i-th 1T1R unit of the first 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the second 1T1R subarray, 1≤i≤N.

Specifically, referring to the description in Embodiment 1, the i-th 1T1R unit of the first 1T1R subarray may be represented as a 1T1R unit A _i , the i-th 1T1R unit of the second 1T1R subarray may be represented as a 1T1R unit B _i , and the i-th 1T1R unit of the fourth 1T1R subarray may be represented as a 1T1R unit L _i . In Embodiment 1, when calculating Z=X+Y, the memristor in the 1T1R unit A _i corresponds to the storage addend X _i , the memristor in the 1T1R unit B _i corresponds to the storage addend Y _i , and the memristor in the 1T1R unit L _i corresponds to the intermediate variable number O _i .

It can be seen that the content of step S902 corresponds to the first sub-step in the second part of the process of calculating Z=X+Y described in Example 1, that is, the intermediate variable number _Oi is obtained by parallel calculation of the addend _Xi and the addend _Yi , and the calculated intermediate variable number _Oi corresponds to the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray described in step S901, 1≤i≤N. The calculation of the first sub-step is implemented by the MAGIC logic gate. The specific calculation process can refer to the relevant description of the MAGIC logic gate in Example 1, and it will not be repeated here to avoid repetition.

Step S903, determining the logic value of the memristor in the i-th 1T1R unit of the fifth 1T1R subarray according to the logic value of the memristor in the i-th 1T1R unit of the third 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray, 1≤i≤N.

Specifically, please refer to the relevant description of the above step S902. Step S903 corresponds to the second sub-step in the second part of the process of calculating Z=X+Y described in Example 1, that is, the final result number _Zi is calculated in parallel by the carry number _Qi and the intermediate variable number _Oi . The final result number _Zi corresponds to the logic value of the memristor in the i-th 1T1R unit of the fifth 1T1R subarray described in step S903. The calculation of the second sub-step is also implemented by the MAGIC logic gate. The specific calculation process can refer to the relevant description of the MAGIC logic gate in Example 1. To avoid repetition, it will not be repeated here.

Step S904, determining a final result according to the logic values of the memristors in the N+1 1T1R units of the fifth 1T1R subarray, wherein the logic value of the memristor is determined by the resistance state of the memristor, the high resistance state of the memristor represents a logic value of 0, and the low resistance state of the memristor represents a logic value of 1.

Specifically, the memristors in the 1st to N+1st 1T1R units of the fifth 1T1R subarray store the 1st to Nth bits of the final result number _Zi and the carry number QN ₊₁ accordingly. Therefore, after the calculation is completed, the calculation result can be directly obtained through the logic values of the memristors in the N+1st 1T1R units of the fifth 1T1R subarray, that is, the logic values of the memristors in the 1st to N+1st 1T1R units of the fifth 1T1R subarray store the 1st to N+1th bits of the calculation result Z accordingly, 1≤i≤N.

In a specific implementation, the step of determining the logic value of the memristor in the i-th 1T1R unit of the third 1T1R subarray includes:

The logic value of the memristor in the i-1th 1T1R unit of the third 1T1R subarray is determined according to the logic value of the memristor in the i-1th 1T1R unit of the first 1T1R subarray, the logic value of the memristor in the i-1th 1T1R unit of the second 1T1R subarray, and the logic value of the memristor in the i-1th 1T1R unit of the third 1T1R subarray, 2≤i≤N.

In a specific implementation, the step of determining the logical value of the memristor in the i+1th 1T1R unit of the third 1T1R subarray according to the logical value of the memristor in the i-th 1T1R unit of the first 1T1R subarray, the logical value of the memristor in the i-th 1T1R unit of the second 1T1R subarray, and the logical value of the memristor in the i-th 1T1R unit of the third 1T1R subarray, 1≤i≤N-1, and determining the logical value of the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray according to the logical value of the memristor in the N-th 1T1R unit of the first 1T1R subarray, the logical value of the memristor in the N-th 1T1R unit of the second 1T1R subarray, and the logical value of the memristor in the N-th 1T1R unit of the third 1T1R subarray, comprises:

Turning on the gate control line corresponding to the first 1T1R sub-array, the gate control line corresponding to the second 1T1R sub-array, and the gate control line corresponding to the third 1T1R sub-array;

The i-th switch module is turned on, and a driving voltage is applied to the i-th peripheral circuit;

Determine the number of first memristors in a low resistance state among the memristors in the i-th 1T1R unit of the first 1T1R subarray, the memristors in the i-th 1T1R unit of the second 1T1R subarray, and the memristors in the i-th 1T1R unit of the third 1T1R subarray;

Determining whether the number of the first memristors is greater than 1;

When the number of the first memristors is greater than 1, a high level is output to the (i+1)th second bit line through the first end of the i-th peripheral circuit to control the memristor in the i-th 1T1R unit of the third 1T1R subarray to perform a set operation, wherein the set operation is used to switch the memristor from a high resistance state to a low resistance state;

When the number of the first memristors is less than or equal to 1, a low level is output to the i+1th second bit line through the first end of the i-th peripheral circuit to control the memristor in the i-th 1T1R unit of the third 1T1R subarray not to perform the set operation, 1≤i≤N-1.

Specifically, the gate control line _G1 is selected to turn on each MOS transistor in the 1T1R unit A _i , so that the bottom electrode of each memristor in the 1T1R unit A _i is grounded, the gate control line _G2 is selected to turn on each MOS transistor in the 1T1R unit B _i , so that the bottom electrode of each memristor in the 1T1R unit B _i is grounded, and the gate control line _G3 is selected to turn on each MOS transistor in the 1T1R unit C _i , so that the bottom electrode of each memristor in the 1T1R unit C _i is grounded. Then the i-th MOS transistor as a switch is selected to make the 1T1R unit A _i , 1T1R unit B _i , 1T1R unit C _i and the i-th peripheral circuit form CCAU _i , 1≤i≤N. The first number of memristors is the number of memristors in the low resistance state in each 1T1R unit included in CCAU _i .

Through the above steps, the carry number Q ₁ is calculated by CCAU _i . The carry number Q ₁ corresponds to the logic value of the memristor in the i-th 1T1R unit of the third 1T1R subarray, 1≤i≤N-1. For the specific process of calculating the carry number Q ₁ by CCAU, please refer to the relevant description of the CCAU working process in Example 1. To avoid repetition, it will not be repeated here.

In a specific implementation, the step of determining the logical value of the memristor in the i+1th 1T1R cell of the third 1T1R subarray according to the logical value of the memristor in the i-th 1T1R cell of the first 1T1R subarray, the logical value of the memristor in the i-th 1T1R cell of the second 1T1R subarray, and the logical value of the memristor in the i-th 1T1R cell of the third 1T1R subarray, 1≤i≤N-1, and determining the logical value of the memristor in the N+1th 1T1R cell of the fifth 1T1R subarray according to the logical value of the memristor in the N-th 1T1R cell of the first 1T1R subarray, the logical value of the memristor in the N-th 1T1R cell of the second 1T1R subarray, and the logical value of the memristor in the N-th 1T1R cell of the third 1T1R subarray, further includes:

Selecting the gate control line corresponding to the fifth 1T1R sub-array and the Nth switch module, and applying a driving voltage to the Nth peripheral circuit;

Determine the number of second memristors in a low resistance state among the memristors in the Nth 1T1R unit of the first 1T1R subarray, the memristors in the Nth 1T1R unit of the second 1T1R subarray, and the memristors in the Nth 1T1R unit of the third 1T1R subarray;

Determining whether the number of the second memristors is greater than 1;

When the number of the second memristors is greater than 1, a high level is output to the third bit line through the first end of the Nth peripheral circuit to control the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray to perform the set operation;

When the number of the second memristors is less than or equal to 1, a low level is output to the third bit line through the first end of the Nth peripheral circuit to control the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray not to perform the set operation.

Specifically, the gate control line _G5 is turned on, the MOS transistor in the 1T1R unit _CN+1 is turned on, the memristor in the 1T1R unit _CN+1 is grounded, and the Nth MOS transistor as a switch is turned on, so that the 1T1R unit _AN , the 1T1R unit _BN , the 1T1R unit _CN and the Nth peripheral circuit form CCAU _N , and the carry number Q _N+1 is calculated through CCAU _N. 1≤i≤N+1. The carry number Q _N+1 corresponds to the logic value of the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray. The second memristor number refers to the number of memristors in the low resistance state in each 1T1R unit included in the CCAU _N.

In a specific implementation, the step of determining the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray according to the logic value of the memristor in the i-th 1T1R unit of the first 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the second 1T1R subarray includes:

Turning on the gate control line corresponding to the first 1T1R sub-array, the gate control line corresponding to the second 1T1R sub-array, the gate control line corresponding to the fourth 1T1R sub-array, and N switch modules;

Applying or operating a voltage on a word line corresponding to the first 1T1R sub-array and a word line corresponding to the second 1T1R sub-array;

Stop applying the OR operation voltage to the word line corresponding to the first 1T1R sub-array and the word line corresponding to the second 1T1R sub-array, and apply the AND non-operation voltage to the word line corresponding to the fourth 1T1R sub-array;

The logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray is determined according to an XOR operation result of the logic value of the memristor in the i-th 1T1R unit of the first 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the second 1T1R subarray.

Specifically, the gate control line _G1 is selected to turn on the MOS transistor in the 1T1R unit A _i , so that the bottom electrode of the memristor in the 1T1R unit A _i is grounded, the gate control line _G2 is selected to turn on the MOS transistor in the 1T1R unit B _i , so that the bottom electrode of the memristor in the 1T1R unit B _i is grounded, the gate control line _G4 is selected to turn on the MOS transistor in the 1T1R unit L _i , so that the bottom electrode of the memristor in the 1T1R unit L _i is grounded, and then the MOS transistors used as switches in each row are selected to connect the first bit line WL _i-1 and the second bit line WL _i-2 , 1≤i≤N. Thus, the memristors in the 1T1R unit A _i , 1T1R unit B _i and 1T1R unit L _i are selected, which serves as the basis for subsequent logic operations.

In specific implementation, in the first step, the word line _BL4 is grounded, an OR operation voltage is applied to the word line _BL1 and the word line _BL2 , and then the OR operation voltage applied to the word line _BL1 and the word line _BL2 is stopped. In the second step, the word line _BL1 and the word line _BL2 are grounded, and an AND non-operation voltage is applied to the word line _BL4 .

Through the above two steps of applying the driving voltage, the intermediate variable number O _i is obtained by performing a parallel exclusive OR operation on the addend _Xi and the addend _Yi , that is, O _i = _Xi XOR _Yi . The intermediate variable number O _i is the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray, 1≤i≤N.

Please refer to FIG. 10A , which shows the first step of applying a driving voltage in the process of implementing an XOR operation, that is, the bottom electrode of the memristor in the 1T1R unit _Li is grounded, and the driving voltage _VOR is applied to the bottom electrodes of the memristor in the 1T1R unit _Ai and the memristor in the 1T1R unit _Bi . Please refer to FIG. 10B , which shows the second step of applying a driving voltage in the process of implementing an XOR operation, that is, the bottom electrodes of the memristor in the 1T1R unit _Ai and the memristor in the 1T1R unit _Bi are grounded, and the driving voltage _VNAND is applied to the bottom electrode of the memristor in the 1T1R unit _Li .

Through the above two steps of applying the driving voltage, O _i =X _i XOR _Yi can be achieved. It should be noted that before applying the driving voltage V _OR for the first time, the memristor as the output needs to be initialized, that is, the resistance state of the memristor in the 1T1R unit _Li needs to be initialized to a high resistance state.

In a specific implementation, the step of determining the logic value of the memristor in the i-th 1T1R unit of the fifth 1T1R subarray according to the logic value of the memristor in the i-th 1T1R unit of the third 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray includes:

Turning on the gate control line corresponding to the third 1T1R sub-array, the gate control line corresponding to the fourth 1T1R sub-array, and the gate control line corresponding to the fifth 1T1R sub-array;

Applying or operating a voltage to a word line corresponding to the third 1T1R sub-array and a word line corresponding to the fourth 1T1R sub-array;

Stop applying the OR operation voltage to the word line corresponding to the third 1T1R sub-array and the word line corresponding to the fourth 1T1R sub-array, and apply the AND non-operation voltage to the word line corresponding to the fourth 1T1R sub-array;

The logic value of the memristor in the i-th 1T1R unit of the fifth 1T1R subarray is determined according to an XOR operation result of the logic value of the memristor in the i-th 1T1R unit of the third 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray.

Specifically, the gate control line _G3 is turned on to turn on each MOS tube in the 1T1R unit _Ci , so that the bottom electrode of each memristor in the 1T1R unit _Ci is grounded; the gate control line _G4 is turned on to turn on each MOS tube in the 1T1R unit _Li , so that the bottom electrode of each memristor in the 1T1R unit _Li is grounded; the gate control line _G5 is turned on to turn on each MOS tube in the 1T1R unit _Si , so that the bottom electrode of each memristor in the 1T1R unit _Si is grounded.

In specific implementation, in the first step, the word line BL ₅ is grounded, an OR operation voltage is applied to the word line BL ₃ and the word line BL ₄ , and then the OR operation voltage applied to the word line BL ₃ and the word line BL ₄ is stopped. In the second step, the word line BL ₃ and the word line BL ₄ are grounded, and an AND non-operation voltage is applied to the word line BL ₅ .

Through the above two steps of applying the driving voltage, the final result number _Zi can be obtained by performing an XOR operation on the intermediate variable number _Oi and the carry number _Qi , that is, _Zi = _Oi XOR _Qi . The final result number _Zi corresponds to the logic value of the memristor in the i-th 1T1R unit of the fifth 1T1R subarray, 1≤i≤N. The above two steps of applying the driving voltage refer to the specific application process of the driving voltage in FIG. 10A and FIG. 10B, and will not be repeated here to avoid repetition.

It should be supplemented that Table 2 is a table of driving voltage application schemes in each calculation process.

Table 2. Driving voltage application scheme for memristor-based adder

Table 2 shows the gate connections and MOS tubes selected in each step of the process of calculating Z=X+Y, as well as the driving voltage applied to the corresponding memristor. Steps 1 to N correspond to the first part of the calculation process, that is, the carry number _Qi+1 to the next _digit is calculated by addend _Xi , addend _Yi and carry number Qi. Steps N+1 to N+4 correspond to the second part of the calculation process, that is, the final result number _Zi is calculated in parallel by addend _Xi , addend _Yi and carry number _Qi , wherein steps N+1 to N+2 correspond to the calculation of the intermediate variable number _Oi by addend _Xi and addend _Yi in parallel, and steps N+3 to N+4 correspond to the calculation of the final result number _Zi by the intermediate variable number _Oi and carry number _Qi in parallel, 1≤i≤N.

Example 3

This embodiment provides an electronic device, which stores a computer program. When the computer program is run on a processor, the method for driving the adder provided in the above-mentioned embodiment 2 is executed.

The electronic device provided in this embodiment can implement the steps of the method for driving the adder provided in Embodiment 2, and will not be described again to avoid repetition.

In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and structure diagrams in the accompanying drawings show the possible architectures, functions and operations of the devices, methods and computer program products according to the various embodiments of the present invention.

If the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a smart phone, a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims (10)

1. A memristor-based adder, characterized in that it comprises: a 1T1R array, N peripheral circuits, the 1T1R array comprises a first 1T1R subarray, a second 1T1R subarray, a third 1T1R subarray, a fourth 1T1R subarray, and a fifth 1T1R subarray which are sequentially arranged, the first 1T1R subarray, the second 1T1R subarray, the third 1T1R subarray, and the fourth 1T1R subarray respectively comprise N 1T1R units, the fifth 1T1R subarray comprises N+1 1T1R units, each 1T1R unit comprises a memristor and a MOS tube, and the bottom electrode of the memristor is connected to the source or drain of the MOS tube; The drain or source of the MOS transistor in each 1T1R unit of each 1T1R sub-array is connected to the word line of the corresponding column, and the gate of the MOS transistor in each 1T1R unit of each 1T1R sub-array is connected to the gate control line of the corresponding column; The top electrodes of the memristors in the i-th 1T1R unit of the first 1T1R subarray and the i-th 1T1R unit of the second 1T1R subarray are connected to the i-th first bit line, the top electrodes of the memristors in the i-th 1T1R unit of the third 1T1R subarray, the i-th 1T1R unit of the fourth 1T1R subarray and the i-th 1T1R unit of the fifth 1T1R subarray are connected to the i-th second bit line, the top electrode of the memristor in the N+1-th 1T1R unit of the fifth 1T1R subarray is connected to the third bit line, the second end of the i-th first bit line is connected to the first end of the i-th second bit line through the switch module, 1≤i≤N; The second end of the i-th peripheral circuit is connected to the first end of the i-th first bit line, the first end of the i-th peripheral circuit is connected to the second end of the i+1-th second bit line, 1≤i≤N-1, and the first end of the N-th peripheral circuit is connected to the first end or the second end of the third bit line. 2. The memristor-based adder according to claim 1 is characterized in that each peripheral circuit includes an inverter and a voltage-dividing resistor, the voltage-dividing resistor is connected to the input end of the inverter, the output end of the inverter is the first end of the peripheral circuit, the input end of the inverter is the second end of the peripheral circuit, the resistance state of the memristor includes a high resistance state and a low resistance state, and the resistance value of the voltage-dividing resistor is equal to the resistance value corresponding to the memristor in the low resistance state. 3. The memristor-based adder according to claim 2 is characterized in that the inverter comprises a PMOS tube and an NMOS tube, the gate of the PMOS tube is connected to the gate of the NMOS tube and serves as the input of the inverter, the drain of the PMOS tube is connected to the drain of the NMOS tube and serves as the output of the inverter, the source of the PMOS tube is connected to a power supply, and the source of the NMOS tube is grounded. 4. A method for driving an adder, characterized in that it is applied to the memristor-based adder according to any one of claims 1 to 3, and the method comprises: Determine the logical value of the memristor in the i+1th 1T1R cell of the third 1T1R subarray according to the logical value of the memristor in the i-th 1T1R cell of the first 1T1R subarray, the logical value of the memristor in the i-th 1T1R cell of the second 1T1R subarray, and the logical value of the memristor in the i-th 1T1R cell of the third 1T1R subarray, 1≤i≤N-1; and determine the logical value of the memristor in the N+1th 1T1R cell of the fifth 1T1R subarray according to the logical value of the memristor in the N-th 1T1R cell of the first 1T1R subarray, the logical value of the memristor in the N-th 1T1R cell of the second 1T1R subarray, and the logical value of the memristor in the N-th 1T1R cell of the third 1T1R subarray; Determine the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray according to the logic value of the memristor in the i-th 1T1R unit of the first 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the second 1T1R subarray, 1≤i≤N; Determine the logic value of the memristor in the i-th 1T1R unit of the fifth 1T1R subarray according to the logic value of the memristor in the i-th 1T1R unit of the third 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray, 1≤i≤N; The final result is determined according to the logic value of the memristor in the N+1 1T1R units of the fifth 1T1R subarray, wherein the logic value of the memristor is determined by the resistance state of the memristor, the high resistance state of the memristor represents the logic value 0, and the low resistance state of the memristor represents the logic value 1. 5. The method for driving an adder according to claim 4, wherein the step of determining the logic value of the memristor in the i-th 1T1R unit of the third 1T1R subarray comprises: The logic value of the memristor in the i-1th 1T1R unit of the third 1T1R subarray is determined according to the logic value of the memristor in the i-1th 1T1R unit of the first 1T1R subarray, the logic value of the memristor in the i-1th 1T1R unit of the second 1T1R subarray, and the logic value of the memristor in the i-1th 1T1R unit of the third 1T1R subarray, 2≤i≤N. 6. The driving method of the adder according to claim 4, characterized in that the step of determining the logical value of the memristor in the i+1th 1T1R unit of the third 1T1R subarray according to the logical value of the memristor in the i-th 1T1R unit of the first 1T1R subarray, the logical value of the memristor in the i-th 1T1R unit of the second 1T1R subarray, and the logical value of the memristor in the i-th 1T1R unit of the third 1T1R subarray, 1≤i≤N-1, and determining the logical value of the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray according to the logical value of the memristor in the N-th 1T1R unit of the first 1T1R subarray, the logical value of the memristor in the N-th 1T1R unit of the second 1T1R subarray, and the logical value of the memristor in the N-th 1T1R unit of the third 1T1R subarray comprises: Turning on the gate control line corresponding to the first 1T1R sub-array, the gate control line corresponding to the second 1T1R sub-array, and the gate control line corresponding to the third 1T1R sub-array; The i-th switch module is turned on, and a driving voltage is applied to the i-th peripheral circuit; Determine the number of first memristors in a low resistance state among the memristors in the i-th 1T1R unit of the first 1T1R subarray, the memristors in the i-th 1T1R unit of the second 1T1R subarray, and the memristors in the i-th 1T1R unit of the third 1T1R subarray; Determining whether the number of the first memristors is greater than 1; When the number of the first memristors is greater than 1, a high level is output to the i+1th second bit line through the first end of the i-th peripheral circuit to control the memristor in the i+1th 1T1R unit of the third 1T1R subarray to perform a set operation, wherein the set operation is used to switch the memristor from a high resistance state to a low resistance state; When the number of the first memristors is less than or equal to 1, a low level is output to the i+1 second bit line through the first end of the i-th peripheral circuit to control the memristor in the i+1-th 1T1R unit of the third 1T1R subarray not to perform the set operation, 1≤i≤N-1. 7. The driving method of the adder according to claim 6, characterized in that the step of determining the logical value of the memristor in the i+1th 1T1R unit of the third 1T1R subarray according to the logical value of the memristor in the i-th 1T1R unit of the first 1T1R subarray, the logical value of the memristor in the i-th 1T1R unit of the second 1T1R subarray, and the logical value of the memristor in the i-th 1T1R unit of the third 1T1R subarray, 1≤i≤N-1, and determining the logical value of the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray according to the logical value of the memristor in the N-th 1T1R unit of the first 1T1R subarray, the logical value of the memristor in the N-th 1T1R unit of the second 1T1R subarray, and the logical value of the memristor in the N-th 1T1R unit of the third 1T1R subarray, further comprises: Selecting the gate control line corresponding to the fifth 1T1R sub-array and the Nth switch module, and applying a driving voltage to the Nth peripheral circuit; Determine the number of second memristors in a low resistance state among the memristors in the Nth 1T1R unit of the first 1T1R subarray, the memristors in the Nth 1T1R unit of the second 1T1R subarray, and the memristors in the Nth 1T1R unit of the third 1T1R subarray; Determining whether the number of the second memristors is greater than 1; When the number of the second memristors is greater than 1, a high level is output to the third bit line through the first end of the Nth peripheral circuit to control the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray to perform the set operation; When the number of the second memristors is less than or equal to 1, a low level is output to the third bit line through the first end of the Nth peripheral circuit to control the memristor in the N+1th 1T1R unit of the fifth 1T1R subarray not to perform the set operation. 8. The driving method of the adder according to claim 4, characterized in that the step of determining the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray according to the logic value of the memristor in the i-th 1T1R unit of the first 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the second 1T1R subarray comprises: Turning on the gate control line corresponding to the first 1T1R sub-array, the gate control line corresponding to the second 1T1R sub-array, the gate control line corresponding to the fourth 1T1R sub-array, and N switch modules; Applying or operating a voltage on a word line corresponding to the first 1T1R sub-array and a word line corresponding to the second 1T1R sub-array; Stop applying the OR operation voltage to the word line corresponding to the first 1T1R sub-array and the word line corresponding to the second 1T1R sub-array, and apply the AND non-operation voltage to the word line corresponding to the fourth 1T1R sub-array; The logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray is determined according to an XOR operation result of the logic value of the memristor in the i-th 1T1R unit of the first 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the second 1T1R subarray. 9. The driving method of the adder according to claim 4, characterized in that the step of determining the logic value of the memristor in the i-th 1T1R unit of the fifth 1T1R subarray according to the logic value of the memristor in the i-th 1T1R unit of the third 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray comprises: Turning on the gate control line corresponding to the third 1T1R sub-array, the gate control line corresponding to the fourth 1T1R sub-array, and the gate control line corresponding to the fifth 1T1R sub-array; Applying or operating a voltage to a word line corresponding to the third 1T1R sub-array and a word line corresponding to the fourth 1T1R sub-array; Stop applying the OR operation voltage to the word line corresponding to the third 1T1R sub-array and the word line corresponding to the fourth 1T1R sub-array, and apply the AND non-operation voltage to the word line corresponding to the fourth 1T1R sub-array; The logic value of the memristor in the i-th 1T1R unit of the fifth 1T1R subarray is determined according to an XOR operation result of the logic value of the memristor in the i-th 1T1R unit of the third 1T1R subarray and the logic value of the memristor in the i-th 1T1R unit of the fourth 1T1R subarray. 10. An electronic device, characterized in that a computer program is stored therein, and when the computer program is run on a processor, the driving method of the adder according to any one of claims 4 to 9 is executed.