CN115954029A - Multi-bit operation module and in-memory calculation circuit structure using the same - Google Patents

Abstract

The present invention relates to the field of static random access memory technology, and more particularly, to a multi-bit arithmetic module and a memory computing circuit structure using the same. The multi-bit operation module completes multi-bit multiply-accumulate operation by calculating discharge accumulation of the bit line load capacitance, the design of bit weight division and global bit line separation has good calculation parallelism and stability and higher reasoning precision, and the multi-bit operation module is matched with a subsequent quantization unit module to obtain quantization output and can support multi-bit MAC operation in a deep neural network.

Description

Multi-bit operation module and in-memory calculation circuit structure using the module

technical field

The invention relates to the technical field of static random access memory, and more specifically, relates to a multi-bit computing module and an in-memory computing circuit structure using the module.

Background technique

In recent years, Convolutional Neural Networks (CNN) have achieved unprecedented success in many applications involving artificial intelligence (AI) and the Internet of Things (IoT), such as image recognition, voice keyword detection, face recognition, etc. .

However, limited by computing hardware, it is inefficient when dealing with AI tasks. Traditional computing hardware is based on the von Neumann architecture. Since the memory and the computing unit are two independent parts, when the computer performs computing operations, it needs to fetch data from the memory, transfer it to the computing unit for calculation, and then write it back. memory. Due to the movement of data between processing elements (Processing Elements, PEs) and memory, it is prone to excessive energy consumption and latency problems, known as "storage walls". Computing In Memory (CIM) breaks the von Neumar architecture of traditional computers, embeds computing circuits in memory, and integrates storage and computing, thereby greatly reducing data migration and memory access consumption.

Nonvolatile Computing In Memory (Nonvolatile Computing In Memory) has great advantages in battery-powered micro AI devices that require nonvolatile data storage and low power consumption. The current non-volatile in-memory computing technology solution supports binary neural networks (BNNs) or binary weight networks (BWNs), which reduces storage requirements to a certain extent and improves energy efficiency. However, BNNs and BWNs are only suitable for simple networks, and can only provide limited system-level reasoning accuracy when applied to complex applications, which limits the further development of AI technology. Therefore, Multiply And Accumulate (MAC) in-memory computing technology with multi-bit input (IN), weight (W) and output (OUT) is extremely important for advanced AI edge chips that require high inference accuracy.

Contents of the invention

Based on this, it is necessary to provide a multi-bit computing module and an in-memory computing circuit structure using the module for the problem of limited reasoning accuracy of traditional in-memory computing.

The present invention adopts following technical scheme to realize:

In a first aspect, the present invention provides a multi-bit calculation module, including a bit division calculation module 1 and a bit division calculation module 2.

The bit division calculation module 1 includes n cascaded calculation units 1 and n weight bit lines 1 LW[1]˜LW[n].

Wherein, the kth cascaded computing unit 1 includes 4 NMOS transistors N1[k], N2[k], N3[k], N4[k]. The specifications of N1[k] and N2[k] are the same. 1≤k≤n.

The gate of N1[k] is connected to the weight bit line one LW[k], the drain is connected to the calculation bit line CBL, and the source is connected to the node one X1[k]. The gate of N2[k] is connected to weight bit line one LW[k], the drain is connected to calculation bit line CBLB, and the source is connected to node two X2[k]. The gate of N3[k] is connected to the global bit line GBL, the drain is connected to node one X1[k], and the source is connected to the ground GND. N4[k], its gate is connected to the global bit line GBLB, its drain is connected to node 2 X2[k], and its source is connected to the ground GND.

The sub-bit computing module 2 includes n cascaded computing units 2 and n even-weighted bit lines 2 RW[1]-RW[n].

Wherein, the k-th cascaded computing unit 2 includes four NMOS transistors N5[k], N6[k], N7[k], and N8[k]. The specifications of N5[k] and N6[k] are the same. The specifications of N7[k], N8[k], N3[k], and N4[k] are the same, and the aspect ratio of N5[k] is h times that of N1[k].

The gate of N5[k] is connected to weight bit line two RW[k], the drain is connected to calculation bit line CBL, and the source is connected to node three X3[k]. The gate of N6[k] is connected to weight bit line 2 RW[k], the drain is connected to calculation bit line CBLB, and the source is connected to node 4 X4[k]. The gate of N7[k] is connected to the global bit line GBL, the drain is connected to node 3 X3[k], and the source is connected to the ground GND. The gate of N8[k] is connected to the global bit line GBLB, the drain is connected to node 4 X4[k], and the source is connected to the ground GND.

The weight bit line two RW[k] and the weight bit line one LW[k] are used to provide weight values. Global bit lines GBL, GBLB are used to provide multi-bit input values.

The multi-bit calculation module works in parallel with the selection columns of the bit-divided calculation module 1 and the bit-divided calculation module 2, receives weight values and multi-bit input values, and performs multi-bit multiplication and accumulation calculations. Calculation bit lines CBL and CBLB are used to reflect multi-bit multiplication and accumulation calculation results through voltage variation.

The realization of this multi-bit operation module is according to the method or process of the embodiment of the present disclosure.

In the second aspect, the present invention discloses an in-memory computing circuit structure, including a storage array module, a data selection module, a sense amplifier module, a mode selection module, a multi-bit operation module disclosed in the first aspect, a quantization unit module, and a timing control circuit module .

The storage array module is used to provide a standard read-write mode and a multi-bit multiply-accumulate calculation mode. The storage array module includes a storage unit and a reference unit. The data selection module includes a column selection module and a row decoding module, which are used for positioning and accessing corresponding storage units in the storage unit according to external address signals in standard read-write mode. The column selection module is also connected with a writing drive circuit, which is used to control writing to the storage unit. The sense amplifier module is used to compare the read current generated by the storage unit with the reference current of the reference unit to generate a conversion voltage, amplify the conversion voltage and obtain an output weight value. The sense amplifier module is also connected with a read-out driving circuit, which is used to read the output weight value during the read operation in the standard read-write mode. The mode selection module is used to switch the standard read-write mode and the multi-bit multiply-accumulate calculation mode of the storage array module. In the multi-bit calculation function mode, the multi-bit calculation module performs multi-bit multiplication and accumulation calculation according to the weight value and multi-bit input value. The multi-bit operation module is connected with an input register for inputting multi-bit input values into the multi-bit operation module through the global bit lines GBL and GBLB. The quantization unit module is used to quantize the accumulated voltage variation of the calculated bit lines CBL and CBLB in the multi-bit multiply-accumulate calculation mode to obtain a quantized output. The timing control circuit module is used to control the timing of each part of the in-memory computing circuit structure to make it work correspondingly.

The implementation of this in-memory computing circuit structure is according to the method or process of the embodiment of the present disclosure.

Compared with the prior art, the present invention has the following beneficial effects:

1. The multi-bit operation module of the present invention completes the multi-bit multiplication and accumulation operation by calculating the discharge and accumulation of the bit line load capacitance, and the design of dividing bit weights and separating global bit lines has good calculation parallelism and stability, and has high Inference accuracy, and cooperate with the subsequent quantization unit module to obtain quantized output, which can support multi-bit MAC operation of deep neural network.

2. The memory array module of the present invention adopts MRAM composed of 1T-1MTJ memory cells, which has high storage density and computing power density, and can reduce area overhead. The invention can complete multi-bit multiplication and accumulation operation while accessing the memory, and can significantly reduce the overall power consumption of the network.

3. The present invention realizes multi-bit multiplication and accumulation calculation based on MRAM, has the characteristics of low static power consumption and non-volatility, and has advantages in equipment applications requiring non-volatile storage of data and low-power consumption batteries.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only are some embodiments of the present invention, for those of ordinary skill in the art,

Other drawings can also be obtained from these drawings without any creative effort.

FIG. 1 is a schematic structural diagram of an in-memory computing circuit structure in Embodiment 1 of the present invention;

Fig. 2 is the structural diagram of memory array module, column selector module, sense amplifier module, mode selector module, multi-bit computing module in Fig. 1;

Fig. 3 is a structural diagram of the left storage array and the left reference array in Fig. 2;

Fig. 4 is a structural diagram of the right storage array and the left reference array in Fig. 2;

Fig. 5 is a structural diagram of a pair of cascaded computing units formed by the k-th cascaded computing unit 1 and the k-th cascaded computing unit 2 in the multi-bit computing module in Fig. 2;

Fig. 6 is the equivalent circuit diagram of multiplying and accumulating calculation in the analog domain of the multi-bit computing module in Fig. 2;

Fig. 7 is a structural diagram of the sense amplifier module in Fig. 2;

FIG. 8 is a transient simulation waveform diagram of a read operation performed by the sense amplifier module in FIG. 7;

Fig. 9 is a structural diagram of the quantization unit module in Fig. 2;

FIG. 10 is a schematic diagram of the quantization process of the quantization unit module in FIG. 9;

Fig. 11 is a schematic diagram of the multi-bit operation module in Fig. 2 performing 2-bit input and 2-bit weight multiplication and accumulation calculation results;

Fig. 12 is the Monte Carlo simulation result diagram A of the in-memory computing circuit structure in Fig. 1 based on 2-bit input and 2-bit weight multiplication and accumulation calculation;

Fig. 13 is the in-memory computing circuit structure of Fig. 1 based on 2-bit input and 2-bit weight multiplication and accumulation calculation Monte Carlo simulation result diagram B;

Fig. 14 is the Monte Carlo simulation result diagram C of the in-memory computing circuit structure in Fig. 1 based on 2-bit input and 2-bit weight multiplication and accumulation calculation;

15 is a schematic diagram of system power consumption and energy efficiency varying with operating voltage in the in-memory computing circuit structure provided by Embodiment 1 of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

It should be noted that when a component is said to be "mounted on" another component, it can be directly on the other component or there can also be an intervening component. When a component is said to be "set on" another component, it may be set directly on the other component or there may be an intervening component at the same time. When a component is said to be "fixed" to another component, it may be directly fixed to the other component or there may be an intervening component at the same time.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "or/and" includes any and all combinations of one or more of the associated listed items.

Example 1

Referring to FIG. 1 , it is a schematic structural diagram of the in-memory computing circuit structure disclosed in the first embodiment.

The in-memory computing circuit structure includes a storage array module, a data selection module, a sensitive amplifier module, a mode selection module, a multi-bit operation module, a quantization unit module, and a timing control circuit module. Referring to FIG. 3 , the structural diagram of the memory array module, the column selection module, the sense amplifier module, the mode selector module, and the multi-bit operation module are shown sequentially from top to bottom.

The storage array module is used to provide a standard read-write mode and a multi-bit multiply-accumulate calculation mode. The storage array module includes a storage unit and a reference unit, including an array of (2N+2N/j) columns and M rows.

Specifically, as shown in Figure 2, the storage unit includes a left storage array and a right storage array:

As shown in Figure 3, it is an enlarged view of the left part of Figure 2. The left storage array includes N columns and M rows of storage units; wherein, every j column constitutes a group of left sub-arrays, and the left storage array includes N/j groups of left sub-arrays.

As shown in Fig. 4, it is an enlarged view of the right part of Fig. 2 . The right storage array also includes N columns and M rows of storage units; wherein, every j column constitutes a group of right sub-arrays, and the right storage array includes N/j groups of right sub-arrays.

The reference part includes a left reference array and a right reference array: the left reference array includes left reference units corresponding to N/j columns and M rows of the left storage array. Wherein, the left reference unit of the kth column is set corresponding to the left subarray of the kth group; 1≤k≤N/j. Similarly, the right reference array includes right reference units corresponding to N/j columns and M rows of the right storage array; wherein, the right reference unit in the kth column corresponds to the kth group of right subarrays.

The storage unit, the left reference unit, and the right reference unit are all based on MRAM. The difference is that the connected bit lines and source lines are different:

The storage unit includes an NMOS transistor M1 and a magnetic tunnel junction device MTJ1. The gate of the NMOS transistor M1 is connected to the word line WL, and the drain is connected to the source line SL. One end of the magnetic tunnel junction device MTJ1 is electrically connected to the bit line BL, and the other end is electrically connected to the source of M1.

The left reference unit and the right reference unit have the same structure, including an NMOS transistor M2 and a magnetic tunnel junction device MTJ2. The gate of the NMOS transistor M2 is connected to the word line WL, and the drain is connected to the reference source line. One end of the magnetic tunnel junction device MTJ2 is electrically connected to the reference bit line, and the other end is electrically connected to the source of M2.

It should be noted that the magnetic tunnel junction devices MTJ1 and MTJ2 will exhibit two states of high resistance and low resistance according to the direction of the write operation current.

The memory cells, the left reference cell and the right reference cell in the same row share the same word line WL. Memory cells in the same column share the same bit line BL and the same source line SL. The left reference cells in the same column share the same reference bit line and the same reference source line. The right reference cells in the same column share the same reference bit line and the same reference source line.

Wherein, the kth reference bit line of the left reference array is used to output the reference current I _REF1 [k], and the kth reference bit line of the right reference array is used to output the reference current I _REF2 [k].

The multi-bit calculation module is set corresponding to the storage array module, and is used for multi-bit multiplication and accumulation calculation according to the weight value and multi-bit input value in the multi-bit calculation function mode. Wherein, the multi-bit operation module is connected with an input register, which is used for inputting multi-bit input values into the multi-bit operation module through the global bit line GBL and the global bit line GBLB. The weight values come from the sense amplifier block.

The multi-bit calculation module includes a bit division calculation module 1 and a bit division calculation module 2.

The bit division calculation module 1 includes n cascaded calculation units 1 and n weight bit lines 1 LW[1]˜LW[n].

Referring to FIG. 5 , the k-th cascaded computing unit includes 4 NMOS transistors N1(k), N2(k), N3(k), and N4(k).

The gate of N1(k) is connected to the k-th weight bit line—LW(k), the drain is connected to the calculation bit line CBL, and the source is connected to the k-th node—X1(k). The gate of N2(k) is connected to the weight bit line one LW(k), the drain is connected to the calculation bit line CBLB, and the source is connected to the kth node two X2(k). The gate of N3(k) is connected to the global bit line GBL, the drain is connected to node-X1(k), and the source is connected to the ground GND. The gate of N4(k) is connected to the global bit line GBLB, the drain is connected to node 2 X2(k), and the source is connected to the ground GND.

The sub-bit computing module 2 includes n cascaded computing units 2 and n even-weighted bit lines 2 RW[1]-RW[n].

Referring to FIG. 5 , the second kth cascaded computing unit includes four NMOS transistors N5[k], N6[k], N7[k], and N8[k]. The gate of N5[k] is connected to the k-th weight bit line 2 RW[k], the drain is connected to the calculation bit line CBL, and the source is connected to the k-th node 3 X3[k]. The gate of N6[k] is connected to the weight bit line 2 RW[k], the drain is connected to the calculation bit line CBLB, and the source is connected to the kth node 4 X4[k]. The gate of N7[k] is connected to the global bit line GBL, the drain is connected to node 3 X3[k], and the source is connected to the ground GND. The gate of N8[k] is connected to the global bit line GBLB, the drain is connected to node 4 X4[k], and the source is connected to the ground GND.

It should be emphasized that n=N/j. The specifications of N1[k] and N2[k] are the same, 1≤k≤n. The specifications of N5[k] and N6[k] are the same. The specifications of N7[k], N8[k], N3[k], and N4[k] are the same. The width-to-length ratio of N5[k] is h times the width-to-length ratio of N1[k]. By adjusting the value of h, the conduction current of the cascaded computing units is weighted and controlled.

The weight bit line two RW[k] and the weight bit line one LW[k] are used to provide weight values. Global bit lines GBL, GBLB are used to provide multi-bit input values.

The multi-bit calculation module works in parallel with the selection columns of the bit-divided calculation module 1 and the bit-divided calculation module 2, receives weight values and multi-bit input values, and performs multi-bit multiplication and accumulation calculations. Calculation bit lines CBL and CBLB are used to reflect multi-bit multiplication and accumulation calculation results through voltage variation.

In the multi-bit multiply-accumulate calculation mode, the multi-bit operation module uses the discharge information of the calculated bit line capacitance (C _CBL /C _CBLB ) to realize the convolution operation on the neural network.

In general, both the left and right storage arrays have N columns and M rows, and each storage array is divided into N/j groups of sub-arrays according to j columns. The left storage array corresponds to the first cascaded computing unit (ie, the low-order cascaded computing unit), and the right storage array corresponds to the second cascaded computing unit (ie, the high-order cascaded computing unit). Under the standard read-write mode and the multi-bit multiplication and accumulation calculation mode, the N/j groups of sub-arrays in the left and right storage arrays all work in parallel, and the left and right sub-arrays of the corresponding positions (that is, the kth group of left sub-arrays, The kth right sub-array) is a pair, a total of N/j pairs; the cascaded computing unit one corresponding to the left storage array and the second cascaded computing unit corresponding to the right storage array (ie the kth low-order cascaded computing unit , the kth high-level cascaded computing unit) form a pair of cascaded computing units, a total of N/j pairs, as shown in Figure 5, which ensures the parallelism and stability of the calculation.

After the memory array module completes the standard read operation, N/j pairs of stored data are read out through the sense amplifier module, and each pair of outputs consists of DOUTL[k] and DOUTR[k] to form a 2-bit weight W[1:0].

In the multi-bit multiplication and accumulation calculation mode, MEN is set to high level, N/j pairs of 2-bit weights are divided into bits and transmitted to the corresponding N/j pairs of cascaded calculation units, and the external 4-bit input is IN[3:0] Divided into two groups (IN[3:2], IN[1:0]) and transmitted to the global bit line GBL/GBLB respectively, characterized by the duration of VGBL/VGBLB high level, the calculation results correspond to the calculation of the bit line CBL/ The amount of voltage change on CBLB.

When a single pair of cascaded computing units is activated, it starts to read the weight information output by the corresponding sense amplifier (CSA):

If the read weight W[1:0] is "00", the calculation unit does not generate current, that is, the result of the multiplication operation is 0; if the read weight W[1:0] is 1 "01", " 10" and "11", then calculate the bit line capacitance (CCBL/CCBLB). The pair of calculation units starts to discharge the calculation unit, and finally multiply and accumulate the results to generate discharge currents I, 2I and 3I respectively, and correspond to the global according to the input value The discharge time produces a discharge voltage drop on the compute bit line CBL/CBLB.

The discharge and accumulation of the multiplication result of the N/j pair on the corresponding calculation bit line CBL/CBLB, that is, the total voltage change on the CBL/CBLB corresponds to the final multiplication and accumulation calculation result.

Referring to Figure 6, it is an equivalent circuit diagram for the multi-bit operation module to perform 2-bit input and 2-bit weight multiplication and accumulation calculation. Take half of the first cascaded computing unit 1 and half of the first cascaded computing unit 2 for illustration . In this embodiment, h is set to 2.

N1[1] and N2[1] (not shown) form a low-order cascade computing unit, which reads the weight value stored in the left storage sub-array. N5[1] and N6[1] (not shown) form a high-level cascaded computing unit to read the weight value stored in the right storage sub-array, where LW[1] and RW[1] represent the left storage sub-array respectively The weight value of the right storage sub-array, that is, the 2-bit weight W[1:0] is transmitted to the high-order cascaded computing unit and the low-order cascaded computing unit, and a pair of 2-bit input IN[3:2] is transmitted To the global bit line GBL, the high level duration T _GBL of V _GBL is determined according to the input data. The width-to-length ratio of N5[1] is twice that of N1[1]. When both the high-order cascade computing unit and the low-order cascade computing unit are turned on, the current I ₂ generated when the high-order cascade unit is turned on is the low-order cascade Calculate twice the cell conduction current _I1 .

The above-mentioned multi-bit operation module supports multiply-accumulate operations involving multi-bit input and multi-bit weights. Compared with existing single-bit multiply-accumulate operations and Boolean logic operations, this multi-bit operation module is suitable for a variety of multi-bit neural networks , which can improve the inference accuracy of AI edge devices.

For the memory array module, it is necessary to configure a data selection module for positioning and accessing the corresponding storage unit in the storage unit according to the external address signal in the standard read-write mode. According to the distribution characteristics of the storage array, the data selection module includes a row decoding module and a column selection module, the latter is used to enable the corresponding row, and the former is used to enable the corresponding row. The column selection module is also connected with a writing drive circuit, which is used to control writing to the storage unit.

(1) The row decoding module is connected to the word line WL (not shown in FIG. 3 ), and the M word lines WL share the same row decoding module (ie, the same row decoder).

(2) The column selection module includes n column selectors 1 and n column selectors 2. As shown in Figure 3,

The kth column selector 1 is set corresponding to the kth group of left sub-arrays. The bit line BL of the left sub-array of the kth group is connected to the input terminal of the kth column selector 1, and the output terminal of the kth column selector 1 outputs the read current I _CELL1 [k].

The kth column selection two is set correspondingly to the kth group of right subarrays. The bit line BL of the right sub-array of the kth group is connected to the input terminal of the kth column selector 2, and the output terminal of the kth column selector 2 outputs the read current I _CELL2 [k].

The n column selectors 1 and n column selectors 2 share the same addressing signal CS, which is convenient for unified control. Specifically, the addressing signal CS is input to the column selection module to enable the k-th column, the first column selector activates the k-th left sub-array, and the second column selector enables the k-th right sub-array.

The sense amplifier module is used to compare the read current generated by the storage unit with the reference current of the reference unit to generate a conversion voltage, amplify the conversion voltage and obtain an output weight value.

As shown in FIG. 3 , the sense amplifier module includes n sense amplifiers 1 and n sense amplifiers 2 .

(A) The kth sense amplifier one is connected to the kth column selector one. The k-th sense amplifier 1 includes the k-th current sampling unit 1 and the k-th voltage amplifier 1 for sampling and comparing I _CELL1 [k] and I _REF1 [k], and outputting DOUTL[k].

Specifically, referring to FIG. 7 , the current sampling unit 1 includes 6 PMOS transistors P1 ˜ P6 and 4 NMOS transistors NM1 ˜ NM4 .

The gate of P1 is connected to the external enable signal SAEN, the source is connected to the power supply VDD, and the drain is connected to the first node NET1. The gate and drain of P2 are connected to the first node NET1, and the source is connected to the power supply VDD. The gate of P3 is connected to the first node NET1, the source is connected to the power supply VDD, and the drain is connected to the first-stage output node SO. The gate of P4 is connected to the second node NET2 , the source is connected to the power supply VDD, and the drain is connected to the first-stage output node SOB. The gate and drain of P5 are connected to the second node NET2, and the source is connected to the power supply VDD. The gate of P6 is connected to the external enable signal SAEN, the source is connected to the power supply VDD, and the drain is connected to the second node NET2.

The gate of NM1 is connected to the clamping signal CLP, the source is connected to the read current I _CELL , and the drain is connected to the first node NET1. The gate of NM2 is connected to the first-stage output node SOB, the source is connected to the ground GND, and the drain is connected to the first-stage output node SO. The gate and drain of NM3 are connected to the first-stage output node SOB, and the source is connected to the ground GND. The gate of NM4 is connected to the clamping signal CLP, the source is connected to the reference current I _REF , and the drain is connected to the second node NET2.

Voltage amplifier one includes 2 PMOS transistors P7-P8, 3 NMOS transistors NM5-NM7, and 1 inverter INV.

The gate and drain of P7 are connected to the third node NET3, and the source is connected to the power supply VDD. The gate and drain of P8 are connected to the fourth node NET4, and the source is connected to the power supply VDD. The gate of NM5 is connected to the first-stage output node SO, the source is connected to the fifth node NET5, and the drain is connected to the third node NET3. The gate of NM6 is connected to the first-stage output node SOB, the source is connected to the fifth node NET5, and the drain is connected to the fourth node NET4. The gate of NM7 is connected to the external enable signal SAEN, the source is connected to the ground GND, and the drain is connected to the fifth node NET5. The input terminal of the inverter INV is connected to the fourth node NET4, and the output signal is the weight value DOUT and is divided into two routes, one of which is used to connect to the readout drive circuit, and the other is connected to the weight bit line WW.

Since the above (A) is the kth sense amplifier 1 and the kth voltage amplifier 1, P1~P8 are PL1[k]~PL8[k], and NM1~NM5 are NML1[k]~NML5[k] ], INV is INVL[k], NET1～NET is NETL1[k]～NETL5[k], SO is SOL[k], SOB is SOBL[k], I _CELL is I _CELL1 [k], I _REF is I _REF1 [k], DOUT is DOUTL[k] (that is, the kth weight value 1), and WW is LW[k].

(2) The k-th sense amplifier 2 is connected to the k-th column selector 2 . The k-th sense amplifier 2 includes the k-th current sampling unit 2 and the k-th voltage amplifier 2, which are used to sample and compare I _CELL2 [k] and I _REF2 [k], and output DOUTR[k].

Sensitive amplifier 2 includes current sampling unit 2 and voltage amplifier 2, used for sampling and comparing read current I _CELL2 of even storage sub-arrays and reference current I _REF2 of even reference arrays, and outputs weight value 2.

Similar to (A), the current sampling unit 2 and the current sampling unit 1 have the same configuration, and also include 6 PMOS transistors P1-P6, and 4 NMOS transistors NM1-NM4.

The composition of voltage amplifier 1 and voltage amplifier 2 is also the same, including 2 PMOS transistors P7-P8, 3 NMOS transistors NM5-NM7, and 1 inverter INV.

For the specific connection, refer to the introduction of (A), and Figure 7:

Since (B) is the kth sensitive amplifier 2 and the kth voltage amplifier 2, P1~P8 are PR1[k]~PR8[k], and NM1~NM5 are NMR1[k]~NMR5[k] , INV2 is INVR[k], NET1～NET5 is NETR1[k]～NETR5[k], SO is SOR[k], SOB is SOBR[k], I CELL is I CELL2 [k], I _CELL is I _CELL2 [k], I _REF is I _REF2 [k], DOUT is DOUTR[k] (that is, the kth weight value 2), and WW is RW[k].

For the output signal DOUTL/DOUTR, if the reference current is less than the bit line current, the output is low level 0; when the reference current is greater than the bit line current, the output is high level 1.

Referring to FIG. 8 , it is a transient simulation waveform diagram of a read operation according to an embodiment of the present invention, and is illustrated by referring to general parameters without serial numbers in (A) and (B):

The read operation process can be divided into two phases:

Pre-charging/pressure drop stabilization stage: the clamp signal CLP is enabled, at this time the clamp transistor between the bit line and the current source is turned on, the word line WL is turned on, and the current flows through the storage part and the reference part. When the MTJ1 in the memory cell is in a high resistance state, the reference current I _REF is greater than the bit line current I _CELL ; when the MTJ1 in the memory cell is in a low resistance state, the reference current I _REF is smaller than the bit line current I _CELL . The bit line current I _CELL is copied to the node SO through the current mirror formed by the PMOS transistors P2 and P3 , and the reference current IREF is copied to the node SOB through the current mirror formed by the PMOS transistors P4 and P5 . Therefore, the current difference between the storage part and the reference part is converted into a voltage difference between the node SO and the node SOB.

Sampling stage: When the stable voltage difference between the node SO and the node SOB is formed, the voltage amplifier enable signal SAE is turned on, the voltage difference between the node SO and the node SOB is multiplied, and the stored data is read out at the output terminal.

Certainly, the sense amplifier module is also connected with a read-out drive circuit, which is used to read the output weight value during the read operation in the standard read-write mode.

The mode selection module is used to switch the standard read-write mode and the multi-bit multiply-accumulate calculation mode of the storage array module.

As shown in Figure 3, the mode selection module selects a mode according to the external enable signal MEN.

When the external enable signal MEN is at a high level, that is, the weight bit line 1 LW[1]~LW[n], the weight bit line 2 RW[1]~RW[n] are not connected to the multi-bit operation module, and the memory array The module is in standard read and write mode.

When the external enable signal MEN is at low level, the memory array module is in the multi-bit multiplication and accumulation calculation mode, and the weight bit line 1 LW[1]~LW[n], the weight bit line 2 RW[1]~RW[n] and The multi-bit operation module is turned on, so that the k-th sense amplifier one is connected to the k-th cascade computing unit one, and the k-th sense amplifier two is connected to the k-th cascade computing unit two.

In the standard read-write mode and the multi-bit multiply-accumulate calculation mode, both the left sub-array and the right sub-array work in parallel. After the storage array module completes the standard read operation, the stored data is read out through the sense amplifier module, and the corresponding weight value one DOUTL and weight value two DOUTR are output, corresponding to 2-bit weights.

In the multi-bit multiplication and accumulation calculation mode, the 2-bit weight is divided into bits and transmitted to the cascaded calculation unit 1/2; the external 4-bit input is divided into two groups, which are respectively transmitted to the global bit line GBL/GBLB, represented by V _GBL / For the duration of the high level of V _GBLB , the calculation results correspond to the calculated voltage variation on the bit line CBL/CBLB respectively.

If the read weight value is "0", the calculation unit does not generate current, that is, the result of the multiplication operation is 0; if the read weight value is "1", the calculation of the bit line capacitance (C _CBL /C _CBLB ) starts The calculation unit is discharged, and the final multiplication and accumulation result corresponds to the discharge amount generated on the global bit line CBL/CBLB.

The quantization unit module is used to quantize the accumulated voltage variation of the calculated bit line CBL/CBLB in the multi-bit multiply-accumulate calculation mode to obtain a quantized output.

It should be noted that there are two quantization unit modules, one is connected to the calculation bit line CBL, which is used to quantify the voltage change of the calculation bit line CBL; the other is connected to the calculation bit line CBLB, and is used to quantify the calculation bit line CBL CBLB voltage change is quantified.

Referring to FIG. 10 , the two quantization unit modules have the same structure, and both include a capacitor array, a successive approximation logic control unit, and a voltage comparator.

The capacitor array includes five capacitors C0-C4, wherein the first capacitor is C0, the second capacitor is C1, the third capacitor is C2, the fourth capacitor is C3, and the fifth capacitor is C4. The relationship of the five capacitors is C4:C3:C2:C1:C0=8:4:2:1:1.

The upper plates of capacitors C0, C1, C2, C3, and C4 are all connected to the input node INP of the voltage comparator, and the lower plates of capacitors C0, C1, C2, C3, and C4 are controlled by switches S[0], S[ 1], S[2], S[3], S[4] are connected to the calculation bit line CBL or CBLB, the reference voltage VREF, and the power supply VDD.

The successive approximation logic control unit uses the successive approximation logic to generate the control signal S[4:0], which is used to control the capacitor array to generate the voltage comparator enable signal EN to control the voltage comparator.

The input node INN of the voltage comparator is connected to the common mode voltage VCM. When the control signal CE is turned on, the input nodes INP and INN are short-circuited, and the voltage comparator enable signal EN turns on the voltage comparator to compare the voltages of the input nodes INP and INN to generate an output Output.

For a single quantization unit module, it quantizes seven different multiply-accumulate results into 4-bit data (0-15), that is, the maximum quantization result MAC_MAX=15.

The quantization unit module performs standard dichotomy conversion. Referring to FIG. 10, for the quantization unit module 1 connected to the calculation bit line CBL, take multiply-accumulate MAC=9 as an example:

First, the control signal CE is turned on, the nodes INN and INP are short-circuited to the common-mode voltage VCM, and VCM corresponds to the quantized digital output 0.

After the capacitor array finishes sampling the analog voltage obtained by multiplying and accumulating the bit line CBL, the switch S[4:0] is switched to the power supply VDD, and the voltage of the node INP at this time is:

V _INP (0) = V _CM +V _DD -V _CBL ;

When the comparison phase starts, the successive approximation logic control unit controls the switch S[4], connects the lower plate of the fifth capacitor C4 to the reference voltage V _REF , and performs the first approximation (that is, 1 ^st VREF), and obtains the node INP The voltage is:

V _INP (1 ^st ) = V _CM -V _CBL +(V _REF +V _DD )/2;

The voltage of V _INP and V _INN is compared by the voltage comparator to obtain an output of 0, which is fed back to the successive approximation logic control unit, which controls the switch S[3] to connect the lower plate of the fourth capacitor C3 with the reference voltage V _REF is connected, and the second approximation (that is, ^2nd VREF) is performed, and the voltage of the node INP is obtained as:

V _INP (2 ^nd )＝V _CM -V _CBL +3*(V _REF +V _DD )/4;

The output 1 is obtained by comparing the voltages of V _INP and V _INN through the voltage comparator, which is fed back to the successive approximation logic control unit. The successive approximation logic control unit controls the switches S[3] and S[2]. The plate is switched to be connected to the power supply VDD, and the lower plate of the third capacitor C2 is connected to the reference voltage VREF, and the third approximation (ie 3 ^rd VREF) is performed, and the voltage of the node INP is obtained as:

V _INP (3 ^rd )＝V _CM -V _CBL +5*(V _REF +V _DD )/8;

The output 1 is obtained by comparing the voltages of V _INP and V _INN through the voltage comparator, which is fed back to the successive approximation logic control unit, which controls the switches S[2] and S[1], and converts the lower voltage of the third capacitor C2 to The plate is switched to be connected to the power supply VDD, the lower plate of the second capacitor C1 is connected to the reference voltage VREF, and the fourth approximation (that is, 4 ^th VREF) is performed, and the voltage of the node INP is obtained as:

V _INP (4 ^th )＝V _CM -V _CBL/CBLB +9*(V _REF +V _DD )/16;

At this time, the voltages of V _INP and V _INN are equal, and the quantization unit outputs a multiplication and accumulation calculation digital result MAC=9, which is the output of the first quantization unit module.

Similarly, for the quantization unit module 2 connected to the calculation bit line CBLB, take the multiply-accumulate MAC=9 as an example, the working process is similar to the above, and also output the multiply-accumulate calculation digital result MAC=9, which is the output of the quantization unit module 2.

The Output of the quantization unit module 1 and the output of the quantization unit module 2 are used to input into the digital combination circuit, and the weights are redistributed, so that a full-precision digital result output can be obtained after conversion by the digital combination circuit. Taking the above two Outputs as both MAC=9 as an example, the final full-precision output is FMAC=153 (“10011001”).

In addition, the work of the above-mentioned components is controlled by the timing control circuit module, which controls the timing of each part of the in-memory computing circuit structure to make them work correspondingly. Specifically, the timing control circuit controls the high-low level switching of each input signal and control signal.

Example 2

In this embodiment 2, when h is 2 in the embodiment 1, the specific simulation domain calculation process is explained in principle and proved by simulation.

Referring to Fig. 11 , it executes 2- Schematic diagram of bit input and 2-bit weight multiplication calculation results.

The specific simulation domain calculation process of W[1:0]×IN[3:2] is as follows:

When the weight W[1:0]=00, that is, the weight value LW[1] of the left storage array and the weight value RW[1] of the right storage array are both "0". What is the value (IN[3:2]=00, 01, 10, 11), the low-level cascaded calculation unit and the high-level cascaded calculation unit are not conducting, that is, no discharge current is generated on the calculated bit line CBL, and the bit line capacitance is calculated C _CBL has no discharge path; when the input IN[3:2]=00, that is, when V _GBL is always low in a calculation cycle, at this time, no matter how much the weight W[1:0] is (W[1: 0]=00, 01, 10, 11), the low-level cascaded calculation unit and the high-level cascaded calculation unit are not connected, that is, no discharge current is generated on the calculation bit line CBL, and there is no discharge path for the calculation bit line capacitance C _CBL ,

In the above seven cases in total, the bit line CBL produces a voltage change ΔV _CBL =0, namely: W[1:0]×IN[3:2]=00×00=00×01=00×10=00×11 =01×00=10×00=11×00=0.

即：

When W[1:0]=01, IN[3:2]=01, that is, RW[1]=0, LW[1]=1, the high level duration T _GBL of V _GBL in one calculation cycle is At time t, the high-order cascaded computing unit is not turned on, and the low-order cascaded computing unit is turned on to generate a current I, and the calculated bit line capacitance C _CBL starts to discharge the low-order cascaded computing unit, and the bit line CBL produces a voltage change

Right now:

即：

When W[1:0]=01, IN[3:2]=10, that is, RW[1]=1, LW[1]=0, the high level duration T _GBL of V _GBL in one calculation cycle is At 2t, the high-order cascaded computing unit is not turned on, and the low-order cascaded computing unit is turned on to generate a current I, that is, the current flowing through the computing bit line CBL is I, and the computing bit line capacitance C _CBL starts to discharge the low-order cascaded computing unit. The bit line CBL produces a voltage change

Right now:

即

When W[1:0]=01, IN[3:2]=11, that is, RW[1]=0, LW[1]=1, when V _GBL has a high level duration of 3t in one calculation cycle , the high-order cascaded computing unit is not turned on, and the low-order cascaded computing unit is turned on to generate a current I, that is, the current flowing through the computing bit line CBL is I, and the computing bit line capacitance C _CBL starts to discharge the low-order cascaded computing unit, and the bit line CBL produces a voltage change

Right now

即：

When W[1:0]=10, IN[3:2]=01, that is, RW[1]=1, LW[1]=0, the high level duration T _GBL of V _GBL in one calculation cycle is At time t, the lower cascaded computing unit is turned on, and the higher cascaded computing unit is turned on to generate a current of 2I, that is, the current flowing through the computing bit line CBL is 2I, and the computing bit line capacitance C _CBL starts to discharge the low cascaded computing unit, and the bit line line CBL produces a voltage change

Right now:

即：

When W[1:0]=10, IN[3:2]=10, that is, RW[1]=1, LW[1]=0, the high level duration T _GBL of V _GBL in one calculation cycle is At 2t, the low-order cascaded computing unit is turned on, and the high-order cascaded computing unit is turned on to generate a current of 2I. The calculated bit line capacitance C _CBL starts to discharge the low-order cascaded computing unit, and the bit line CBL produces a voltage change.

Right now:

即：

When W[1:0]=10, IN[3:2]=11, that is, RW[1]=1, LW[1]=0, the high level duration T _GBL of V _GBL in one calculation cycle is At 3t, the low-order cascaded computing unit is turned on, and the high-order cascaded computing unit is turned on to generate a current of 2I, that is, the current flowing through the computing bit line CBL is 2I, and the computing bit line capacitance C _CBL starts to discharge the low-order cascaded computing unit, and the bit line line CBL produces a voltage change

Right now:

即：

When W[1:0]=11, IN[3:2]=01, that is, RW[1]=1, LW[1]=1, the high level duration of VGBL in one calculation cycle T _GBL is t When , the low-order cascaded computing unit conducts to generate a current I and the high-order cascaded computing unit conducts to generate a current 2I, that is, the current flowing through the computing bit line CBL is 3I, and the computing bit line capacitance C _CBL starts to discharge the low-order cascaded computing unit , to calculate the voltage change of the bit line CBL

Right now:

即：

When W[1:0]=11, IN[3:2]=10, that is, RW[1]=1, LW[1]=1, the duration of V _GBL high level T _GBL is 2t in one calculation cycle When , the low-order cascaded computing unit conducts to generate a current I and the high-order cascaded computing unit conducts to generate a current 2I, that is, the current flowing through the computing bit line CBL is 3I, and the computing bit line capacitance C _CBL starts to discharge the low-order cascaded computing unit , to calculate the voltage change of the bit line CBL

Right now:

即：

When W[1:0]=11, IN[3:2]=11, that is, RW[1]=1, LW[1]=1, the high level duration T _GBL of VGBL in one calculation cycle is 3t When , the low-order cascaded computing unit is turned on to generate a current I and the high-order cascaded computing unit is turned on to generate a current 2I, that is, the current flowing through the computing bit line CBL is 2I, and the computing bit line capacitance C _CBL starts to discharge the low-bit cascaded computing unit , to calculate the voltage change of the bit line CBL

Right now:

The specific truth table is shown in Table 1:

Table 1 The truth table for the multi-bit multiplication and accumulation operation performed by the multi-bit operation module

From the above analysis, we can see that in the simulation domain,

It is easy to prove that when IN[3:2] are "00", "01", "10" and "11", the corresponding discharge times are "0t", "1t", "2t" and "3t".

In order to prove that when W[1:0] is "00", "01", "10" and "11" respectively, the corresponding calculation unit discharge currents are "0I", "1I", "2I", "3I" ", according to the equivalent circuit in Figure 6 for DC analysis:

When both N1[1] and N5[1] work in the saturation region, and N2[1] and N6[1] work in the deep linear region, an adjustable current source I can be made in series with an adjustable linear resistor R _on The equivalent analysis circuit of , here let the width-length ratio of N1[1] be (W/L) ₁ , the width-length ratio of N5[1] be 2(W/L) ₁ , N2[1], N6[1] The width-to-length ratio is (W/L) ₂ , the threshold voltage of N1[1] and N5[1] is V _TH1 , the threshold voltage of N2[1] and N6[1] is V _TH2 ; the voltage of LW[1] is V _LW1 , and the voltage of RW[1] is V _RW1 .

It should be noted that (W/L) ₁ and (W/L) ₂ represent two kinds of width-to-length ratios.

Before the calculation starts, the calculation bit line capacitance C _CBL is precharged to V _PRE . When both the high-order cascaded computing unit and the low-order cascaded computing unit are activated, the conduction current I ₁ of the low-order cascaded computing unit is:

Among them, μ _n and C _ox are process-related constants.

The conduction current I ₂ of the high-level cascaded computing unit is:

The adjustable linear resistance R _on is:

Among them, the voltage V _LX of the node LX (that is, X1[1]) is:

V _LX =I ₁ *R _on ; (7)

The voltage V _RX of node RX (that is, X3[1]) is:

V _RX =I ₂ *R _on ; (8)

When the resistance value of the adjustable linear resistor R _on is small enough, it can be considered that the impact of changes in V _LX and _VRX on I ₁ and I ₂ is negligible, that is, the conduction current of the low-order cascaded computing unit and the high-order cascaded computing unit Follow its width-to-length ratio linearly, that is:

The discharge current of a pair of cascaded computing units is equal to the sum of the current I ₂ of the high-order cascaded computing unit and the current I ₁ of the low-order cascaded computing unit. According to formulas (9), (10), and (11), it can be known that:

When W[1:0] are "00", "01", "10" and "11" respectively, the total discharge current is: 0*I ₁ +0*I ₂ =0, 1*I ₁ +0 *I ₂ =I ₁ , 0*I ₁ +1*I ₂ =I ₂ =2I ₁ , 1*I ₁ +1*I ₂ =3I ₁ .

And according to the linear capacitance VCR (Voltage Current Relation) relationship can be obtained:

That is, formulas (1), (2), and (3) are verified.

In addition, see Figure 12, Figure 13, and Figure 14 for Monte Carlo simulation proof diagrams of 2-bit input and 2-bit weight multiplication to calculate 7 kinds of discharge results. Figure 12 verifies W[1:0]×N[3:2 ]=10×01 and W[1:0]×N[3:2]=01×10, the discharge amount on the CBL is both 2ΔV, and the Gaussian distribution of the Monte Carlo simulation shows that the discharge operation is over The mean and standard deviation of the voltage on the posterior CBL are approximately equal. Similarly, Figure 13 verifies the calculations of W[1:0]×IN[3:2]=01×11 and W[1:0]×N[3:2]=11×01 on the CBL The discharge capacity is 3ΔV; Figure 14 verifies that the two calculation cases of W[1:0]×IN[3:2]=10×11 and W[1:0]×N[3:2]=11×10 are in The discharge capacity on the CBL is 6ΔV. It can be seen that the multi-bit multiplication and accumulation calculation performed by the multi-bit operation module in the analog domain is reliable.

In Embodiment 2, the power consumption and energy efficiency of the in-memory computing circuit system disclosed in Embodiment 1 are simulated as a function of the operating voltage. Referring to FIG. 15 , the abscissa is the operating voltage, the left ordinate represents power consumption, and the right ordinate represents energy efficiency. It can be seen from the figure that as the operating voltage decreases, the power consumption decreases and the energy efficiency improves. The minimum operating voltage of the circuit can reach 0.5V. Consumption and energy efficiency meet the requirements.

Example 3

This embodiment 3 considers a more general situation, that is, in order to verify the practicability of the design method: set the width-to-length ratio of N5[k] in the high-order cascaded computing unit to h of the width-to-length ratio of N1[k] in the low-order cascaded computing unit times, while other _conditions remain unchanged, the discharge current I h generated when the high-order cascaded computing unit is activated can be h times the discharge current I ₁ generated when the low-order cascaded computing unit is activated.

With reference to embodiment 2, formula (5), (8) are replaced with formula (13), (14):

The conduction current I _h of the high-level cascaded computing unit is:

The voltage V _RX of node RX (ie X3[k]) is:

V _RX =I _h *R _on (14)

Substituting formula (14) into formula (13) and substituting formula (7) into formula (4) at the same time, we can get:

make

Then rewrite formulas (15) and (16) to get:

can be transformed into a proof:

成立即可。That is to prove formula (18):

Just set up.

And according to L'Hopital's law:

That is, formula (18) is proved, so, I _h =I ₁ *h.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. multi-bit operation module, which is used to realize multi-bit multiplication and accumulation calculation, is characterized in that, described multi-bit operation module comprises: Bit division calculation module 1, which includes n cascaded calculation units 1, n weight bit lines 1 LW[1]～LW[n]; Wherein, the kth cascaded computing unit 1 includes: The gate of the NMOS transistor N1[k] is connected to the weight bit line LW[k], the drain is connected to the calculation bit line CBL, and the source is connected to the node X1[k]; NMOS transistor N2[k], its gate is connected to weight bit line one LW[k], its drain is connected to calculation bit line CBLB, and its source is connected to node two X2[k]; the specifications of N1[k] and N2[k] are the same ; NMOS transistor N3[k], its gate is connected to the global bit line GBL, its drain is connected to node X1[k], and its source is connected to ground GND; and NMOS transistor N4[k], its gate is connected to the global bit line GBLB, its drain is connected to node 2 X2[k], and its source is connected to ground GND; 1≤k≤n; Bit division calculation module 2, which includes n cascaded calculation unit 2, n even weight bit line 2 RW[1]～RW[n]; Among them, the kth cascaded computing unit 2 includes: NMOS transistor N5[k], its gate is connected to weight bit line two RW[k], its drain is connected to calculation bit line CBL, and its source is connected to node three X3[k]; NMOS transistor N6[k], its gate is connected to weight bit line 2 RW[k], its drain is connected to calculation bit line CBLB, and its source is connected to node 4 X4[k]; the specifications of N5[k] and N6[k] are the same ; NMOS transistor N7[k], its gate is connected to the global bit line GBL, its drain is connected to node 3 X3[k], and its source is connected to ground GND; and NMOS transistor N8[k], its gate is connected to the global bit line GBLB, its drain is connected to node 4 X4[k], and its source is connected to ground GND; N7[k], N8[k], N3[k], N4[k] ] have the same specifications, and the width-to-length ratio of N5[k] is h times the width-to-length ratio of N1[k]; Weight bit line 2 RW[k] and weight bit line 1 LW[k] are used to provide weight values; global bit lines GBL and GBLB are used to provide multi-bit input values; The multi-bit calculation module works in parallel from the sub-bit calculation module 1 and the sub-bit calculation module 2 gating columns, receives weight values and multi-bit input values, and performs multi-bit multiplication and accumulation calculations; calculates bit lines CBL and CBLB for passing voltage The amount of change reflects the multi-bit multiply-accumulate calculation result. 2. In-memory computing circuit structure, characterized in that it includes: A storage array module, which is used to provide a standard read-write mode and a multi-bit multiply-accumulate calculation mode; the storage array module includes a storage unit and a reference unit; A data selection module, which includes a column selection module and a row decoding module, is used to locate and access the corresponding storage unit in the storage unit according to the external address signal in the standard read-write mode; the column selection module is also connected with a write drive circuit , used to control writing to the storage unit; A sense amplifier module, which is used to compare the read current generated by the storage unit with the reference current of the reference unit to generate a conversion voltage, amplify the conversion voltage and obtain an output weight value; the sense amplifier module is also connected to a readout drive circuit, It is used to read the output weight value during the read operation of the standard read and write mode; A mode selection module, which is used to switch the standard read-write mode and the multi-bit multiplication and accumulation calculation mode of the storage array module; The multi-bit computing module as claimed in claim 1, under the multi-bit computing function mode, according to the weight value and the multi-bit input value, multi-bit multiplication and accumulation calculation is carried out; the multi-bit computing module is connected with an input register, which is used for Inputting multi-bit input values into the multi-bit computing module through global bit lines GBL and GBLB; A quantization unit module, which is used to quantify the accumulated voltage variation of the calculated bit lines CBL and CBLB in the multi-bit multiply-accumulate calculation mode to obtain a quantized output; and The timing control circuit module is used to control the timing of each part of the in-memory computing circuit structure to make it work correspondingly. 3. The in-memory computing circuit structure according to claim 2, wherein the storage unit comprises a left storage array and a right storage array; The left storage array includes N columns and M rows of storage cells; wherein, every j column constitutes a group of left sub-arrays, and the left storage array includes N/j groups of left sub-arrays, N=n*j; The right storage array also includes N columns and M rows of storage cells; wherein, every j column constitutes a set of right sub-arrays, and the right storage array includes N/j groups of right sub-arrays; The reference part includes a left reference array and a right reference array; the left reference array includes left reference units corresponding to N/j columns and M rows of the left storage array; wherein, the kth column left reference unit and the kth group left subarray Corresponding setting; 1≤k≤N/j; The right reference array includes right reference units corresponding to N/j columns and M rows of the right storage array; wherein, the kth column right reference unit is set correspondingly to the kth right subarray. 4. The in-memory computing circuit structure according to claim 3, wherein the storage unit comprises: The NMOS transistor M1 has its gate connected to the word line WL, and its drain connected to the source line SL; and A magnetic tunnel junction device MTJ1, one end of which is electrically connected to the bit line BL, and the other end is electrically connected to the source of M1; The left reference unit and the right reference unit have the same structure, including: The NMOS transistor M2 has its gate connected to the word line WL, and its drain connected to the reference source line; and A magnetic tunnel junction device MTJ2, one end of which is electrically connected to the reference bit line, and the other end is electrically connected to the source of M2; Memory cells, left reference cells, and right reference cells in the same row share the same word line WL; memory cells in the same column share the same bit line BL and the same source line SL; left reference cells in the same column share the same reference bit line, The same reference source line; the right reference cells in the same column share the same reference bit line and the same reference source line; The kth reference bit line of the left reference array is used to output the reference current I _REF1 [k], and the kth reference bit line of the right reference array is used to output the reference current I _REF2 [k]. 5. The computing circuit structure in memory according to claim 4, wherein the column selection module comprises n column selectors one and n column selectors two; n column selectors one and n column selectors Device two share the same addressing signal CS; Wherein, the k-th column selector 1 is set correspondingly to the k-th group left sub-array, and the k-th column selector 2 is set correspondingly to the k-th group right sub-array; The bit line BL of the left sub-array of the kth group is connected to the input terminal of the kth column selector 1, and the output terminal of the kth column selector 1 outputs the read current I _CELL1 [k]; The bit line BL of the right sub-array of the kth group is connected to the input terminal of the kth column selector 2, and the output terminal of the kth column selector 2 outputs the read current I _CELL2 [k]; The row decoding module is connected to the word line WL, and the M word lines WL share the same row decoding module. 6. The computing circuit structure in memory according to claim 5, wherein said sense amplifier module comprises n sense amplifiers one, n sense amplifiers two; The kth sense amplifier one is connected to the kth column selector one; the kth sense amplifier two is connected to the kth column selector two; The k-th sense amplifier 1 includes the k-th current sampling unit 1 and the k-th voltage amplifier 1, which are used to sample and compare I _CELL1 [k] and I _REF1 [k], and output DOUTL[k]; The k-th sense amplifier 2 includes the k-th current sampling unit 2 and the k-th voltage amplifier 2, which are used to sample and compare I _CELL2 [k] and I _REF2 [k], and output DOUTR[k]. 7. The computing circuit structure in memory according to claim 6, wherein the k-th current sampling unit 1 comprises: The gate of the PMOS transistor PL1[k] is connected to the external enable signal SAEN, the source is connected to the power supply VDD, and the drain is connected to the first node NETL1[k]; PMOS transistor PL2[k], its gate and drain are connected to the first node NETL1[k], and its source is connected to the power supply VDD; PMOS transistor PL3[k], its gate is connected to the first node NETL1[k], its source is connected to the power supply VDD, and its drain is connected to the first-stage output node SOL[k]; The gate of the PMOS transistor PL4[k] is connected to the second node NETL2[k], the source is connected to the power supply VDD, and the drain is connected to the first-stage output node SOBL[k]; PMOS transistor PL5[k], its gate and drain are connected to the second node NETL2[k], and its source is connected to the power supply VDD; PMOS transistor PL6[k], its gate is connected to the external enable signal SAEN, its source is connected to the power supply VDD, and its drain is connected to the second node NETL2[k]; The gate of the NMOS transistor NML1[k] is connected to the clamping signal CLP, the source is connected to the read current I _CELL1 [k], and the drain is connected to the first node NETL1[k]; The NMOS transistor NML2[k] has its gate connected to the first-stage output node SOBL[k], its source connected to the ground GND, and its drain connected to the first-stage output node SOL[k]; NMOS transistor NML3[k], its gate and drain are connected to the first-stage output node SOBL[k], and its source is connected to ground GND; and The gate of the NMOS transistor NML4[k] is connected to the clamping signal CLP, the source is connected to the reference current I _REF1 [k], and the drain is connected to the second node NETL2[k]; The kth voltage amplifier one includes: PMOS transistor PL7[k], its gate and drain are connected to the third node NETL3[k], and its source is connected to the power supply VDD; PMOS transistor PL8[k], its gate and drain are connected to the fourth node NETL4[k], and its source is connected to the power supply VDD; The NMOS transistor NML5[k] has its gate connected to the first-stage output node SOL[k], its source connected to the fifth node NETL5[k], and its drain connected to the third node NETL3[k]; The NMOS transistor NML6[k] has its gate connected to the first-stage output node SOBL[k], its source connected to the fifth node NETL5[k], and its drain connected to the fourth node NETL4[k]; The NMOS transistor NML7[k] has its gate connected to the external enable signal SAEN, its source connected to the ground GND, and its drain connected to the fifth node NETL5[k]; and Inverter INVL[k], its input terminal is connected to the fourth node NETL4[k], the output signal is a weight value DOUTL[k] and is divided into two routes, one of which is used to connect the readout drive circuit, and the other is connected to the weight bit Line-LW[k]. 8. The internal computing circuit structure according to claim 7, wherein the k-th current sampling unit two comprises: PMOS transistor PR1[k], its gate is connected to the external enable signal SAEN, its source is connected to the power supply VDD, and its drain is connected to the first node NETR1[k]; PMOS transistor PR2[k], its gate and drain are connected to the first node NETR1[k], and its source is connected to the power supply VDD; PMOS transistor PR3[k], its gate is connected to the first node NETR1[k], its source is connected to the power supply VDD, and its drain is connected to the first-stage output node SOR[k]; PMOS transistor PR4[k], its gate is connected to the second node NETR2[k], its source is connected to the power supply VDD, and its drain is connected to the first-stage output node SOBR[k]; PMOS transistor PR5[k], its gate and drain are connected to the second node NETR2[k], and its source is connected to the power supply VDD; PMOS transistor PR6[k], its gate is connected to the external enable signal SAEN, its source is connected to the power supply VDD, and its drain is connected to the second node NETR2[k]; The gate of the NMOS transistor NMR1[k] is connected to the clamping signal CLP, the source is connected to the read current I _CELL2 [k], and the drain is connected to the first node NETR1[k]; The NMOS transistor NMR2[k] has its gate connected to the first-stage output node SOBR[k], its source connected to the ground GND, and its drain connected to the first-stage output node SOR[k]; NMOS transistor NMR3[k], its gate and drain are connected to the first-stage output node SOBR[k], and its source is connected to ground GND; and The gate of the NMOS transistor NMR4[k] is connected to the clamping signal CLP, the source is connected to the reference current I _REF2 [k], and the drain is connected to the second node NETR2[k]; Described voltage amplifier two comprises: PMOS transistor PR8[k], its gate and drain are connected to the third node NETR3[k], and its source is connected to the power supply VDD; PMOS transistor PR9[k], its gate and drain are connected to the fourth node NETR4[k], and its source is connected to the power supply VDD; The NMOS transistor NMR5[k] has its gate connected to the first-stage output node SOR[k], its source connected to the fifth node NETR5[k], and its drain connected to the third node NETR3[k]; The NMOS transistor NMR6[k] has its gate connected to the first-stage output node SOBR[k], its source connected to the fifth node NETR5[k], and its drain connected to the fourth node NETR4[k]; The NMOS transistor NMR7[k] has its gate connected to the external enable signal SAEN, its source connected to the ground GND, and its drain connected to the fifth node NETR5[k]; Inverter INVR[k], whose input terminal is connected to the fourth node NETR4[k], the output signal is a weight value DOUTR[k] and is divided into two routes, one of which is used to connect the readout drive circuit, and the other is connected to the weight bit Line two RW[k]. 9. The internal computing circuit structure according to claim 7, wherein the mode selection module selects a mode according to an external enable signal MEN; When the external enable signal MEN is at a high level, the storage array module is in a standard read-write mode; When the external enable signal MEN is low level, the memory array module is in the multi-bit multiplication and accumulation calculation mode, the kth sense amplifier one is connected to the kth cascaded calculation unit one, and the kth sense amplifier two is connected to the kth sense amplifier Two cascaded computing units are connected. 10. The in-memory computing circuit structure according to claim 7, wherein the quantization unit module includes a capacitor array, a successive approximation logic control unit, and a voltage comparator; The capacitor array includes capacitors C0, C1, C2, C3, and C4, and the upper plates of the capacitors C0, C1, C2, C3, and C4 are all connected to the input node INP of the voltage comparator, and the capacitors C0, C1, C2, The lower plates of C3 and C4 are respectively connected to the calculation bit line CBL/CBLB, the reference voltage VREF, and the power supply VDD through the control switches S[0], S[1], S[2], S[3], and S[4] ; The successive approximation logic control unit adopts the successive approximation logic to generate the control signal S[4:0], which is used to control the capacitor array to generate the voltage comparator enable signal EN and then control the voltage comparator; The input node INN of the voltage comparator is connected to the common mode voltage VCM; when the control signal CE is turned on, the input nodes INP and INN are short-circuited, and the voltage comparator enable signal EN turns on the voltage comparator, and the voltage of the input nodes INP and INN Compare and generate output Output.

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