CN114698270B - Precision circuit packaging substrate based on surface protection and its processing technology - Google Patents
Precision circuit packaging substrate based on surface protection and its processing technology Download PDFInfo
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- CN114698270B CN114698270B CN202210325646.1A CN202210325646A CN114698270B CN 114698270 B CN114698270 B CN 114698270B CN 202210325646 A CN202210325646 A CN 202210325646A CN 114698270 B CN114698270 B CN 114698270B
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- 238000012545 processing Methods 0.000 title claims abstract description 28
- 238000005516 engineering process Methods 0.000 title claims abstract description 16
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 title description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 130
- 239000011889 copper foil Substances 0.000 claims abstract description 120
- 238000004519 manufacturing process Methods 0.000 claims abstract description 71
- 238000000034 method Methods 0.000 claims abstract description 71
- 238000005260 corrosion Methods 0.000 claims abstract description 42
- 230000007797 corrosion Effects 0.000 claims description 33
- 238000009713 electroplating Methods 0.000 claims description 23
- 238000005530 etching Methods 0.000 claims description 21
- 238000003801 milling Methods 0.000 claims description 20
- 238000003825 pressing Methods 0.000 claims description 18
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 17
- 239000003292 glue Substances 0.000 claims description 17
- 229910052802 copper Inorganic materials 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 238000004140 cleaning Methods 0.000 claims description 9
- 238000007788 roughening Methods 0.000 claims description 9
- 238000011068 loading method Methods 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 claims description 6
- 238000000576 coating method Methods 0.000 claims description 6
- 238000011049 filling Methods 0.000 claims description 6
- 238000002203 pretreatment Methods 0.000 claims description 6
- 238000005553 drilling Methods 0.000 claims description 5
- 238000011410 subtraction method Methods 0.000 claims description 5
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 229910000619 316 stainless steel Inorganic materials 0.000 claims description 3
- 229910001374 Invar Inorganic materials 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 239000012535 impurity Substances 0.000 claims description 3
- 238000007747 plating Methods 0.000 claims description 3
- 238000006116 polymerization reaction Methods 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 224
- 238000000465 moulding Methods 0.000 description 5
- 238000011161 development Methods 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000654 additive Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005429 filling process Methods 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4682—Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4673—Application methods or materials of intermediate insulating layers not specially adapted to any one of the previous methods of adding a circuit layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
本申请涉及一种基于表层保护的精密线路封装载板及其加工工艺，所述加工工艺包括如下步骤：载体件的制作、抗蚀层的制作、第一埋线层的制作和后制程制作，所述后制程制作包括增层制作、第二埋线层的制作、重复增层及埋线层制作、去除载体件和去除抗蚀层，得到单面埋线产品。本加工工艺中采用常规铜箔制作载体层，并在铜箔的表面形成一层抗蚀层，从而降低了材料制作成本，控制了埋线层线路咬蚀终点，进而保证了线路板面的平整度。
The present application relates to a precision circuit packaging carrier based on surface protection and its processing technology, the processing technology includes the following steps: the production of a carrier, the production of an anti-corrosion layer, the production of a first buried wire layer and post-process production, the post-process production includes the production of a layer increase, the production of a second buried wire layer, repeated layer increase and buried wire layer production, removal of the carrier and removal of the anti-corrosion layer, and obtaining a single-sided buried wire product. In this processing technology, conventional copper foil is used to make the carrier layer, and an anti-corrosion layer is formed on the surface of the copper foil, thereby reducing the material production cost, controlling the end point of the buried wire layer circuit bite, and thus ensuring the flatness of the circuit board surface.
Description
Technical Field
The application relates to a packaging loading plate, in particular to a precise circuit packaging loading plate based on surface protection and a processing technology thereof.
Background
Along with the development of electronic technology and the requirements of people on miniaturization and high precision of electronic products, the requirements on packaging substrates are higher and higher, the existing masking method (Tenting) process cannot meet the processing requirements of small line width, small line distance and high-density wiring products, so that the application requirements of semi-additive method, wire embedding and other processes are higher and higher, but in the existing single-sided wire embedding technology, a Carrier member (Carrier) adopts an ultrathin copper (such as copper foil with the thickness of 3-5 mu m) structure, the cost of the special material is higher, the manufacturing process is complex and complicated, the control on the biting amount is relatively strict when the bottom ultrathin copper is removed after the wire embedding product is separated, excessive line biting of a wire embedding layer is easily caused, and a relatively obvious difference exists between a copper surface and an insulating medium layer, so that the surface evenness of the whole board is reduced, and the popularization and application of the wire embedding process are greatly limited.
Content of the application
In order to overcome the defects, the application provides a processing technology of a precise circuit packaging loading board based on surface protection, wherein a carrier layer is manufactured by adopting a conventional copper foil in the processing technology, and a layer of corrosion resistant layer is formed on the surface of the copper foil, so that the manufacturing cost of the material is reduced, the line biting end point of a buried line layer is controlled, and the flatness of a circuit board surface is further ensured.
The technical scheme adopted by the application for solving the technical problems is as follows:
a processing technology of a precise circuit packaging loading plate based on surface protection comprises the following steps:
Preparing two conventional copper foils, and adhering the two copper foils together through glue to form a carrier, namely, the carrier comprises a first copper foil layer and a second copper foil layer, wherein the surfaces of the two outer sides of the carrier are defined as outer surfaces, the surfaces of the two inner sides of the carrier are defined as inner surfaces, and the two inner surfaces are adhered together;
Step 2, manufacturing a corrosion resistant layer, namely plating a layer of tin on at least one outer surface of the carrier piece to form the corrosion resistant layer, forming a bare pattern circuit area on the corrosion resistant layer, and covering a photosensitive layer on a non-pattern circuit area on the outer surface of the carrier piece;
and 3, manufacturing a first buried line layer:
3.1 electroplating, namely manufacturing an embedded first buried line layer on the exposed pattern line area on the resist layer of the carrier by adopting an electroplating mode;
Removing the film, namely removing the photosensitive layer by removing the film from the electroplated product, and exposing the pattern circuit and the spacing space thereof;
Step 4, post process manufacturing
4.1, Layer adding manufacturing, namely filling an insulating medium on the first buried line layer to form an insulating medium layer;
4.2, manufacturing a second buried line layer:
① Processing blind holes, namely processing blind holes in the insulating medium layer;
② Seed layer manufacturing, namely manufacturing a seed layer on the surface of the insulating medium layer and the blind holes;
③ Manufacturing a pattern circuit, namely manufacturing a second buried line layer on the seed layer;
4.3 repeating the steps 4.1 and 4.2 until an n-layer plate is formed, wherein n is more than or equal to 2, n is a natural number, and the outermost layer of the product is an outer pattern circuit layer;
4.4 removing the carrier piece, namely separating the first copper foil layer from the second copper foil layer, and removing the first copper foil layer or the second copper foil layer in an etching mode to obtain a product with a corrosion-resistant layer;
and 4.5, removing the anti-corrosion layer, namely removing the anti-corrosion layer in the product by using tin stripping liquid to obtain the product with the buried line layer on one side.
Preferably, in the step 1, a frame is also prepared, the first copper foil layer and the second copper foil layer are adhered together through the frame, specifically, glue is coated on the upper surface and the lower surface of the frame at the temperature of 80-120 ℃, then two copper foils are respectively adhered on the upper surface and the lower surface of the frame, so that a carrier piece is formed, the frame is of an annular structure with a hollow inside, the width of the frame is 5-15 mm, the frame is made of 316 stainless steel or invar alloy, the thermal expansion coefficient of the frame is less than or equal to 12ppm/° C, the thickness of a conventional copper foil is 17.5 mu m, 35 mu m or 50 mu m, and the thermal expansion coefficient of the conventional copper foil is 16-18 ppm/° C.
Preferably, in the step1, a layer of glue is uniformly coated on the periphery of one copper foil near the edge area, then the other Zhang Tongbo is aligned and attached to the surface of the copper foil coated with the glue, and the copper foil is flattened, baked and solidified to form the carrier member.
Preferably, the step 4.4 specifically includes the following processes:
① Edge milling, namely edge milling along the position 2-5mm away from the inner side of the frame to separate the first copper foil layer from the second copper foil layer;
② Frame treatment, namely etching, removing residual glue and removing impurities from the frame subjected to edge milling treatment to obtain a reusable frame;
③ And removing the copper foil layer, namely removing the first copper foil layer or the second copper foil layer by means of alkaline etching.
Preferably, the step 4.4 specifically includes the following processes:
① Edge milling, namely edge milling along the position 2-5mm away from the inner side of the joint of the first copper foil layer and the second copper foil layer, and separating the first copper foil layer from the second copper foil layer;
② And removing the copper foil layer, namely removing the first copper foil layer or the second copper foil layer by means of alkaline etching.
Preferably, the step 2 specifically includes the following processes:
① Pre-treatment, namely cleaning and roughening the outer surface of the carrier piece;
② The manufacturing of a corrosion resistant layer, namely, the whole surface of the outer surface of the carrier piece is tinned to form the corrosion resistant layer, and the thickness of the corrosion resistant layer is controlled to be 0.5-2.0 mu m;
③ And (3) manufacturing a pattern circuit area, namely exposing the pattern circuit area to be manufactured in a mode of film pressing, exposure and development, wherein a non-pattern circuit area is covered with an electroplating-resistant photosensitive layer.
Preferably, the step 2 specifically includes the following processes:
① Pre-treatment, namely cleaning and roughening the outer surface of the carrier piece;
② The method comprises the steps of manufacturing a pattern circuit area, namely exposing the pattern circuit area to be manufactured in a film pressing, exposing and developing mode, and covering an electroplating-resistant photosensitive layer on a non-pattern circuit area;
③ And (3) preparing a corrosion resistant layer, namely preparing the surface of the exposed pattern circuit area by tinning, wherein the thickness of the corrosion resistant layer is controlled to be 0.5-2.0 mu m.
Preferably, the manufacturing of the graphic circuit area specifically comprises the following processes:
① Film pressing, namely manufacturing a photosensitive layer, and uniformly coating a photosensitive layer on the outer surface of the carrier piece in a pressing or coating mode;
② Exposing, namely enabling light and a photosensitive layer to perform polymerization reaction in an image transfer mode to form a pattern which cannot be removed by a developing solution but can be removed by a film removing solution;
③ And developing, namely removing the photosensitive layer in the unreacted area, and reserving the area where photopolymerization reaction occurs, namely exposing the pattern circuit area 18 to be manufactured, wherein the non-pattern circuit area covers the electroplating-resistant photosensitive layer 15.
Preferably, the step 4.1 specifically includes the following processes:
① Pre-treatment, namely cleaning and roughening the surface of the pattern circuit layer to increase the binding force between the circuit and the insulating medium and improve the product performance;
② Filling an insulating medium, namely forming an insulating medium layer on the pattern circuit layer through a pressing or vacuum pressing matching baking process;
In the step (4.2) ①, blind holes are manufactured by adopting laser windowing and laser drilling processes, the alignment reference is a target hole taking an inner layer target as a reference in the manufacturing process, or blind holes are manufactured by adopting a laser direct blind hole forming process, the alignment reference is an inner layer target in the manufacturing process, in the step (4.2) ②, a seed layer is manufactured by adopting a copper deposition process or a sputtering process, and in the step (4.2) ③, the pattern build-up manufacturing is performed by adopting an addition method and a pattern electroplating or subtraction method and a whole plate electroplating and etching process according to the pattern wiring density.
The invention also provides a precise circuit packaging loading plate based on surface protection, which is processed by adopting the processing technology.
The beneficial effects of the application are as follows:
1) Compared with the prior art, the application adopts the conventional copper foil to replace the ultrathin copper with higher cost, the material cost is greatly reduced, the adopted frame can be reused, the overall cost is very low, and the copper foil layer in the carrier piece is in a tight state by utilizing the difference between the thermal expansion coefficients of the frame and the copper foil, so that the quality of the carrier piece is improved, and the yield of product manufacture is improved;
2) In the processing process, a whole plate tinning scheme or a pattern tinning method can be flexibly selected by combining product grade requirements and cost factors, the whole plate tinning scheme is adopted, the buried line layer and the insulating layer are on the same horizontal line after tin stripping, the height difference between the buried line layer and the insulating layer after tin stripping can be controlled to be less than or equal to 2 mu m, so that the buried line layer circuit is protected by the tin layer, the buried line layer cannot be attacked by tin when carrier copper foil is removed, the height difference between a copper surface and a base material can be controlled, the flatness of the whole plate surface is ensured, the buried line layer circuit is protected by the tin layer, the process flow is simple, and the process cost is low;
3) The processing technology is suitable for double-sided boards and multi-layer boards, can meet the design requirement of 8/8um of minimum line width/line distance, can process double sides on a carrier in the processing process, and improves the production efficiency of products.
Drawings
FIG. 1 is a schematic view of a structure of the present application without a frame carrier member;
FIG. 2 is a schematic view of the structure of a frame-containing carrier member of the present application;
FIG. 3 is a schematic view of the structure of the carrier member after the entire plate is electroplated with a tin layer in accordance with the present application;
FIG. 4 is a schematic view of the structure of the carrier member after the photosensitive layer is attached;
FIG. 5 is a schematic view of a structure of a carrier member according to the present application after a first buried line layer is formed;
FIG. 6 is a schematic view of the structure of the carrier member of the present application with the photosensitive layer removed;
FIG. 7 is a schematic view of an n-layer structure according to the present application;
FIG. 8 is a schematic view of the structure of the n-layer carrier removing member of the present application;
FIG. 9 is a schematic view of the structure of the n-layer copper foil removed layer according to the present application;
FIG. 10 is a schematic view of the structure of the n-layer plate after resist removal in the present application;
in the figure, 10-carrier, 11-first copper foil layer, 12-second copper foil, 13-frame, 14-resist layer, 15-photosensitive layer, 16-first buried line layer, 17-insulating dielectric layer, 18-pattern line region, 21-second buried line layer, and 22-outer pattern line layer.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the following figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be capable of being practiced otherwise than as specifically shown or described. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The embodiment of the method is characterized by comprising the following steps of:
preparing two conventional copper foils as shown in fig. 1 or 2, and adhering the two copper foils together through glue to form a carrier member 10, namely, the carrier member 10 comprises a first copper foil layer 11 and a second copper foil layer 12, wherein the surfaces on two outer sides of the carrier member 10 are defined as outer surfaces, the surfaces on two inner sides of the carrier member 10 are defined as inner surfaces, and the two inner surfaces are adhered together;
Step 2, manufacturing a corrosion resistant layer 14, namely plating a layer of tin on at least one outer surface of the carrier member 10 to form the corrosion resistant layer 14, forming a bare pattern circuit area 18 on the corrosion resistant layer 14, and covering a photosensitive layer 15 on a non-pattern circuit area on the outer surface of the carrier member 10, as shown in fig. 4, wherein the corrosion resistant layer 14 is a tin layer, and manufacturing a circuit on any unexpected surface of the carrier member 10 is single-sided processing, or simultaneously manufacturing circuits on two outer surfaces to perform double-sided processing, thereby improving the manufacturing efficiency of the carrier plate;
step 3, the first buried line layer 16 is manufactured, namely the surface layer embedded line is manufactured,
3.1 Electroplating, as shown in FIG. 5, an embedded first buried line layer 16 is manufactured on the exposed pattern line area 18 on the resist layer 14 of the carrier member in an electroplating manner;
3.2 removing film, as shown in figure 6, removing film from the electroplated product to remove photosensitive layer 15, exposing pattern circuit and its spacing space;
Step 4, post process manufacturing
4.1, Layer adding and manufacturing, namely filling an insulating medium on the first buried line layer 16 to form an insulating medium layer 17;
4.2 manufacturing of the second buried line layer 21:
① Processing blind holes, namely processing blind holes in the insulating medium layer 17;
② Seed layer manufacturing, namely manufacturing a seed layer on the surface of the insulating medium layer 17 and the blind holes;
③ Manufacturing a pattern line, namely manufacturing a second buried line layer 21 on the seed layer;
4.3 repeating the steps 4.1 and 4.2 until n-layer plates are formed, wherein n is more than or equal to 2, n is a natural number, and the outermost layer of the product is an outer pattern circuit layer 22, namely, repeatedly filling the preparation of the insulating medium and the pattern circuit layer, adding one layer of plate every time the steps 4.1 and 4.2 are repeated, forming a double-layer plate when the repetition number is 0, forming a multi-layer plate when the repetition number is more than or equal to 1, and omitting the third buried line layer to the n-1 buried line layer and the insulating medium layer between the third buried line layer and the n-1 buried line layer in the diagram as shown in FIG. 7;
4.4 removing the carrier member 10, as shown in FIG. 8, firstly separating the first copper foil layer 11 from the second copper foil layer 12, then removing the first copper foil layer 11 or the second copper foil layer 12 by etching to obtain a product with a corrosion resistant layer 14, as shown in FIG. 9, when a single side is manufactured, if a circuit is manufactured on the outer surface of the first copper foil layer, after the carrier member 10 is separated, removing the second copper foil layer 12, and then etching the first copper foil layer 11 to obtain a plate with a corrosion resistant layer, when a double side is manufactured, the circuit is manufactured on the first copper foil layer and the second copper foil layer, after the carrier member 10 is separated, two plates are obtained, and then the first copper foil layer or the second copper foil layer is etched to obtain two plates with corrosion resistant layers;
4.5 removing the resist layer 14 As shown in FIG. 10, the resist layer 14 in the product was removed by using a stripping tin solution to obtain a product having a buried line layer on one side. The tin stripping liquid can not attack the copper layer of the circuit, can effectively control the height difference between the embedded circuit layer and the insulating medium layer in the surface layer, and is manufactured into the following working procedures of welding prevention, surface treatment, forming, finished product testing, finished product inspection, packaging and shipment according to the design requirement of the product, so that a finished product plate is formed, and the final finished product is the packaging carrier plate.
In one embodiment, in the step 1, a frame 13 is further prepared, the first copper foil layer 11 and the second copper foil layer 12 are adhered together through the frame 13, specifically, glue is coated on the upper surface and the lower surface of the frame 13 at the temperature of 80-120 ℃, then two copper foils are respectively adhered on the upper surface and the lower surface of the frame to form the carrier member 10, the frame 13 is of an annular structure with a hollow inside, the width of the frame is 5-15 mm, the frame is made of 316 stainless steel or invar alloy, the thermal expansion coefficient of the frame is less than or equal to 12ppm/° C, the thickness of a conventional copper foil is 17.5 μm, 35 μm or 50 μm, and the thermal expansion coefficient of the conventional copper foil is 16-18 ppm/° C. As shown in fig. 2, the carrier member 10 is composed of a first copper foil layer 11, a frame 13 and a second copper foil layer 12, preferably, the conventional copper foil has a thickness of 17.5 μm or 35 μm, and when the temperature is restored to room temperature, the copper foil is cooled to room temperature due to larger CTE, so that the copper foil is in a tight state, the quality of the carrier member is improved, the manufacturing yield of the product is improved, and the carrier member can be manufactured in a single-sided or double-sided manner.
In another embodiment, the step 1 specifically includes uniformly coating a layer of glue on the periphery of one copper foil near the edge area, then attaching another Zhang Tongbo to the surface of the copper foil coated with glue in alignment, flattening, and baking to cure to form the carrier member 10. As shown in fig. 1, the carrier member 10 is composed of a first copper foil layer 11 and a second copper foil layer 12, and two copper foils are bonded to each other only near the edge area by glue so as to facilitate subsequent board separation, preferably, glue is applied in a range of about 10mm near the edge of the copper foil, and the conventional copper foil has a thickness of 17.5 μm or 35 μm.
When the carrier member 10 is composed of the first copper foil layer 11, the frame 13 and the second copper foil layer 12, the above step 4.4 specifically includes the following processes:
① Edge milling, namely, edge milling is carried out along the position 2-5mm away from the inner side of the frame 13 to separate the first copper foil layer from the second copper foil layer, namely, the frame part is removed through edge milling, if double-sided molding is carried out, the edge is separated into two plates, namely, two products, if single-sided molding is carried out, and the edge is separated into one plate and one copper foil after edge milling;
② The frame treatment, namely etching, removing residual glue and impurities from the frame 13 subjected to edge milling treatment to obtain a reusable frame 13;
③ And removing the copper foil layer, namely removing the first copper foil layer or the second copper foil layer by means of alkaline etching. In the process, the etching liquid cannot attack the tin layer, so that the etching liquid is effectively prevented from attacking the surface embedded circuit.
When the carrier member 10 is composed of the first copper foil layer 11 and the second copper foil layer 12, the above step 4.4 specifically includes the following processes:
① Edge milling, namely edge milling is carried out along the position 2-5mm away from the inner side of the joint of the first copper foil layer 11 and the second copper foil layer 12, and the first copper foil layer 11 and the second copper foil layer 12 are separated, namely the joint of the first copper foil layer 11 and the second copper foil layer 12 is removed through edge milling, if the double-sided molding is carried out, the edge milling is carried out, then the two plates, namely two products, are separated, if the single-sided molding is carried out, and if the single-sided molding is carried out, the edge milling is carried out, then the two plates and the copper foil are separated;
② And removing the copper foil layer, namely removing the first copper foil layer or the second copper foil layer by means of alkaline etching. In the process, the etching liquid cannot attack the tin layer, so that the etching liquid is effectively prevented from attacking the surface layer embedded circuit.
In one embodiment, the step 2 specifically includes the following processes:
① Pretreatment, namely cleaning and roughening the outer surface of the carrier member 10;
② The preparation of a corrosion resistant layer, namely, carrying out tinning on the whole surface of the outer surface of the carrier member 10 to prepare a corrosion resistant layer 14, wherein the thickness of the corrosion resistant layer 14 is controlled to be 0.5-2.0 mu m;
③ And (3) manufacturing a pattern circuit area, namely exposing the pattern circuit area 18 to be manufactured by means of film pressing, exposure and development, wherein a non-pattern circuit area covers the electroplating-resistant photosensitive layer 15. As shown in fig. 3, the scheme is that the whole plate is plated with tin, the photosensitive layer is pressed on the surface of the anti-corrosion layer, and when the anti-corrosion layer is finally removed, the first buried line layer and the first insulating medium layer are on the same horizontal line, so that the flatness is very good.
In another embodiment, the step 2 specifically includes the following processes:
① Pretreatment, namely cleaning and roughening the outer surface of the carrier member 10;
② The pattern circuit area is manufactured, namely the pattern circuit area 18 to be manufactured is exposed through the modes of film pressing, exposure and development, and the non-pattern circuit area is covered with the electroplating-resistant photosensitive layer 15;
③ And (3) preparing a corrosion resistant layer, namely preparing the surface of the exposed pattern circuit area by tinning to form a corrosion resistant layer 14, wherein the thickness of the corrosion resistant layer is controlled to be 0.5-2.0 mu m, and as shown in figure 3, the scheme is that pattern electrotinning is carried out, namely, a photosensitive layer is directly pressed on the outer surface of a carrier piece, the pattern circuit area is only tinned, when the corrosion resistant layer is finally removed, a first buried line layer is recessed in a first insulating medium layer, and the height difference between the first buried line layer and the first insulating medium layer is controlled to be less than or equal to 2.0 mu m.
The manufacturing of the graph circuit area specifically comprises the following processes:
① The film pressing step, namely, a photosensitive layer 15 is manufactured, and a layer of photosensitive layer 15 is uniformly coated on the outer surface of the carrier member 10 in a pressing or coating mode;
② Exposing, namely enabling light and a photosensitive layer to perform polymerization reaction in an image transfer mode to form a pattern which cannot be removed by a developing solution but can be removed by a film removing solution;
③ And developing, namely removing the photosensitive layer in the unreacted area, and reserving the area where photopolymerization reaction occurs, namely exposing the pattern circuit area 18 to be manufactured, wherein the non-pattern circuit area covers the electroplating-resistant photosensitive layer 15.
The step 4.1 specifically comprises the following processes:
① The method comprises the steps of preprocessing, namely cleaning and roughening the surface of a pattern circuit layer to increase the binding force of a circuit and an insulating medium and improve the performance of a product, wherein the pattern circuit layer is a first buried layer, a second buried layer and a third buried layer, if a final carrier plate is a three-layer plate, the pattern circuit layer is a first buried layer and a second buried layer, if the final carrier plate is a four-layer plate, the pattern circuit is a first buried layer, a second buried layer and a third buried layer, and the like.
② The insulating medium is filled, namely, the insulating medium layer 17 is formed on the pattern circuit layer through a pressing or vacuum pressing and baking process, and the insulating medium filling process is not limited to the two modes, so long as the processing characteristics of the insulating medium are matched.
In the step (4.2) ①, blind holes are manufactured by adopting laser windowing and laser drilling processes, the alignment reference is a target hole taking an inner layer target as a reference in the manufacturing process, or blind holes are manufactured by adopting a laser direct blind hole forming process, the alignment reference is an inner layer target in the manufacturing process, in the step (4.2) ②, a seed layer is manufactured by adopting a copper deposition process or a sputtering process, and in the step (4.2) ③, the pattern build-up manufacturing is performed by adopting an addition method and a pattern electroplating or subtraction method and a whole plate electroplating and etching process according to the pattern wiring density. Of course, the blind hole processing mode is not limited to the laser windowing and laser drilling process or LDD (LASER DIRECT DRILLING, laser directly forming blind holes), the seed layer manufacturing is not limited to the copper deposition process and the sputtering process, the equivalent conducting function can be realized, the pattern wiring is not limited to the addition method or the subtraction method, and the pattern manufacturing can be realized, wherein the addition method, the pattern electroplating, the half-addition method, the subtraction method, the whole plate electroplating and the etching are all conventional processes in the field, and are not described in detail herein.
As shown in fig. 10, the above processing process is adopted to obtain a precision circuit package carrier board based on surface protection.
It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (7)
1. A processing technology of a precise circuit packaging loading board based on surface protection is characterized by comprising the following steps:
preparing two conventional copper foils, and adhering the two copper foils together through glue to form a carrier (10), namely, the carrier (10) comprises a first copper foil layer (11) and a second copper foil layer (12), wherein the surfaces of the two outer sides of the carrier (10) are defined as outer surfaces, the surfaces of the two inner sides of the carrier (10) are defined as inner surfaces, and the two inner surfaces are adhered together;
step 2, manufacturing a corrosion resistant layer (14), namely plating a layer of tin on at least one outer surface of the carrier member (10) to form the corrosion resistant layer (14), and forming a bare pattern circuit area (18) on the corrosion resistant layer (14), wherein a photosensitive layer (15) is covered on a non-pattern circuit area on the outer surface of the carrier member (10);
step 3, manufacturing a first buried line layer (16):
3.1 electroplating, namely manufacturing an embedded first buried line layer (16) on the exposed pattern line area (18) on the resist layer (14) of the carrier by adopting an electroplating mode;
Removing the film, namely removing the photosensitive layer (15) by removing the film from the electroplated product, and exposing the pattern circuit and the interval space thereof;
Step 4, post process manufacturing
4.1, Layer adding manufacturing, namely filling an insulating medium on the first buried line layer (16) to form an insulating medium layer (17);
4.2 manufacturing a second buried line layer (21):
① Processing blind holes, namely processing blind holes in the insulating medium layer (17);
② The seed layer is manufactured, namely, the seed layer is manufactured on the surface of the insulating medium layer (17) and the blind holes;
③ Manufacturing a pattern line, namely manufacturing a second buried line layer (21) on the seed layer;
4.3 repeating the steps 4.1 and 4.2 until an n-layer plate is formed, wherein n is more than or equal to 2, n is a natural number, and the outermost layer of the product is an outer pattern circuit layer (22);
4.4 removing the carrier member (10) by first separating the first copper foil layer (11) from the second copper foil layer (12) and then removing the first copper foil layer (11) or the second copper foil layer (12) by etching to obtain a product having a resist layer (14);
4.5 removing the anti-corrosion layer (14), namely removing the anti-corrosion layer (14) in the product by using tin stripping liquid to obtain a product with a buried line layer on one side;
the step 2 specifically comprises the following processes:
① Pre-treatment, namely cleaning and roughening the outer surface of the carrier member (10);
② The method comprises the steps of manufacturing a pattern circuit area, namely exposing the pattern circuit area (18) to be manufactured in a film pressing, exposing and developing mode, and covering an electroplating-resistant photosensitive layer (15) on a non-pattern circuit area;
③ The manufacturing of a corrosion resistant layer, namely, the surface of the exposed pattern circuit area is subjected to tinning to form a corrosion resistant layer (14), and the thickness of the corrosion resistant layer is controlled to be 0.5-2.0 mu m;
The manufacturing of the graph circuit area specifically comprises the following processes:
① Film pressing, namely manufacturing a photosensitive layer (15), and uniformly coating a photosensitive layer (15) on the outer surface of the carrier member (10) in a pressing or coating mode;
② Exposing, namely enabling light and a photosensitive layer to perform polymerization reaction in an image transfer mode to form a pattern which cannot be removed by a developing solution but can be removed by a film removing solution;
③ Removing the photosensitive layer in the unreacted area, reserving the area with photopolymerization reaction, namely exposing the pattern circuit area (18) to be manufactured, and covering the electroplating-resistant photosensitive layer (15) in the non-pattern circuit area;
the step 4.1 specifically comprises the following processes:
① Pre-treatment, namely cleaning and roughening the surface of the pattern circuit layer to increase the binding force between the circuit and the insulating medium and improve the product performance;
② Filling an insulating medium, namely forming an insulating medium layer (17) on the pattern circuit layer through a pressing or vacuum pressing matching baking process;
In the step (4.2) ①, blind holes are manufactured by adopting laser windowing and laser drilling processes, the alignment reference is a target hole taking an inner layer target as a reference in the manufacturing process, or blind holes are manufactured by adopting a laser direct blind hole forming process, the alignment reference is an inner layer target in the manufacturing process, in the step (4.2) ②, a seed layer is manufactured by adopting a copper deposition process or a sputtering process, and in the step (4.2) ③, the pattern build-up manufacturing is performed by adopting an addition method and a pattern electroplating or subtraction method and a whole plate electroplating and etching process according to the pattern wiring density.
2. The processing technology of the precise circuit packaging carrier board based on surface protection of claim 1 is characterized in that in the step 1, a frame (13) is also prepared, the first copper foil layer (11) and the second copper foil layer (12) are adhered together through the frame (13), specifically, glue is coated on the upper surface and the lower surface of the frame (13) at the temperature of 80-120 ℃, then two copper foils are respectively adhered on the upper surface and the lower surface of the frame to form a carrier piece (10), the frame (13) is of an annular structure with a hollow inside, the width of the frame is 5-15 mm, the frame is made of 316 stainless steel or invar alloy, the thermal expansion coefficient of the frame is less than or equal to 12ppm/°c, the thickness of a conventional copper foil is 17.5 μm, 35 μm or 50 μm, and the thermal expansion coefficient of the conventional copper foil is 16-18 ppm/°c.
3. The process for manufacturing the precise circuit packaging carrier board based on surface protection as claimed in claim 1, wherein the step 1 is specifically that after a layer of glue is uniformly coated on the periphery of one copper foil near the edge area, the other copper foil Zhang Tongbo is attached to the surface of the copper foil coated with the glue in an aligned manner, and the carrier piece (10) is formed by baking and curing after flattening.
4. The process for manufacturing a surface protection-based precision circuit package carrier plate according to claim 2, wherein the step 4.4 comprises the following steps:
① Edge milling, namely edge milling along the position 2-5mm away from the inner side of the frame (13) to separate the first copper foil layer from the second copper foil layer;
② Frame treatment, namely etching, removing residual glue and removing impurities from the frame (13) subjected to edge milling treatment to obtain a reusable frame (13);
③ And removing the copper foil layer, namely removing the first copper foil layer or the second copper foil layer by means of alkaline etching.
5. The process for manufacturing a surface protection-based precision circuit package carrier plate according to claim 3, wherein the step 4.4 comprises the following steps:
① Edge milling, namely edge milling along the position 2-5mm away from the inner side of the joint of the first copper foil layer (11) and the second copper foil layer (12), so as to separate the first copper foil layer (11) from the second copper foil layer (12);
② And removing the copper foil layer, namely removing the first copper foil layer or the second copper foil layer by means of alkaline etching.
6. The process for manufacturing a surface protection-based precision circuit package carrier board according to claim 1, wherein the step 2 comprises the following steps:
① Pre-treatment, namely cleaning and roughening the outer surface of the carrier member (10);
② The manufacturing of a corrosion resistant layer, namely, the whole surface of the outer surface of a carrier (10) is tinned to form a corrosion resistant layer (14), and the thickness of the corrosion resistant layer (14) is controlled to be 0.5-2.0 mu m;
③ And (3) manufacturing a pattern circuit area, namely exposing the pattern circuit area (18) to be manufactured through a film pressing, exposing and developing mode, and covering the non-pattern circuit area with an electroplating-resistant photosensitive layer (15).
7. A precise circuit packaging loading board based on surface protection is characterized by being processed by adopting the processing technology of any one of claims 1-6.
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| CN104902696A (en) * | 2015-06-24 | 2015-09-09 | 上海美维科技有限公司 | Method of manufacturing copper column on printed circuit board based on wire embedding structure |
| CN105451430A (en) * | 2014-09-02 | 2016-03-30 | 富葵精密组件(深圳)有限公司 | Partially-embedded type circuit structure and manufacturing method thereof |
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| US4489364A (en) * | 1981-12-31 | 1984-12-18 | International Business Machines Corporation | Chip carrier with embedded engineering change lines with severable periodically spaced bridging connectors on the chip supporting surface |
| US4652974A (en) * | 1985-10-28 | 1987-03-24 | International Business Machines Corporation | Method and structure for effecting engineering changes in a multiple device module package |
| CN107241875B (en) * | 2016-03-28 | 2019-05-07 | 上海美维科技有限公司 | A kind of manufacturing method of two-sided printed board of sunkening cord |
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| CN105451430A (en) * | 2014-09-02 | 2016-03-30 | 富葵精密组件(深圳)有限公司 | Partially-embedded type circuit structure and manufacturing method thereof |
| CN104902696A (en) * | 2015-06-24 | 2015-09-09 | 上海美维科技有限公司 | Method of manufacturing copper column on printed circuit board based on wire embedding structure |
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