CN114698257B - Package substrate with fully embedded precision circuits and its processing technology - Google Patents
Package substrate with fully embedded precision circuits and its processing technology Download PDFInfo
- Publication number
- CN114698257B CN114698257B CN202210300495.4A CN202210300495A CN114698257B CN 114698257 B CN114698257 B CN 114698257B CN 202210300495 A CN202210300495 A CN 202210300495A CN 114698257 B CN114698257 B CN 114698257B
- Authority
- CN
- China
- Prior art keywords
- layer
- manufacturing
- insulating medium
- namely
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000012545 processing Methods 0.000 title claims abstract description 38
- 239000000758 substrate Substances 0.000 title claims abstract description 28
- 238000005516 engineering process Methods 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 81
- 238000009713 electroplating Methods 0.000 claims abstract description 19
- 238000011049 filling Methods 0.000 claims abstract description 18
- 238000004806 packaging method and process Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 73
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 55
- 239000011889 copper foil Substances 0.000 claims description 42
- 229910052802 copper Inorganic materials 0.000 claims description 13
- 239000010949 copper Substances 0.000 claims description 13
- 238000013461 design Methods 0.000 claims description 9
- 238000003825 pressing Methods 0.000 claims description 9
- 238000005553 drilling Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 7
- 238000004140 cleaning Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 6
- 238000007788 roughening Methods 0.000 claims description 6
- 239000000654 additive Substances 0.000 claims description 5
- 238000011161 development Methods 0.000 claims description 5
- 238000002203 pretreatment Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 238000005137 deposition process Methods 0.000 claims description 4
- 238000004544 sputter deposition Methods 0.000 claims description 4
- 238000006243 chemical reaction Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000003698 laser cutting Methods 0.000 claims description 3
- 238000006116 polymerization reaction Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- 238000012546 transfer Methods 0.000 claims description 3
- 230000000996 additive effect Effects 0.000 claims description 2
- 230000009286 beneficial effect Effects 0.000 abstract description 4
- 238000011068 loading method Methods 0.000 abstract description 4
- 238000012536 packaging technology Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 182
- 238000011410 subtraction method Methods 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003814 drug Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000007781 pre-processing Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/188—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by direct electroplating
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application relates to a packaging loading plate with a fully-embedded precise circuit and a processing technology thereof, wherein the processing technology comprises the steps of preparing a substrate, manufacturing a first buried line layer, filling a first insulating medium, manufacturing a second buried line layer, repeatedly filling the insulating medium layer and the buried line layer, and manufacturing an n buried line layer, wherein the manufacturing of the n buried line layer comprises the steps of manufacturing an insulating layer, manufacturing a pattern reserved area, processing a through hole, manufacturing a seed layer, manufacturing a photosensitive pattern, electroplating the pattern, removing a film, removing a carrier layer and flashing. The processing technology meets the requirements of double-sided precise circuit manufacture, improves the reliability of the circuit, and simultaneously improves the surface flatness of the carrier plate, thereby being beneficial to the improvement of the packaging technology and the performance of finished products.
Description
Technical Field
The application relates to a packaging loading plate, in particular to a packaging loading plate with a fully embedded precise circuit and a processing technology thereof.
Background
Along with the continuous updating and iteration of the information age, the requirements on functions of various chips are higher and higher, such as high-speed operation, high storage, high precision, high stability and the like, and correspondingly, the requirements on packaging substrates are higher and higher, such as high-density wiring, thin plates, high flatness and the like, in the prior art, whether a masking method (Tenting) process or an improved semi-additive method (mSAP) process is adopted, a main flow process or a copper surface is higher than an insulating medium, then the conductors and the conductor surfaces are directionally insulated through surface layer ink coating, and part of products with flatness requirements on a carrier plate can be flattened through an ink flattening process, so that the flatness requirements of the products are met, but the thickness of the obtained carrier plate and the line width and the space of the line cannot meet the requirements.
Therefore, another process is a single-sided buried line process, the present step end is mainly applied to the RF field, the product is mainly characterized in that single-sided wiring is dense, the other side is of conventional design, special protection of patterns is not needed to be embedded, but with the continuous development of the technology, the wiring design of a carrier plate is more and more complex and presents an integrated trend, and the requirement for configuring the product by double-sided precise line design is more and more great, so that development of a process for manufacturing double-sided precise lines is urgently needed.
Content of the application
In order to overcome the defects, the application provides a processing technology of a packaging carrier plate based on a full-embedded precise circuit, which meets the requirements of manufacturing double-sided precise circuits, improves the reliability of the double-sided precise circuits, improves the surface flatness of the carrier plate, and is beneficial to improving the packaging technology and the performance of finished products.
The technical scheme adopted by the application for solving the technical problems is as follows:
A processing technology of a packaging carrier plate with a fully embedded precise circuit comprises the following steps:
step 1, preparing a substrate, namely preparing a substrate with a carrier layer and a copper foil layer;
Step 2, manufacturing a first buried line layer, namely manufacturing an embedded first buried line layer on the copper foil layer in an image electroplating mode;
filling an insulating medium, namely filling the insulating medium on the first buried line layer to form a first insulating medium layer;
and 4, manufacturing a second buried line layer:
① Processing a via hole, namely processing the via hole in the first insulating medium layer;
② Seed layer manufacturing, namely manufacturing a seed layer on the surface of the first insulating medium layer and the through hole;
③ Manufacturing a pattern circuit, namely manufacturing a second buried line layer on the seed layer;
step 5, repeating the steps 3 and 4 until an n-1 laminate is formed, wherein n is more than or equal to 3, and n is a natural number;
and 6, manufacturing an n buried line layer:
① The manufacture of the insulating layer, namely filling insulating medium on the n-1 buried line layer to form an n-1 insulating medium layer;
② The method comprises the steps of manufacturing a pattern reserved area, namely performing half-engraving on an n-1 insulating medium layer through a UV cold light processing technology, and engraving a pattern shape area which finally needs to be manufactured to a preset depth;
③ Processing the through holes, namely processing the design positions of the through holes in the n-1 insulating medium layer through a UV cold light processing technology to form the through holes, wherein the through holes are communicated to the n-1 buried line layer;
④ Seed layer manufacturing, namely manufacturing a seed layer on the surfaces of the n-1 insulating medium layer, the pattern shape area and the through holes for conducting the whole board;
⑤ Manufacturing a photosensitive pattern, namely photosensitive the seed layer in ④ to form a photosensitive layer, and exposing a pattern shape area and a via hole to be electroplated;
⑥ Electroplating the pattern, namely electroplating copper on the plate, filling copper in the through hole and forming an n buried line layer on the exposed pattern shape area;
⑦ Removing the residual photosensitive layer;
⑧ Polishing, namely grinding and polishing the plate after film removal to remove slight bulges on the surface;
⑨ Removing the carrier layer;
⑩ And (3) flashing, namely etching the copper foil layer to expose the first buried line layer on the copper foil layer, thereby completing the manufacturing of the multilayer board with the precise circuits embedded on both sides.
Preferably, in step 1, the carrier layer and the copper foil layer are opened around the working area of the substrate.
Preferably, drilling is performed around the working area of the substrate to form a plurality of through holes for communicating the carrier layer and the copper foil layer, and when the first insulating medium layer is pressed, the insulating medium flows into the through holes, and the copper foil layer and the carrier layer are combined together from the side wall.
Preferably, a groove is cut around the working area of the substrate by using a laser cutting process, the groove is communicated with the carrier layer and the copper foil layer, and when the first insulating medium layer is pressed, the insulating medium flows into the groove to combine the copper foil layer and the carrier layer together.
Preferably, a certain area is burned out around the working area of the substrate by using a laser process, and the carrier layer is exposed, when the first insulating medium layer is pressed, the insulating medium flows to the surface of the burned-out area of the carrier layer, and the copper foil layer and the carrier layer are combined together.
Preferably, the step 2 specifically includes the following processes:
① Pre-treatment, namely cleaning and roughening the surface of the copper foil layer;
② Manufacturing a photosensitive layer, namely uniformly distributing a photosensitive layer on the surface of the copper foil layer in a pressing or coating mode;
③ Exposing, namely enabling light and a photosensitive layer to perform polymerization reaction in an image transfer mode to form a pattern which cannot be removed by a developing solution but can be removed by a film removing solution;
④ Removing the photosensitive layer of the unreacted area, and reserving the area where photopolymerization reaction occurs;
⑤ Electroplating the exposed area after development to form a required pattern circuit;
⑥ Removing the film, namely removing the photosensitive layer to form a final first buried line layer.
Preferably, the steps ① and ① in the steps 3 and 6 specifically include the following processes:
① Pre-treatment, namely cleaning and roughening the surface of the pattern circuit layer to increase the binding force between the circuit and the insulating medium and improve the product performance;
② Filling an insulating medium, namely forming an insulating medium layer on the pattern circuit layer through a pressing or vacuum pressing matching baking process.
Preferably, in ① of the step 4, a laser windowing and laser drilling process is adopted to manufacture blind holes, in the manufacture process, the alignment reference is a target hole taking an inner layer target as a reference, or a laser direct blind hole forming process is adopted to manufacture blind holes, in the manufacture process, the alignment reference is an inner layer target, in ② of the step 4 or ④ of the step 6, a seed layer is manufactured by adopting a copper deposition process or a sputtering process, in ③ of the step 4 or ⑥ of the step 6, in the process of manufacturing patterns, an addition method is adopted to match pattern electroplating, a semi-addition method or a subtraction method to match a whole plate electroplating and etching process according to pattern wiring density, and pattern build-up manufacturing is carried out.
Preferably, in ⑥ of the step 6, the upper surface of the n buried line layer is lower than the upper surface of the n-1 insulating dielectric layer by 0-5 um.
The application also provides a packaging carrier plate with the fully-embedded precise circuit, which is processed by adopting the processing technology.
The beneficial effects of the application are as follows:
1) Based on the existing embedded circuit process ETS (Embedded Trace Substrate), the UV laser and the mSAP processing process are innovatively used to embed the other surface of the outermost circuit into the insulating layer, so that all circuits are embedded into the insulating layer;
2) The processing technology meets the requirements of manufacturing the multi-layer board with double-sided precise circuits, improves the reliability of the multi-layer board, improves the surface flatness of the carrier board, and is beneficial to improving the packaging technology and the performance of finished products;
3) The processing technology is suitable for the design of the minimum line width/line distance of the outer layer of 15 mu m/15 mu m, can meet the design requirement of a new packaging mode on the double-sided fine circuit of the substrate, and reduces the bad products caused by flying lines and broken lines;
4) According to the application, the double-sided precise circuit in the carrier plate is embedded in the insulating medium, so that the bonding area of the fine circuit and the surrounding medium layer is enhanced, the bonding force is enhanced, the performance stability of the fine wire is improved, the electromagnetic crosstalk can be effectively reduced by isolating the circuit from the circuit through the PP insulating layer, and the good circuit shielding performance can be widely applied to high-end smart phones and PC ends;
5) Because the pattern circuit is embedded in the insulating medium layer, the flatness of the two sides of the substrate is better than that of a conventional substrate, and after the substrate is covered with the ink, the flatness is less than or equal to 3 mu m, and the sensitive IC packaging requirement can be met.
Drawings
FIG. 1 is a schematic view of the structure of an n-1 laminate of the present application;
FIG. 2 is a schematic view of the structure of the n-1 laminate of the present application after forming a pattern shape region;
FIG. 3 is a schematic view of the structure of the n-1 laminate of the present application after processing via holes;
FIG. 4 is a schematic view of the structure of the n-1 layer plate after the photosensitive layer is formed;
FIG. 5 is a schematic view of an n-layer structure according to the present application;
FIG. 6 is a schematic view of the structure of the n-layer plate of the present application after the photosensitive layer is removed;
FIG. 7 is a schematic view of the structure of the n-layer carrier layer removed in the present application;
FIG. 8 is a schematic view of the structure of the n-layer copper foil removed layer according to the present application;
FIG. 9 is a schematic view of the structure of the finished board of the present application;
In the figure, the substrate 10, the carrier layer 11, the copper foil layer 12, the first buried line layer 13, the first insulating dielectric layer 14, the second buried line layer 21, the second buried line layer 22, the first insulating dielectric layer 1, the pattern-shaped area 23, the photosensitive layer 24 and the second buried line layer 25 are arranged.
Detailed Description
The technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the following figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the application described herein may be capable of being practiced otherwise than as specifically shown or described. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Spatially relative terms, such as "above," "upper" and "upper surface," "above" and the like, may be used herein for ease of description to describe one device or feature's spatial relationship to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the process is carried out, the exemplary term "above" may be included. Upper and lower. Two orientations below. The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The embodiment of the method for processing the packaging carrier plate with the fully-embedded precise circuit comprises the following steps of:
step 1, preparing a substrate 10, namely preparing a substrate with a carrier layer 11 and a copper foil layer 12, wherein the copper foil layer is an ultrathin copper foil layer;
step 2, manufacturing a first buried line layer 13, namely manufacturing an embedded first buried line layer 13 on the copper foil layer 12 in an image electroplating mode;
Filling an insulating medium, namely filling the insulating medium on the first buried line layer 13 to form a first insulating medium layer 14;
step 4, manufacturing a second buried line layer 21:
① Processing via holes, namely processing via holes in the first insulating medium layer 14;
② Seed layer preparation, namely preparing a seed layer on the surface of the first insulating medium layer 14 and the through hole;
③ Manufacturing a pattern line, namely manufacturing a second buried line layer 21 on the seed layer;
Step 5, repeating the steps 3 and 4 until an n-1 laminate is formed, wherein n is more than or equal to 3 and n is a natural number, namely repeating the preparation of filling the insulating medium and the buried line layer, adding one laminate every time the steps 3 and 4 are repeated, manufacturing a second insulating medium layer and a third buried line layer when the steps 3 and 4 are repeated for the first time, and the like to form a multilayer board with the required layer number, wherein the uppermost layer is an n-1 buried line layer, and forming an n-1 laminate at the moment, wherein the third to n-1 buried line layers and the insulating medium layers between the third and n-1 buried line layers are omitted in the figure, and the following steps are the same;
step 6, manufacturing an n-th buried line layer 25:
① The insulating layer is manufactured by filling insulating medium on the n-1 buried line layer to form an n-1 insulating medium layer 22;
② Pattern reserved area manufacture, as shown in fig. 2, half-engraving is performed on the n-1 insulating medium layer 22 through a UV cold light processing technology, and a pattern shape area 23 which is finally required to be manufactured to a preset depth is engraved;
③ Processing the through holes, namely processing the design positions of the through holes in the n-1 insulating medium layer 22 through a UV cold light processing technology to form the through holes, wherein the through holes are communicated to the n-1 buried line layer as shown in FIG. 3;
④ Seed layer manufacturing, namely manufacturing a seed layer on the surfaces of the n-1 insulating medium layer, the pattern shape area and the through holes for conducting the whole board;
⑤ Manufacturing a photosensitive pattern, namely, as shown in fig. 4, photosensitive the seed layer ④ to form a photosensitive layer 24, and exposing a pattern shape area and a via hole to be electroplated;
⑥ Pattern plating, as shown in fig. 5, copper plating is performed on the plate, copper is filled in the through hole, and an n-th buried line layer 25 is formed on the exposed pattern shape area;
⑦ Film stripping, namely, as shown in fig. 6, removing the residual photosensitive layer;
⑧ Polishing, namely grinding and polishing the plate after film removal to remove slight bulges on the surface;
⑨ The carrier layer 11 is removed, as shown in FIG. 7, by peeling;
⑩ And (3) flashing, namely etching away the copper foil layer 12 to expose the first buried wire layer 13 on the copper foil layer, thereby completing the manufacture of the multilayer board with the precise circuits embedded on the two sides. According to the design requirement of the product, the post-manufacturing process comprises the steps of welding prevention, surface treatment, forming, finished product testing, finished product inspection, packaging and shipment, and as shown in fig. 9, a finished product plate is formed, and the final finished product is the packaging carrier plate.
In step 1, the carrier layer 11 and the copper foil layer 12 are opened around the working area of the substrate 10, and the following three methods are adopted:
Drilling around the working area of the substrate 10 to form a plurality of through holes for communicating the carrier layer 11 and the copper foil layer 12, and when the first insulating medium layer 14 is pressed, the insulating medium flows into the through holes to combine the copper foil layer 12 and the carrier layer 11 together from the side wall.
And secondly, cutting grooves on the periphery of the working area of the substrate 10 by utilizing a laser cutting process, wherein the grooves are communicated with the carrier layer 11 and the copper foil layer 12, and when the first insulating medium layer 14 is pressed, insulating medium flows into the grooves to combine the copper foil layer 12 and the carrier layer 11 together.
The third method is to burn out a certain area around the working area of the substrate 10 by using a laser process to expose the carrier layer 11, and when the first insulating medium layer 14 is pressed, the insulating medium flows to the surface of the burned area of the carrier layer to combine the copper foil layer 12 and the carrier layer 11 together.
By using the three processes, the edge of the working area of the substrate is subjected to isolation treatment, and the ultrathin copper foil layer is combined with the carrier layer 11 through the first insulating medium, so that the ultrathin copper foil layer can be prevented from being separated due to external force or attack of liquid medicine in the production process.
The step 2 specifically comprises the following processes:
① Pre-treatment, namely cleaning and roughening the surface of the copper foil layer 12;
② Manufacturing a photosensitive layer, namely uniformly distributing a photosensitive layer on the surface of the copper foil layer in a pressing or coating mode;
③ Exposing, namely enabling light and a photosensitive layer to perform polymerization reaction in an image transfer mode to form a pattern which cannot be removed by a developing solution but can be removed by a film removing solution;
④ Removing the photosensitive layer of the unreacted area, and reserving the area where photopolymerization reaction occurs;
⑤ Electroplating the exposed area after development to form a required pattern circuit;
⑥ Removing the film, namely removing the photosensitive layer to form a final first buried line layer 13.
The steps ① and ① in the steps 3 and 6 specifically include the following processes:
① The method comprises the steps of preprocessing, namely cleaning and roughening the surface of a pattern circuit layer to increase the binding force of a circuit and an insulating medium and improve the performance of a product, wherein the pattern circuit layer is a first buried layer, a second buried layer and a third buried layer, if a final carrier plate is a three-layer plate, the pattern circuit layer is a first buried layer and a second buried layer, if the final carrier plate is a four-layer plate, the pattern circuit is a first buried layer and a second buried layer, and the like.
② Filling an insulating medium, namely forming an insulating medium layer on the pattern circuit layer through a pressing or vacuum pressing matching baking process. The process of filling the insulating medium is not limited to the above two modes as long as the processing characteristics of the insulating medium are matched.
In ① of the step 4, a laser windowing and laser drilling process is adopted to manufacture blind holes, the alignment reference is a target hole taking an inner layer target as a reference in the manufacturing process, or a laser direct blind hole forming process is adopted to manufacture blind holes, the alignment reference is an inner layer target in the manufacturing process, in ② of the step 4 or ④ of the step 6, a seed layer is manufactured by adopting a copper deposition process or a sputtering process, and in ③ of the step 4 or ⑥ of the step 6, when in pattern manufacturing, an additive method is adopted to match with a pattern electroplating, a semi-additive method or a subtractive method to match with a whole plate electroplating and etching process according to the pattern wiring density, so that pattern build-up manufacturing is carried out. Of course, the blind hole processing mode is not limited to the laser windowing and laser drilling process or LDD (LASER DIRECT DRILLING, laser directly forming blind holes), the seed layer manufacturing is not limited to the copper deposition process and the sputtering process, the equivalent conducting function can be realized, the pattern wiring is not limited to the addition method or the subtraction method, and the pattern manufacturing can be realized, wherein the addition method, the pattern electroplating, the half-addition method, the subtraction method, the whole plate electroplating and the etching are all conventional processes in the field, and are not described in detail herein.
In the ⑥ of the step 6, the upper surface of the n-th buried line layer 25 is lower than the upper surface of the n-1-th insulating dielectric layer by 0-5 um. Namely, the distance between the highest interface of the copper surface and the highest interface of the insulating medium is controlled to be 0-5 um during manufacturing, on one hand, the phenomenon that the height of the electroplated pattern is higher than that of the insulating medium to cause irregular top of the circuit pattern is prevented, and on the other hand, the copper surface is controlled to be lower than the insulating medium and cannot exceed a certain limit, so that adverse effects on the sealing and testing process are prevented.
As shown in fig. 9, a package carrier with fully embedded precision circuit is manufactured by the above-mentioned processing technology.
It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the application, which are all within the scope of the application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
Claims (8)
1. A processing technology of a packaging carrier plate with a fully embedded precise circuit is characterized by comprising the following steps:
step 1, preparing a substrate (10), namely preparing a substrate with a carrier layer (11) and a copper foil layer (12);
Step 2, manufacturing a first buried line layer (13), namely manufacturing an embedded first buried line layer (13) on the copper foil layer (12) in an image electroplating mode;
Filling an insulating medium, namely filling the insulating medium on the first buried line layer (13) to form a first insulating medium layer (14);
and 4, manufacturing a second buried line layer (21):
① Processing a via hole, namely processing the via hole in the first insulating medium layer (14);
② Seed layer preparation, namely preparing a seed layer on the surface of the first insulating medium layer (14) and the through hole;
③ Manufacturing a pattern line, namely manufacturing a second buried line layer (21) on the seed layer;
step 5, repeating the steps 3 and 4 until an n-1 laminate is formed, wherein n is more than or equal to 3, and n is a natural number;
step 6, manufacturing an n buried line layer (25):
① The manufacture of the insulating layer, namely, filling an insulating medium on the n-1 buried line layer to form an n-1 insulating medium layer (22);
② The manufacturing of the pattern reserved area, namely, half-engraving is carried out on the n-1 insulating medium layer (22) through a UV cold light processing technology, and a pattern shape area (23) which is finally required to be manufactured to a preset depth is engraved;
③ Processing the through hole, namely processing the design position of the through hole in the n-1 insulating medium layer (22) through a UV cold light processing technology to form the through hole which is communicated to the n-1 buried line layer;
④ Seed layer manufacturing, namely manufacturing a seed layer on the surfaces of the n-1 insulating medium layer, the pattern shape area and the through holes for conducting the whole board;
⑤ Manufacturing a photosensitive pattern, namely photosensitive the seed layer in ④ to form a photosensitive layer (24), and exposing a pattern shape area and a via hole to be electroplated;
⑥ Electroplating the pattern, namely electroplating copper on the plate, filling copper in the through hole and forming an n buried line layer (25) on the exposed pattern-shaped area;
⑦ Removing the residual photosensitive layer;
⑧ Polishing, namely grinding and polishing the plate after film removal to remove slight bulges on the surface;
⑨ Removing the carrier layer (11);
⑩ Etching the copper foil layer (12) to expose the first buried line layer (13) on the copper foil layer, thereby completing the manufacture of the multilayer board with the precise circuits embedded on both sides;
The steps ① and ① in the steps 3 and 6 specifically include the following processes:
① Pre-treatment, namely cleaning and roughening the surface of the pattern circuit layer to increase the binding force between the circuit and the insulating medium and improve the product performance;
② Filling an insulating medium, namely forming an insulating medium layer on the pattern circuit layer through a pressing or vacuum pressing matching baking process;
In ① of the step 4, a laser windowing and laser drilling process is adopted to manufacture blind holes, the alignment reference is a target hole taking an inner layer target as a reference in the manufacturing process, or a laser direct blind hole forming process is adopted to manufacture blind holes, the alignment reference is an inner layer target in the manufacturing process, in ② of the step 4 or ④ of the step 6, a seed layer is manufactured by adopting a copper deposition process or a sputtering process, and in ③ of the step 4 or ⑥ of the step 6, when in pattern manufacturing, an additive method is adopted to match with a pattern electroplating, a semi-additive method or a subtractive method to match with a whole plate electroplating and etching process according to the pattern wiring density, so that pattern build-up manufacturing is carried out.
2. The process for manufacturing a package carrier with fully embedded precision circuits according to claim 1, wherein in step 1, the carrier layer (11) and the copper foil layer (12) are opened around the working area of the substrate (10).
3. The process for manufacturing a package carrier with fully embedded precision circuits according to claim 2, wherein a plurality of through holes are formed around the working area of the substrate (10) by drilling, wherein the through holes are communicated with the carrier layer (11) and the copper foil layer (12), and when the first insulating medium layer (14) is pressed, the insulating medium flows into the through holes, and the copper foil layer (12) and the carrier layer (11) are combined together from the side walls.
4. The process for manufacturing a package carrier with fully embedded precision circuits according to claim 2, wherein a laser cutting process is used to cut grooves around the working area of the substrate (10), the grooves are communicated with the carrier layer (11) and the copper foil layer (12), and when the first insulating medium layer (14) is pressed, the insulating medium flows into the grooves to combine the copper foil layer (12) with the carrier layer (11).
5. The process for manufacturing a package carrier with fully embedded precision circuits according to claim 2, wherein a laser process is used to burn out a certain area around the working area of the substrate (10) to expose the carrier layer (11), and when the first insulating medium layer (14) is pressed, the insulating medium flows to the surface of the burned-out area of the carrier layer to bond the copper foil layer (12) and the carrier layer (11) together.
6. The process for manufacturing a package carrier with fully embedded precision circuits according to claim 1, wherein said step 2 comprises the following steps:
① Pre-treatment, namely cleaning and roughening the surface of the copper foil layer (12);
② Manufacturing a photosensitive layer, namely uniformly distributing a photosensitive layer on the surface of the copper foil layer in a pressing or coating mode;
③ Exposing, namely enabling light and a photosensitive layer to perform polymerization reaction in an image transfer mode to form a pattern which cannot be removed by a developing solution but can be removed by a film removing solution;
④ Removing the photosensitive layer of the unreacted area, and reserving the area where photopolymerization reaction occurs;
⑤ Electroplating the exposed area after development to form a required pattern circuit;
⑥ Removing the film, namely removing the photosensitive layer to form a final first buried line layer (13).
7. The process of claim 1, wherein in step ⑥, the upper surface of the n buried line layer (25) is lower than the upper surface of the n-1 insulating dielectric layer by 0-5 um.
8. A packaging carrier plate with a fully embedded precise circuit is characterized by being processed by adopting the processing technology of any one of claims 1-7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210300495.4A CN114698257B (en) | 2022-03-25 | 2022-03-25 | Package substrate with fully embedded precision circuits and its processing technology |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210300495.4A CN114698257B (en) | 2022-03-25 | 2022-03-25 | Package substrate with fully embedded precision circuits and its processing technology |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114698257A CN114698257A (en) | 2022-07-01 |
| CN114698257B true CN114698257B (en) | 2024-12-03 |
Family
ID=82138951
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210300495.4A Active CN114698257B (en) | 2022-03-25 | 2022-03-25 | Package substrate with fully embedded precision circuits and its processing technology |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114698257B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103491732A (en) * | 2013-10-08 | 2014-01-01 | 华进半导体封装先导技术研发中心有限公司 | Method for manufacturing circuit board layer-adding structure |
| CN106376184A (en) * | 2016-07-22 | 2017-02-01 | 深南电路股份有限公司 | Manufacturing method of embedded line and packaging substrate |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4489364A (en) * | 1981-12-31 | 1984-12-18 | International Business Machines Corporation | Chip carrier with embedded engineering change lines with severable periodically spaced bridging connectors on the chip supporting surface |
| CN107241875B (en) * | 2016-03-28 | 2019-05-07 | 上海美维科技有限公司 | A kind of manufacturing method of two-sided printed board of sunkening cord |
| CN108207082A (en) * | 2017-12-29 | 2018-06-26 | 上海美维科技有限公司 | A kind of method for laser machining line slot and making two-sided printed circuit board of sunkening cord |
| CN114206001B (en) * | 2021-11-30 | 2023-11-14 | 江苏普诺威电子股份有限公司 | High-voltage-resistant MEMS (micro-electromechanical systems) packaging loading plate and manufacturing process thereof |
-
2022
- 2022-03-25 CN CN202210300495.4A patent/CN114698257B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103491732A (en) * | 2013-10-08 | 2014-01-01 | 华进半导体封装先导技术研发中心有限公司 | Method for manufacturing circuit board layer-adding structure |
| CN106376184A (en) * | 2016-07-22 | 2017-02-01 | 深南电路股份有限公司 | Manufacturing method of embedded line and packaging substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114698257A (en) | 2022-07-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8633392B2 (en) | Circuit board with high-density circuit patterns | |
| CN102111952B (en) | Multilayer wiring substrate | |
| US20090277673A1 (en) | PCB having electronic components embedded therein and method of manufacturing the same | |
| CN102111968A (en) | Method of manufacturing multilayer wiring substrate, and multilayer wiring substrate | |
| CN103458628A (en) | Multi-layer circuit board and manufacturing method thereof | |
| CN103517582B (en) | Multi-layer circuit board and its manufacturing method | |
| CN106255349A (en) | A kind of manufacturing method of PCB and PCB | |
| CN103796451A (en) | Printed wiring board and method for manufacturing printed wiring board | |
| CN103579173A (en) | Semiconductor package and fabrication method thereof | |
| CN108323002B (en) | Printed circuit board and method | |
| CN116646254A (en) | Packaging carrier plate with high aspect ratio via hole and processing method thereof | |
| TWI677267B (en) | Circuit board and method for manufacturing the same | |
| CN114698257B (en) | Package substrate with fully embedded precision circuits and its processing technology | |
| CN114679850B (en) | Front-mounted double-sided embedded precision circuit packaging substrate and its processing technology | |
| CN110740564B (en) | Processing method of dense network multilayer printed circuit board | |
| CN114641153B (en) | Embedded precision circuit packaging substrate based on photosensitive insulating medium and its processing technology | |
| CN116631883B (en) | Packaging substrate and manufacturing method thereof, chip and manufacturing method thereof | |
| CN114698270B (en) | Precision circuit packaging substrate based on surface protection and its processing technology | |
| KR100633852B1 (en) | Cavity formed substrate manufacturing method | |
| KR20110010427A (en) | Odd-layer printed circuit board and manufacturing method thereof | |
| CN110062538B (en) | A PCB manufacturing method and PCB with leads at the bottom of a stepped groove | |
| KR100547349B1 (en) | Semiconductor Package Substrate and Manufacturing Method Thereof | |
| JP2021040118A (en) | Multilayer flexible circuit board and manufacturing method thereof | |
| CN119136445B (en) | A method for manufacturing a hole-coated copper and a method for manufacturing an asymmetric structure HDI board | |
| CN223142206U (en) | Intermediate structure for packaging carrier board circuit preparation process |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |