CN114695554A - Semiconductor structure and forming method thereof - Google Patents

Abstract

A semiconductor structure and a method of forming the same, comprising: the semiconductor device comprises a substrate, a first electrode and a second electrode, wherein the substrate is provided with a first fin part and a second fin part; the first side wall structures are arranged on the side walls of the first grid structures, and the edges of the first side wall structures have a second size; and the second side wall structures are arranged on the side walls of the second gate structures, and have a fourth size along the second side wall structures, and the fourth size is smaller than the second size. And covering the first fin part by increasing the second size of the first side wall structure, so that the size of the formed first source drain opening is reduced. When the source-drain doping layer in the second source-drain opening is filled, the source-drain doping layer formed in the first source-drain opening can fill more space, so that the depression of the source-drain doping layer in the first source-drain opening at the middle position is reduced, the risk that the conducting layer penetrates through the middle part of the source-drain doping layer is reduced, and the performance of the finally formed semiconductor structure is improved.

Description

Semiconductor structure and method of forming the same

technical field

The present invention relates to the technical field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.

Background technique

With the improvement of the integration level of semiconductor devices, the critical dimension of transistors is continuously reduced, and the reduction of the critical dimension means that a larger number of transistors can be arranged on a chip, thereby improving the performance of the device. However, as device areas continue to shrink, problems also arise. With the sharp reduction of the size of the transistor, the thickness of the gate dielectric layer and the operating voltage cannot be changed accordingly, which makes it more difficult to suppress the short-channel effect and increases the channel leakage current of the transistor.

The MOS tube shrinks and the gate becomes shorter, so that the current channel under the gate also becomes shorter. When the MOS tube channel is shortened to a certain extent, a short channel effect will occur. Theoretically, the channel length is the distance from the source front extension to the drain front extension. However, the effective length of the channel will be affected by the junction void region formed by the source and drain and the substrate. When the channel length is equal to or shorter than the depth of the junction surface void region, the junction surface void region will significantly cut into the current channel, resulting in a lower gate threshold voltage, which is the short-channel effect.

In order to reduce the short channel effect of the semiconductor device, the first width dimension of the gate structure along the extension direction of the fin is usually increased in the prior art. However, when the first width dimension of the gate structure is increased, other problems will also occur, so that the performance of the finally formed semiconductor structure is degraded.

Therefore, the performance of the semiconductor structures formed in the prior art still needs to be improved.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the performance of the finally formed semiconductor structure.

In order to solve the above problems, the present invention provides a semiconductor structure, comprising: a substrate, the substrate includes a first region and a second region, the first region has a plurality of first fins separated from each other, the first region The second area has a plurality of mutually separated second fins, the first fins and the second fins respectively extend along the first direction; a plurality of first gate structures located on the first area, the The first gate structure straddles the first fin, and the adjacent first gate structures have a first dimension along the first direction, and the sidewalls of the first gate structures have a first dimension. a first spacer structure, the first spacer structure has a second dimension along the first direction; a plurality of second gate structures located on the second region, the second gate structures spanning the The second fins have a third size along the first direction between the adjacent second gate structures, the third size is smaller than the first size, and the side of the second gate structures There is a second spacer structure on the wall, and the second spacer structure has a fourth size along the first direction, and the fourth size is smaller than the second size; a first source-drain opening in the first fin; a second source-drain opening in the second fin on both sides of the second gate structure; the first source-drain opening and the second a source-drain doped layer in the source-drain opening, the top surface of the source-drain doped layer located in the first source-drain opening is lower than the top surface of the first fin, and located in the second source-drain opening The top surface of the source-drain doped layer is flush with the top surface of the second fin.

Optionally, the method further includes: a conductive layer on the source and drain doped layers.

Optionally, the material of the conductive layer includes metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

Optionally, the first spacer structure includes: a first spacer located on a sidewall of the first gate structure, and a second spacer located on a sidewall of the first spacer.

Optionally, the second spacer structure includes: a third spacer located on the sidewall of the second gate structure.

Optionally, the first gate structure has a first width dimension along the first direction, the second gate structure has a second width dimension along the first direction, and the first width dimension greater than the second width dimension.

Optionally, the material of the source and drain doped layers includes: SiP, SiCP, SiGe or SiGeB.

Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate, the substrate includes a first region and a second region, and the first region has a plurality of mutually discrete a first fin, the second area has a plurality of mutually discrete second fins, the first fin and the second fin respectively extend along a first direction; a plurality of second fins are formed on the first area a first gate structure, the first gate structure spanning the first fin, and a first dimension along the first direction between adjacent first gate structures, the first A first spacer structure is formed on the sidewall of the gate structure, and the first spacer structure has a second dimension along the first direction; a plurality of second gate structures are formed on the second region, the first spacer structure is Two gate structures span the second fins, and adjacent second gate structures have a third dimension along the first direction, and the third dimension is smaller than the first dimension, so A second spacer structure is formed on the sidewall of the second gate structure, and the second spacer structure has a fourth size along the first direction, and the fourth size is smaller than the second size; forming first source-drain openings in the first fins on both sides of the first gate structure; forming second source-drain openings in the second fins on both sides of the second gate structure; A source-drain doped layer is formed in the source-drain opening and the second source-drain opening at the same time, until the source-drain doped layer fills the second source-drain opening, and the source-drain doped layer located in the first source-drain opening The top surface of the drain doped layer is lower than the top surface of the first fin, and the top surface of the source and drain doped layer in the second source/drain opening is flush with the top surface of the second fin.

Optionally, after forming the source and drain doped layers, the method further includes: forming a conductive layer on the source and drain doped layers.

Optionally, the material of the conductive layer includes metal, and the metal includes: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

Optionally, the first spacer structure includes: a first spacer located on a sidewall of the first gate structure, and a second spacer located on a sidewall of the first spacer.

Optionally, the second spacer structure includes: a third spacer located on the sidewall of the second gate structure.

Optionally, before forming the first gate structure and the second gate structure, the method further includes: forming a first dummy gate structure on the first region, the first dummy gate structure spanning all the forming the first fin portion; forming a second dummy gate structure on the second region, the second dummy gate structure spanning the second fin portion.

Optionally, the method for forming the first spacer includes: forming a first spacer material on sidewalls and top surfaces of the first dummy gate structure and the second dummy gate structure, and on the substrate layer; etch back the first spacer material layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed to form an initial first spacer; remove the second dummy gate structure The initial first spacer on the sidewall of the gate structure, and the first spacer is formed on the sidewall of the first dummy gate structure.

Optionally, the formation process of the first spacer material layer includes an atomic layer deposition process.

Optionally, the method for forming the second spacer and the third spacer includes: forming the first spacer and the sidewall of the second dummy gate structure, the first dummy gate structure and the sidewall of the second dummy gate structure. forming a second spacer material layer on the top surface of the second dummy gate structure and the substrate; and etching back the second spacer material layer until the first dummy gate structure and the first spacer material layer are exposed Up to the top surface of the two dummy gate structures, the second spacer is formed on the sidewall of the first spacer, and the third spacer is formed on the sidewall of the second dummy gate structure.

Optionally, the formation process of the second spacer material layer includes an atomic layer deposition process.

Optionally, the method for forming the first gate structure and the second gate structure includes: forming a dielectric layer on the substrate, the dielectric layer covering the first dummy gate structure and the second gate structure Two sidewalls of dummy gate structures; removing the first dummy gate structure, forming a first gate opening in the dielectric layer; removing the second dummy gate structure, forming a second gate in the dielectric layer opening; forming the first gate structure in the first gate opening; forming the second gate structure in the second gate opening.

Optionally, the first gate structure has a first width dimension along the first direction, the second gate structure has a second width dimension along the first direction, and the first width dimension greater than the second width dimension.

Optionally, the method for forming the source-drain doped layer includes: using an epitaxial growth process to simultaneously form an epitaxial layer in the first source-drain opening and the second source-drain opening, until the epitaxial layer is fully filled. In-situ doping is performed on the epitaxial layer during the epitaxial growth process, and the source-drain ions are doped into the epitaxial layer to form the source-drain doped layer.

Optionally, the material of the source and drain doped layers includes: SiP, SiCP, SiGe or SiGeB.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the structure of the technical solution of the present invention, the first gate structure located on the first region has a first spacer structure on the sidewall of the first gate structure, and the first spacer structure is along the The first direction has a second dimension; the second gate structure located on the second region has a second spacer structure on the sidewall of the second gate structure, and the second spacer structure is along the The first direction has a fourth dimension that is smaller than the second dimension. By increasing the second dimension of the first sidewall structure along the first direction, the first fin portion is further covered, and the exposed dimension of the first fin portion along the first direction is reduced, thereby further covering the first fin portion. The size of the formed first source-drain opening along the first direction is reduced. When the size of the first source-drain opening decreases along the first direction, when the source-drain doping layer in the second source-drain opening is filled, the doped layer formed in the first source-drain opening is filled. The source-drain doped layer can fill more space, which reduces the concavity of the source-drain doped layer in the first source-drain opening in the middle position, thereby reducing the penetration of the source-drain doped layer by the subsequently formed conductive layer. The risk of the middle portion of the drain doped layer improves the contact between the conductive layer and the source-drain doped layer in the first source-drain opening, thereby improving the performance of the finally formed semiconductor structure.

In the formation method of the technical solution of the present invention, a first gate structure is formed on the first region, a first spacer structure is formed on the sidewall of the first gate structure, and the first spacer structure is along the The first direction has a second dimension; a second gate structure is formed on the second region, a sidewall of the second gate structure has a second spacer structure, and the second spacer structure is along the The first direction has a fourth dimension that is smaller than the second dimension. By increasing the second dimension of the first sidewall structure along the first direction, the first fin portion is further covered, and the exposed dimension of the first fin portion along the first direction is reduced, thereby further covering the first fin portion. The size of the formed first source-drain opening along the first direction is reduced. When the size of the first source-drain opening decreases along the first direction, when the source-drain doping layer in the second source-drain opening is filled, the doped layer formed in the first source-drain opening is filled. The source-drain doped layer can fill more space, which reduces the concavity of the source-drain doped layer in the first source-drain opening in the middle position, thereby reducing the penetration of the source-drain doped layer by the subsequently formed conductive layer. The risk of the middle portion of the drain doped layer improves the contact between the conductive layer and the source-drain doped layer in the first source-drain opening, thereby improving the performance of the finally formed semiconductor structure.

Description of drawings

1 is a schematic structural diagram of a semiconductor structure;

FIG. 2 to FIG. 13 are schematic structural diagrams of each step of an embodiment of a method for forming a semiconductor structure of the present invention.

Detailed ways

As described in the background art, the performance of the semiconductor structures formed in the prior art still needs to be improved. The following will be described in detail with reference to the accompanying drawings.

Referring to FIG. 1 , a substrate 100 is provided, and the substrate 100 has a plurality of fins 101 which are separated from each other, and the fins extend along the first direction X; an isolation layer 102 is formed on the substrate 100 , the The isolation layer 102 covers part of the sidewall surface of the fin 101, and the top surface of the isolation layer 102 is lower than the top surface of the fin 101; a dummy gate structure 103 is formed on the substrate 100, and the The dummy gate structure 103 spans the fin portion 101 , and the dummy gate structure 103 covers part of the sidewalls and the top surface of the fin portion 101 ; formed in the fin portion 101 on both sides of the dummy gate structure 103 Source-drain openings (not marked); a source-drain doped layer 104 is formed in the source-drain doped layer 104 , and the source-drain doped layer 104 has source-drain ions; a conductive layer is formed on the source-drain doped layer 104 105.

In this embodiment, by increasing the first width dimension d1 of the dummy gate structure 103 in the first direction X, the first width dimension d1 is greater than 50 nm, so as to increase the length of the channel, thereby reducing the length of the channel. channel effect.

However, when the first width dimension d1 of the dummy gate structure 103 increases, the enlarged size of the fin portion 101 along the first direction X also increases, so that both sides of the dummy gate structure 103 are exposed The second width dimension d2 of the exposed fins 101 increases; when the second width dimension d2 of the exposed fins 101 increases, the size of the subsequently formed source-drain openings along the first direction X is made will also increase. Since the source-drain doping layer 104 is formed by epitaxial growth on the fins 101 exposed on the surface of the source-drain opening, when the size of the source-drain opening along the first direction X is larger, the The volume of the source-drain doped layer 104 grown in the second direction Y is smaller, and the second direction Y is perpendicular to the first direction X, so that the source-drain doped layer 104 will appear in the middle position sunken.

When the source-drain doped layer 104 is recessed in the middle position, the source-drain doped layer 104 is easily etched through during the formation of the conductive layer 105 , so that the final conductive layer 105 is formed. The bottom surface of the fin portion is in contact with the fin portion 101 , so that the contact resistance between the conductive layer 105 and the source-drain doped layer 104 is increased, thereby reducing the performance of the finally formed semiconductor structure.

On this basis, the present invention provides a semiconductor structure and a method for forming the same, wherein the first spacer structure has a second dimension along the first direction; the second spacer structure has a second dimension along the first direction Four dimensions, the fourth dimension being smaller than the second dimension. By increasing the second size of the first spacer structure along the first direction, the size of the formed first source-drain opening along the first direction is reduced. When the source-drain doped layers in the second source-drain openings are filled, the source-drain doped layers formed in the first source-drain openings can fill more space, reducing the first source-drain doped layer. A recess in the middle of the source-drain doped layer in the source-drain opening reduces the risk of the subsequently formed conductive layer penetrating the middle portion of the source-drain doped layer, so that the conductive layer and the first The contact between the source-drain doped layers in the source-drain opening is improved, thereby improving the performance of the finally formed semiconductor structure.

In order to make the above objects, features and advantages of the present invention more clearly understood, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

2 to 13 are schematic structural diagrams of a process of forming a semiconductor structure according to an embodiment of the present invention.

Referring to FIG. 2 , a substrate 200 is provided, the substrate 200 includes a first region I and a second region II, the first region I has a plurality of first fins 201 separated from each other, and the second region II There are several second fins 202 which are separated from each other, and the first fins 201 and the second fins 202 extend along the first direction X respectively.

In this embodiment, the method for forming the substrate 200, the first fins 201 and the second fins 202 includes: providing an initial substrate (not shown); forming a patterned layer (not shown) on the initial substrate (not shown), the patterned layer exposes part of the top surface of the initial substrate; the initial substrate is etched using the patterned layer as a mask to form the substrate 200 and the first fins 201 and the second fin part 202; after the substrate 200, the first fin part 201 and the second fin part 202 are formed, the patterning layer is removed.

In this embodiment, the material of the substrate 200 is silicon; in other embodiments, the material of the substrate may also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium.

In this embodiment, the materials of the first fins 201 and the second fins 202 are silicon; in other embodiments, the materials of the first fins and the second fins may also be Germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium.

Referring to FIG. 3 , an isolation layer 203 is formed on the substrate 200 , the isolation layer 203 covers part of the sidewalls of the first fins 201 and the second fins 202 , and the isolation layer 203 is The top surfaces are lower than the top surfaces of the first fins 201 and the second fins 202 .

In this embodiment, the method for forming the isolation layer 203 includes: forming an initial isolation layer (not shown) on the substrate 200 , and the initial isolation layer covers the first fin portion 201 and the first fin portion 201 and the first isolation layer. Two fins 202 ; etch back the initial isolation layer to form the isolation layer 203 , the top surface of the initial isolation layer 203 is lower than the top surfaces of the first fin 201 and the second fin 202 .

The material of the isolation layer 203 is an insulating material, and the insulating material includes: silicon oxide, silicon nitride or silicon oxynitride; in this embodiment, the material of the isolation layer 203 is silicon oxide.

After forming the isolation layer 203, the method further includes: forming a plurality of first gate structures on the first region I, the first gate structures spanning the first fins 201, and the adjacent ones The first gate structures have a first dimension along the first direction X, the sidewalls of the first gate structures have a first spacer structure, and the first spacer structure is along the first spacer structure. The direction X has a second dimension; a plurality of second gate structures are formed on the second region II, the second gate structures span the second fins 202, and the adjacent second gates There is a third dimension between the structures along the first direction X, the third dimension is smaller than the first dimension, the sidewall of the second gate structure has a second spacer structure, the second side The wall structure has a fourth size along the first direction X, and the fourth size is smaller than the second size; a first source and drain are formed in the first fins 201 on both sides of the first gate structure openings; second source-drain openings are formed in the second fins 201 on both sides of the second gate structure; source-drain doping is simultaneously formed in the first source-drain opening and the second source-drain opening impurity layer until the source-drain doped layer fills the second source-drain opening, the top surface of the source-drain doped layer in the first source-drain opening is lower than the surface of the first fin 201 The top surface, the top surface of the source-drain doped layer located in the second source-drain opening is flush with the top surface of the second fin portion 202 . For the specific process, please refer to FIG. 4 to FIG. 12 .

Referring to FIG. 4 , a first dummy gate structure 204 is formed on the first region I, and the first dummy gate structure 204 spans the first fin portion 201 ; a second dummy gate structure 204 is formed on the second region II A dummy gate structure 205 , the second dummy gate structure 205 spans the second fin portion 202 .

In this embodiment, the first dummy gate structure 204 includes: a first dummy gate dielectric layer, and the first dummy gate dielectric layer covers part of the sidewalls and the top surface of the first fin part 201 , and the first dummy gate dielectric layer is located on the first fin portion 201 . The first dummy gate layer (not marked) on the first dummy gate dielectric layer; the second dummy gate structure 205 includes: a second dummy gate dielectric layer, and the second dummy gate dielectric layer covers the second fin Part of the sidewalls and the top surface of the portion 202, and a second dummy gate layer (not marked) on the second dummy gate dielectric layer.

In this embodiment, the materials of the first dummy gate dielectric layer and the second dummy gate dielectric layer are silicon oxide; in other embodiments, the first dummy gate dielectric layer and the second dummy gate dielectric layer are made of silicon oxide. The material of the gate dielectric layer can also be silicon oxynitride.

In this embodiment, the materials of the first dummy gate layer and the second dummy gate layer are polysilicon.

In this embodiment, the first dummy gate structure 204 and the second dummy gate structure 205 are formed at the same time, and the first dummy gate structure 204 and the second dummy gate structure 205 are simultaneously formed through a global process, which can Effectively improve production efficiency.

In this embodiment, the adjacent first dummy gate structures 204 have a first dimension D1 along the first direction X.

In this embodiment, the adjacent second dummy gate structures 205 have a third dimension D3 along the first direction X, and the third dimension D3 is smaller than the first dimension D1.

Referring to FIG. 5 , a first spacer material layer 206 is formed on the sidewalls and top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205 and the substrate 200 .

In this embodiment, the formation process of the first spacer material layer 206 adopts an atomic layer deposition process.

Referring to FIG. 6 , the first spacer material layer 206 is etched back until the top surfaces of the first dummy gate structure 204 and the second dummy gate structure 205 are exposed to form an initial first spacer 207 .

In this embodiment, the process of etching back the first spacer material layer 206 adopts a dry etching process. In other embodiments, the process of etching back the initial first spacer material layer may also use a wet etching process.

Referring to FIG. 7 , the initial first spacer 207 located on the sidewall of the second dummy gate structure 205 is removed, and the first spacer 208 is formed on the sidewall of the first dummy gate structure 204 .

In this embodiment, the method for removing the initial first spacer 207 located on the sidewall of the second dummy gate structure 205 includes: forming a sacrificial layer (not shown) on the first region I, the A sacrificial layer covers the first dummy gate structure 204 ; after the sacrificial layer is formed, the initial first spacer 207 located on the sidewall of the second dummy gate structure 205 is removed to form the first spacer 208 ; After forming the first spacer 208, the sacrificial layer is removed.

Referring to FIG. 8 , after the first spacer 208 is formed, a second spacer 209 is formed on the sidewall of the first spacer 208 , and a third side is formed on the sidewall of the second dummy gate structure 205 Wall 210.

In this embodiment, the second sidewall 209 and the third sidewall 210 are formed simultaneously.

In this embodiment, the method for forming the second sidewall spacer 209 and the third sidewall spacer 210 includes: forming on the sidewalls of the first sidewall spacer 208 and the second dummy gate structure 205 , the first sidewall spacer A second spacer material layer (not shown) is formed on the top surfaces of a dummy gate structure 204 and the second dummy gate structure 205 and the substrate 200 ; etch back the second spacer material layer, Until the top surfaces of the first dummy gate structures 204 and the second dummy gate structures 205 are exposed, the second sidewall spacers 209 are formed on the sidewalls of the first sidewall spacers 208 and the second sidewall spacers 209 are formed on the sidewalls of the first sidewall spacers 208 The sidewalls of the two dummy gate structures 205 form the third spacer 210 .

In this embodiment, the formation process of the second spacer material layer adopts an atomic layer deposition process.

In this embodiment, the first spacer structure includes: a first spacer 208 located on the sidewall of the first gate structure, and a second spacer 209 located on the sidewall of the first sidewall 208, The first spacer structure has a second dimension D2 along the first direction X; the second spacer structure includes: a third spacer 210 located on the sidewall of the second gate structure 205, the first spacer The two sidewall structures have a fourth dimension D4 along the first direction X, and the fourth dimension D4 is smaller than the second dimension D2. By increasing the second dimension D2 of the first sidewall structure along the first direction X, the first fin portion 201 is further covered, and the first fin portion 201 along the first direction X is reduced The exposed size further reduces the size of the subsequently formed first source-drain opening along the first direction X. When the size of the first source-drain opening decreases along the first direction X, when the source-drain doped layer in the second source-drain opening is filled, it is formed in the first source-drain opening The source-drain doped layer can fill more space, reducing the concavity of the source-drain doped layer in the first source-drain opening at the middle position, thereby reducing the penetration of the subsequently formed conductive layer through the The risk of the middle portion of the source-drain doped layer improves the contact between the conductive layer and the source-drain doped layer in the first source-drain opening, thereby improving the performance of the finally formed semiconductor structure.

Referring to FIG. 9 , after the first spacer structure and the second spacer structure are formed, first source-drain openings are formed in the first fins 201 on both sides of the first dummy gate structure 204 211 ; forming second source-drain openings 212 in the second fins 205 on both sides of the second dummy gate structure 205 .

In this embodiment, the method for forming the first source-drain opening 211 and the second source-drain opening 212 includes: etching the first dummy gate structure 204 and the first spacer structure as a mask In the first fin portion 201, the first source-drain opening 211 is formed in the first fin portion 201; the second dummy gate structure 205 and the second spacer structure are used as masks for etching In the second fin portion 202 , the second source-drain opening 212 is formed in the second fin portion 202 .

In this embodiment, the process of etching the first fins 201 and the second fins 202 adopts a wet etching process; in other embodiments, the first fins and the second fins are etched The process of the two fins may also use a dry etching process.

Referring to FIG. 10 , a source-drain doped layer 213 is simultaneously formed in the first source-drain opening 211 and the second source-drain opening 212 until the source-drain doped layer 213 is fully filled with the second source-drain Up to the opening 212, the top surface of the source-drain doped layer 213 in the first source-drain opening 211 is lower than the top surface of the first fin 201, and the source-drain in the second source-drain opening 212 The top surface of the doped layer 213 is flush with the top surface of the second fin 202 .

In this embodiment, the method for forming the source-drain doped layer 213 includes: using an epitaxial growth process to simultaneously form an epitaxial layer (not shown in the figure) in the first source-drain opening 211 and the second source-drain opening 212 ) until the second source-drain opening 212 is filled with the epitaxial layer; in-situ doping is performed on the epitaxial layer during the epitaxial growth process, and the source-drain ions are doped into the epitaxial layer , forming the source-drain doped layer 213 .

The material of the source and drain doping layer 213 includes: SiP, SiCP, SiGe or SiGeB; in this embodiment, the material of the source and drain doping layer 213 is SiP.

Referring to FIG. 11 , after the source-drain doped layer 213 is formed, a dielectric layer 214 is formed on the substrate 200 , and the dielectric layer covers the first dummy gate structure 204 and the second dummy gate structure 205 sidewall.

In this embodiment, the material of the dielectric layer 214 is silicon oxide; in other embodiments, the material of the dielectric layer may also be a low-K dielectric material (a low-K dielectric material refers to a material with a relative permittivity lower than 3.9). dielectric material) or ultra-low-K dielectric material (ultra-low-K dielectric material refers to a dielectric material with a relative permittivity lower than 2.5).

Referring to FIG. 12, after the dielectric layer 214 is formed, the first dummy gate structure 204 is removed, and a first gate opening is formed in the dielectric layer 214; A second gate opening is formed in the dielectric layer 214; the first gate structure 215 is formed in the first gate opening; and the second gate structure 216 is formed in the second gate opening.

In this embodiment, the first gate structure 215 includes: a first gate dielectric layer and a first gate layer (not shown) on the first gate dielectric layer; the second gate structure 216 Including: a second gate dielectric layer and a second gate layer (not marked) located on the second gate dielectric layer.

In this embodiment, the materials of the first gate dielectric layer and the second gate dielectric layer include high-K dielectric materials.

Materials of the first gate layer and the second gate layer include metals, and the metals include tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the first gate layer and the second gate layer are made of tungsten.

In this embodiment, the first gate structure 215 has a first width dimension d1 along the first direction X, the second gate structure 215 has a second width dimension d2 along the first direction X, The first width dimension d1 is greater than the second width dimension d2.

In this embodiment, the range of the first width dimension d1 is greater than 50 nm; by setting the first width dimension d1 of the first gate structure 215 to be greater than 50 nm, the length of the channel is increased, thereby reducing the channel effect.

Referring to FIG. 13 , after the first gate structure 215 and the second gate structure 216 are formed, a conductive layer 217 is formed on the source-drain doped layer 213 .

In this embodiment, the method for forming the conductive layer 217 includes: forming a conductive opening (not shown) in the dielectric layer 214, and the conductive opening exposes the surface of the source-drain doped layer 213; The conductive layer 217 is formed in the conductive opening.

The material of the conductive layer 217 includes metal, and the metal includes tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. In this embodiment, the material of the conductive layer 217 is copper.

Correspondingly, an embodiment of the present invention further provides a semiconductor structure, please continue to refer to FIG. 13 , including: a substrate 200, the substrate 200 includes a first region I and a second region II, the first region I There are several discrete first fins 201 on the second area II, and there are several mutually discrete second fins 202 on the second area II, the first fins 201 and the second fins 202 are respectively along the first direction X extension; a plurality of first gate structures 215 on the first region I, the first gate structures 215 spanning the first fins 201, and the adjacent first gate structures 215 There is a first dimension D1 along the first direction X, the sidewall of the first gate structure 215 has a first spacer structure, and the first spacer structure has a first spacer structure along the first direction X. Two dimensions D2; a plurality of second gate structures 216 on the second region II, the second gate structures 216 spanning the second fins 202, and adjacent to the second gate structures There is a third dimension D3 along the first direction X between 216, the third dimension D3 is smaller than the first dimension D1, the sidewall of the second gate structure 216 has a second spacer structure, so The second spacer structure has a fourth dimension D4 along the first direction X, and the fourth dimension D4 is smaller than the second dimension D2; the first fins located on both sides of the first gate structure 215 The first source and drain openings 211 in the part 201; the second source and drain openings 212 in the second fin part 202 on both sides of the second gate structure 216; The source-drain doped layer 213 in the second source-drain opening 212, the top surface of the source-drain doped layer 213 in the first source-drain opening 211 is lower than the top surface of the first fin 201, located in The top surface of the source-drain doped layer 213 in the second source-drain opening 212 is flush with the top surface of the second fin 202 .

In this embodiment, through the first gate structure 215 located on the first region I, the sidewall of the first gate structure 215 has a first spacer structure, and the first spacer structure is along the The first direction X has a second dimension D2; the second gate structure 216 located on the second region II has a second spacer structure on the sidewall of the second gate structure 216, and the second gate structure 216 has a second spacer structure. The two sidewall structures have a fourth dimension D4 along the first direction X, and the fourth dimension D4 is smaller than the second dimension D2. By increasing the second dimension D2 of the first sidewall structure along the first direction X, the first fin portion 201 is further covered, and the first fin portion 201 along the first direction X is reduced The exposed size further reduces the size of the formed first source-drain opening 211 along the first direction X. When the size of the first source-drain opening 211 is reduced along the first direction X, when the source-drain doping layer 213 in the second source-drain opening 212 is filled up, the first source-drain doped layer 213 is formed in the first source-drain opening 212 . The source-drain doped layer 213 in the drain opening 211 can fill more space, reducing the concavity of the source-drain doped layer in the first source-drain opening 211 in the middle position, thereby reducing the subsequent formation of the doped layer. The risk of the conductive layer 217 penetrating the middle portion of the source-drain doping layer 213 increases the contact between the conductive layer 217 and the source-drain doping layer 213 in the first source-drain opening 211 , and further Improve the performance of the resulting semiconductor structure.

In this embodiment, it further includes: a conductive layer 217 located on the source-drain doped layer 213 .

In this embodiment, the material of the conductive layer 217 includes metal, and the metal includes tungsten, aluminum, copper, titanium, silver, gold, lead or nickel.

In this embodiment, the first spacer structure includes: a first spacer 208 located on the sidewall of the first gate structure 215 , and a second spacer 209 located on the sidewall of the first sidewall 208 .

In this embodiment, the second spacer structure includes: a third spacer 210 located on the sidewall of the second gate structure 216 .

In this embodiment, the first gate structure 215 has a first width dimension d1 along the first direction X, and the second gate structure 216 has a second width dimension along the first direction X d2, the first width dimension d1 is greater than the second width dimension d2.

The material of the source and drain doping layer 213 includes: SiP, SiCP, SiGe or SiGeB; in this embodiment, the material of the source and drain doping layer 213 is SiP.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (21)

1. a semiconductor structure, is characterized in that, comprises: a substrate, the substrate includes a first region and a second region, the first region has a plurality of mutually discrete first fins, the second region has a plurality of mutually discrete second fins, the the first fin and the second fin respectively extend along the first direction; a plurality of first gate structures located on the first region, the first gate structures spanning the first fins, and the first gate structures adjacent to each other are along the first direction having a first size, a sidewall of the first gate structure has a first spacer structure, and the first spacer structure has a second size along the first direction; a plurality of second gate structures located on the second region, the second gate structures spanning the second fins, and the first direction between the adjacent second gate structures having a third size, the third size being smaller than the first size, a second spacer structure on the sidewall of the second gate structure, and the second spacer structure having a first spacer along the first direction four dimensions, the fourth dimension is smaller than the second dimension; a first source-drain opening in the first fin on both sides of the first gate structure; second source-drain openings in the second fins on both sides of the second gate structure; a source-drain doped layer located in the first source-drain opening and the second source-drain opening, the top surface of the source-drain doped layer located in the first source-drain opening is lower than the first fin The top surface of the source-drain doped layer in the second source-drain opening is flush with the top surface of the second fin. 2 . The semiconductor structure of claim 1 , further comprising: a conductive layer on the source and drain doped layers. 3 . 3 . The semiconductor structure of claim 1 , wherein the material of the conductive layer comprises metal, and the metal comprises: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. 4 . 4 . The semiconductor structure of claim 1 , wherein the first spacer structure comprises: a first spacer located on a sidewall of the first gate structure, and a first spacer located on a side of the first spacer. 5 . second side wall of the wall. 5 . The semiconductor structure of claim 1 , wherein the second spacer structure comprises: a third spacer located on a sidewall of the second gate structure. 6 . 6. The semiconductor structure of claim 1, wherein the first gate structure has a first width dimension along the first direction and the second gate structure has a first width dimension along the first direction The second width dimension of , the first width dimension is larger than the second width dimension. 7 . The semiconductor structure of claim 1 , wherein the material of the source and drain doped layers comprises: SiP, SiCP, SiGe or SiGeB. 8 . 8. A method for forming a semiconductor structure, comprising: A substrate is provided, the substrate includes a first region and a second region, the first region has a plurality of mutually discrete first fins, and the second region has a plurality of mutually discrete second fins, so the first fin portion and the second fin portion respectively extend along the first direction; A plurality of first gate structures are formed on the first region, the first gate structures span the first fins, and the first gate structures adjacent to each other are along the first direction having a first size, a sidewall of the first gate structure has a first spacer structure, and the first spacer structure has a second size along the first direction; A plurality of second gate structures are formed on the second region, the second gate structures span the second fins, and the second gate structures adjacent to each other are along the first direction having a third size, the third size being smaller than the first size, a second spacer structure on the sidewall of the second gate structure, and the second spacer structure having a first spacer along the first direction four dimensions, the fourth dimension is smaller than the second dimension; forming first source-drain openings in the first fins on both sides of the first gate structure; forming second source-drain openings in the second fins on both sides of the second gate structure; A source-drain doped layer is simultaneously formed in the first source-drain opening and the second source-drain opening, until the source-drain doped layer fills the second source-drain opening, at the first source-drain opening. The top surface of the source-drain doped layer in the drain opening is lower than the top surface of the first fin, and the top surface of the source-drain doped layer in the second source-drain opening is flush with the second fin top surface of the part. 9 . The method for forming a semiconductor structure according to claim 8 , wherein after forming the source and drain doped layers, the method further comprises: forming a conductive layer on the source and drain doped layers. 10 . 10 . The method for forming a semiconductor structure according to claim 9 , wherein the material of the conductive layer comprises metal, and the metal comprises: tungsten, aluminum, copper, titanium, silver, gold, lead or nickel. 11 . 11 . The method for forming a semiconductor structure according to claim 8 , wherein the first spacer structure comprises: a first spacer located on the sidewall of the first gate structure, and a first spacer located on the sidewall of the first gate structure. 12 . The second sidewall of the sidewall sidewall. 12 . The method of claim 11 , wherein the second spacer structure comprises: a third spacer located on a sidewall of the second gate structure. 13 . 13 . The method for forming a semiconductor structure according to claim 12 , wherein before forming the first gate structure and the second gate structure, the method further comprises: forming a first gate structure on the first region. 14 . a dummy gate structure, the first dummy gate structure spans the first fin; a second dummy gate structure is formed on the second region, the second dummy gate structure spans the second fin . 14 . The method for forming a semiconductor structure according to claim 13 , wherein the method for forming the first sidewall spacer comprises: forming the first and second dummy gate structures on the sidewalls and the sidewalls of the second dummy gate structure. 15 . forming a first spacer material layer on the top surface and the substrate; etching back the first spacer material layer until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed , forming an initial first spacer; removing the initial first spacer located on the sidewall of the second dummy gate structure, and forming the first spacer on the sidewall of the first dummy gate structure. 15. The method for forming a semiconductor structure according to claim 14, wherein the forming process of the first spacer material layer comprises an atomic layer deposition process. 16 . The method for forming a semiconductor structure according to claim 14 , wherein the method for forming the second spacer and the third spacer comprises: forming the first spacer and the second dummy between the first spacer and the second dummy. forming a second spacer material layer on the sidewall of the gate structure, the top surfaces of the first dummy gate structure and the second dummy gate structure, and the substrate; and etching back the second spacer material layer , until the top surfaces of the first dummy gate structure and the second dummy gate structure are exposed, the second spacer is formed on the sidewalls of the first spacer, and the second dummy gate is formed on the sidewalls of the first spacer The sidewalls of the structure form the third sidewall. 17 . The method of claim 16 , wherein the formation process of the second spacer material layer comprises an atomic layer deposition process. 18 . 18. The method for forming a semiconductor structure according to claim 13, wherein the method for forming the first gate structure and the second gate structure comprises: forming a dielectric layer on the substrate, wherein the the dielectric layer covers the sidewalls of the first dummy gate structure and the second dummy gate structure; the first dummy gate structure is removed, and a first gate opening is formed in the dielectric layer; the second dummy gate structure is removed A dummy gate structure, forming a second gate opening in the dielectric layer; forming the first gate structure in the first gate opening; forming the second gate in the second gate opening Extreme structure. 19. The method of claim 8, wherein the first gate structure has a first width dimension along the first direction, and the second gate structure has a width along the first direction A second width dimension in the first direction, the first width dimension being larger than the second width dimension. 20 . The method for forming a semiconductor structure according to claim 8 , wherein the method for forming the source-drain doped layer comprises: using an epitaxial growth process to form the first source-drain opening and the second source-drain opening. 21 . An epitaxial layer is formed in the opening at the same time until the epitaxial layer fills the second source and drain openings; in the epitaxial growth process, the epitaxial layer is doped in-situ, and the epitaxial layer is doped with all the The source-drain ions form the source-drain doped layer. 21. The method for forming a semiconductor structure according to claim 8, wherein the material of the source and drain doped layers comprises: SiP, SiCP, SiGe or SiGeB.

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