CN109599366B - Semiconductor device and method of forming the same - Google Patents

Abstract

A semiconductor device and a method for forming the same, wherein the method includes: providing a semiconductor substrate with a first fin on the semiconductor substrate; forming a first initial doped layer in the first fin; performing a groove treatment process, so that The first initial doped layer forms a first doped layer, the first doped layer has a groove, the top surface of the first doped layer exposes the groove, and the groove is in the width direction of the first fin. The sidewall surfaces on both sides are the surfaces of the first doped layer; the first metal silicide layer is formed on the outer sidewall and top surface of the first doped layer and the inner wall surface of the groove. The method improves the performance of semiconductor devices.

Description

Semiconductor device and method of forming the same

technical field

The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor device and a forming method thereof.

Background technique

MOS (Metal-Oxide-Semiconductor) transistors are one of the most important components in modern integrated circuits. The basic structure of the MOS transistor includes: a semiconductor substrate; a gate structure located on the surface of the semiconductor substrate, and the gate structure includes: a gate dielectric layer located on the surface of the semiconductor substrate and a gate electrode layer located on the surface of the gate dielectric layer; The source and drain doped regions in the semiconductor substrate on both sides of the pole structure.

With the development of semiconductor technology, the ability of the traditional planar MOS transistor to control the channel current becomes weaker, resulting in serious leakage current. Fin Field Effect Transistor (Fin FET) is an emerging multi-gate device, which generally includes a fin protruding from the surface of the semiconductor substrate, and a gate structure covering part of the top surface and sidewall of the fin, located at The source and drain doped regions in the fins on both sides of the gate structure.

However, the performance of semiconductor devices composed of fin field effect transistors in the prior art still needs to be improved.

Contents of the invention

The problem to be solved by the invention is to provide a semiconductor device and its forming method to improve the performance of the semiconductor device.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, comprising: providing a semiconductor substrate having a first fin; forming a first initial doped layer located in the first fin; Groove treatment process, making the first initial doped layer form a first doped layer, the first doped layer has a groove, the top surface of the first doped layer exposes the groove, and the groove is in the first The sidewall surfaces on both sides of the fin width direction are the surfaces of the first doped layer; the first metal silicide layer is formed on the outer sidewall and top surface of the first doped layer and the inner wall surface of the groove.

Optionally, it also includes: before performing the groove treatment process, forming a first fin sidewall, the first fin sidewall is located on both sidewalls of the first initial doped layer in the width direction of the first fin and The top surface of the first initial doped layer is exposed; the step of performing the groove treatment process includes: etching back part of the first initial doped layer to reduce the height of the first initial doped layer, so that the first initial doped layer The layer forms a first transitional doping layer, and the first transitional doping layer has a depression located in the first fin, and the sidewalls on both sides of the depression in the width direction of the first fin have first fin sidewalls; The sidewall of the recess forms a mask sidewall, and the mask sidewall is in contact with the first fin sidewall; the first transition doped layer is etched using the mask sidewall and the first fin sidewall as a mask, so that The first transitional doped layer forms the first doped layer; after etching the first transitional doped layer using the mask sidewall and the first fin sidewall as a mask, the mask sidewall is removed; the semiconductor The device forming method further includes: removing the first fin sidewall after etching the first transition doped layer by using the mask sidewall and the first fin sidewall as a mask; removing the first fin sidewall and the mask sidewall , forming the first metal silicide layer.

Optionally, it also includes: before forming the first initial doped layer, forming an isolation layer covering the sidewall of the first fin part on the semiconductor substrate, the first fin exposed by the isolation layer includes the first A replacement region; the method for forming the first fin sidewall and the first initial doped layer includes: forming a first fin sidewall on the surface of the isolation layer on the sidewall of the first replacement region; etching and removing the first fin sidewall Covering the first replacement region, forming a first initial replacement groove in the first fin, and in the width direction of the first fin, the sidewalls on both sides of the first initial replacement groove respectively have first fin sidewalls; etching the second The first fin sidewall of the inner wall of an initial replacement groove is used to increase the size of the first initial replacement groove in the width direction of the first fin to form a first replacement groove; the first initial doping is formed in the first replacement groove layer.

Optionally, the material of the first fin sidewall is SiN, SiCN, SiBN or SiON; the material of the mask sidewall is SiN, SiCN, SiBN or SiON.

Optionally, the thickness of the mask sidewall is 2nm˜10nm.

Optionally, the thickness of the first fin sidewall is 2nm˜8nm.

Optionally, the step of forming a mask sidewall on the sidewall of the recess includes: forming a mask sidewall material layer on the sidewall and bottom of the recess, the surface of the first fin sidewall and the semiconductor substrate; etching back The mask sidewall material layer is etched until the top surface of the first transition doped layer and the top surface of the first fin sidewall are exposed to form the mask sidewall.

Optionally, the process of etching the first transition doped layer by using the mask sidewall and the first fin sidewall as a mask includes an anisotropic dry etching process.

Optionally, the etching depth of the first transition doped layer occupies 20%-100% of the thickness of the first transition doped layer by using the mask sidewall and the first fin sidewall as a mask.

Optionally, the depth of etching back part of the first initial doped layer is 3nm˜10nm.

Optionally, the first fin sidewall is removed during the process of removing the mask sidewall.

Optionally, the cross-sectional shape of the groove in the width direction of the first fin includes a "U" shape.

Optionally, it also includes: before forming the first initial doped layer, forming a first gate structure across the first fin on the semiconductor substrate, the first gate structure covering part of the first fin The top surface and part of the sidewall surface; the first initial doped layer is respectively located in the first fins on both sides of the first gate structure; after the first doped layer is formed, the first doped layer is respectively located in the first gate structure in the first fins on both sides.

Optionally, the semiconductor substrate includes a first region and a second region, the first fin is located on the first region of the semiconductor substrate, and the second region of the semiconductor substrate has a second fin; the formation of the semiconductor device The method further includes: before forming the first initial doped layer, forming a second doped layer located in the second fin; after forming the first doped layer, forming a second doped layer on the surface of the second doped layer Two metal silicide layers.

Optionally, the semiconductor substrate has an isolation layer covering part of the sidewall of the second fin, and the second fin exposed by the isolation layer includes a second replacement region; the method for forming the semiconductor device further includes: Form a second fin sidewall on the surface of the isolation layer on the sidewall of the second replacement region of the second fin; etch to remove the second replacement region covered by the second fin sidewall, and form a second initial replacement in the second fin In the groove, in the width direction of the second fin, the sidewalls on both sides of the second initial displacement groove respectively have second fin sidewalls; the second fin sidewalls on the inner wall of the second initial displacement groove are etched to increase the second initial displacement The size of the groove in the width direction of the second fin forms a second replacement groove; a second doped layer is formed in the second replacement groove; after removing the second fin sidewall of the second doped layer sidewall, the formation of the the second metal silicide layer.

Optionally, the first region is used to form N-type transistors, and the second region is used to form P-type transistors.

Optionally, after forming the first initial doped layer and before performing the groove treatment process, an underlying dielectric layer is formed, and the underlying dielectric layer is located between the semiconductor substrate, the first initial doped layer and the second doped layer. layer; form a first dielectric opening that penetrates the underlying dielectric layer in the underlying dielectric layer, and the first dielectric opening is located on the first initial doped layer; form a second dielectric opening that penetrates the underlying dielectric layer in the underlying dielectric layer, and the second The dielectric opening is located on the second doped layer; after the first dielectric opening and the second dielectric opening are formed, the groove treatment process is performed; after the groove treatment process is performed, on the outer sidewall and top of the first doped layer A first metal silicide layer is formed on the surface and the inner wall of the groove, and a second metal silicide layer is formed on the top surface and the side wall surface of the second doped layer.

Optionally, the method further includes: after forming the first metal silicide layer and the second metal silicide layer, forming a first plug in the first dielectric opening, and forming a second plug in the second dielectric opening.

The present invention also provides a semiconductor device, comprising: a semiconductor substrate with a first fin; a first doped layer located in the first fin, with a groove in the first doped layer, the The top surface of the first doped layer exposes a groove, and the sidewall surfaces on both sides of the groove in the width direction of the first fin are the surfaces of the first doped layer; located on the outer sidewall and the top surface of the first doped layer , and the first metal silicide layer on the inner wall surface of the groove.

Optionally, the cross-sectional shape of the groove in the width direction of the first fin includes a "U" shape.

Compared with the prior art, the technical solution of the present invention has the following advantages:

In the method for forming a semiconductor device provided by the technical solution of the present invention, after the groove treatment process is performed, the first initial doped layer is formed into a first doped layer, the first doped layer has grooves, and the first doped layer The top surface of the layer exposes the grooves, thus making the surface area of the first doped layer larger than the surface area of the first initially doped layer. Since the sidewall surfaces on both sides of the groove in the width direction of the first fin are the surfaces of the first doped layer, the area of the sidewall of the groove is larger, thereby making the surface area of the first doped layer larger . The contact area between the first metal silicide layer and the first doped layer is relatively large. The cross-sectional area in the current conduction direction from the first doped layer to the first metal silicide layer is larger, thereby reducing the contact resistance between the first metal silicide layer and the first doped layer, thereby improving the Improve the performance of semiconductor devices.

In the semiconductor device provided by the technical solution of the present invention, the first doped layer has a groove, and the top surface of the first doped layer exposes the groove. The sidewall surfaces on both sides of the groove in the width direction of the first fin are the surfaces of the first doped layer, so the surface area of the first doped layer is larger, and the first metal silicide layer and the first doped layer The area of layer contact is larger. The cross-sectional area in the current conduction direction from the first doped layer to the first metal silicide layer is larger, thereby reducing the contact resistance between the first metal silicide layer and the first doped layer, thereby improving the Improve the performance of semiconductor devices.

Description of drawings

1 to 22 are structural schematic diagrams of the process of forming a semiconductor device in an embodiment of the present invention.

Detailed ways

As mentioned in the background, semiconductor devices formed in the prior art have poor performance.

A method for forming a semiconductor device, comprising: providing a semiconductor substrate with fins on the semiconductor substrate; forming a gate structure across the fins on the semiconductor substrate; fins on the fins on both sides of the gate structure Form a source-drain doped layer; form an interlayer dielectric layer on the source-drain doped layer and the gate structure; form an exposed source-drain doped layer side wall surface and top in the interlayer dielectric layer on both sides of the gate structure Opening on the surface; etching the source-drain doped layer at the bottom of the opening to form a groove in the source-drain doped layer; after that, forming a metal silicide layer on the sidewall and top surface of the source-drain doped layer; forming a metal silicide layer Then, a plug is formed in the opening.

However, the performance of the semiconductor device formed by the above-mentioned method is relatively poor. After research, it is found that the reasons are:

The function of the metal silicide layer is to reduce the contact barrier between the source-drain doped layer and the plug. A groove is formed in the doped source and drain layer at the bottom of the opening to increase the total surface of the doped source and drain layer exposed by the opening, thereby increasing the contact area between the metal silicide layer and the doped source and drain layer.

Before etching the source-drain doped layer at the bottom of the opening, the opening exposes the sidewall surface and the top surface of the source-drain doped layer. After etching the doped source and drain layer at the bottom of the opening, the formed groove at least penetrates the doped source and drain layer in the width direction of the fin, that is, the bottom surface of the groove and the outer side of the doped source and drain layer in the width direction of the fin The walls are connected.

On this basis, with the continuous reduction of the feature size of semiconductor devices, the distance between adjacent gate structures is continuously reduced, and correspondingly, the size of the source-drain doped region in the channel length direction is continuously reduced. As a result, the total contact area between the source-drain doped region and the metal silicide layer is reduced, which in turn leads to a larger contact resistance between the source-drain doped region and the metal silicide layer.

In order to solve the above problems, the present invention provides a method for forming a semiconductor device, including: forming a first initial doped layer located in the first fin; performing a groove treatment process, so that the first initial doped layer forms a first doped layer The impurity layer has a groove in the first doped layer, the top surface of the first doped layer exposes the groove, and the sidewall surfaces on both sides of the groove in the width direction of the first fin are first doped The surface of the layer; a first metal silicide layer is formed on the outer sidewall and top surface of the first doped layer and the inner wall surface of the groove. The method improves the performance of semiconductor devices.

In order to make the above objects, features and advantages of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

1 to 22 are structural schematic diagrams of the process of forming a semiconductor device in an embodiment of the present invention.

With reference to Fig. 1 and Fig. 2, the view of the first area in Fig. 2 is a sectional view along the cutting line M1-M2 in Fig. 1, and the view of the second area in Fig. 2 is along the cutting line N1-N2 in Fig. 1 A cross-sectional view of a semiconductor substrate 100 is provided, and the semiconductor substrate 100 has a first fin 111 thereon.

In this embodiment, the semiconductor device is taken as an example of a fin field effect transistor. In other embodiments, the semiconductor device is a triode or a diode.

The semiconductor substrate 100 may be single crystal silicon, polycrystalline silicon or amorphous silicon. The semiconductor substrate 100 may also be made of semiconductor materials such as silicon, germanium, and silicon germanium. In this embodiment, the material of the semiconductor substrate 100 is single crystal silicon.

The semiconductor substrate 100 includes a first region A, and the first fin 111 is located on the first region A of the semiconductor substrate 100 . The semiconductor substrate 100 also includes a second region B. As shown in FIG. There is a second fin 112 on the second region B of the semiconductor substrate 100 .

In other embodiments, the semiconductor substrate does not include the second region.

In this embodiment, the first region A is used to form an N-type fin field effect transistor, and the second region B is used to form a P-type fin field effect transistor.

The material of the first fin portion 111 and the second fin portion 112 is single crystal silicon or single crystal silicon germanium. In this embodiment, there are several first fins 111 and several second fins 112 . In other embodiments, there is one first fin 111 and one second fin 112 .

In this embodiment, it further includes: forming an isolation layer 103 covering part of the sidewalls of the first fin 111 and part of the sidewall of the second fin 112 on the semiconductor substrate 100, the top surface of the isolation layer 103 being lower than the first The top surface of the fin 111 and the top surface of the second fin 112 . The material of the isolation layer 103 includes silicon oxide.

The first fin 111 exposed by the isolation layer 103 includes a first replacement region and a first non-replacement region. The direction from the region to the first non-replacement region is parallel to the extending direction of the first fin 111 . The second fin 112 exposed by the isolation layer 103 includes a second replacement region and a second non-replacement region. The direction from the region to the second non-replacement region is parallel to the extending direction of the second fin 112 .

Continuing to refer to FIG. 1 and FIG. 2 , a first gate structure 121 is formed on the semiconductor substrate 100 and the isolation layer 103 , the first gate structure 121 spans the first non-replacement region of the first fin 111 and covers the first The top surface and the sidewall surface of the first non-replacement region of a fin portion 111; the second gate structure 122 is formed on the semiconductor substrate 100 and the isolation layer 103, and the second gate structure 122 straddles the second fin portion 112 Two non-replacement regions cover the top surface and the sidewall surface of the second non-replacement region of the second fin portion 112 .

The first gate structure 121 includes a first gate dielectric layer across the first fin portion 111 and a first gate electrode layer on the first gate dielectric layer. The second gate structure 122 includes a second gate dielectric layer across the second fin portion 112 and a second gate electrode layer on the second gate dielectric layer. The first gate dielectric layer is located on a part of the surface of the isolation layer 103 in the first region A, and covers the top surface and the sidewall surface of the first non-replacement region of the first fin 111 . The second gate dielectric layer is located on a part of the surface of the isolation layer 103 in the second region B and covers the top surface and the sidewall surface of the second non-replacement region of the second fin 112 .

In this embodiment, the material of the first gate dielectric layer and the second gate dielectric layer is silicon oxide. In other embodiments, the material of the first gate dielectric layer and the second gate dielectric layer is a high-K dielectric material (K greater than 3.9). The material of the first gate electrode layer and the second gate electrode layer is polysilicon.

In this embodiment, the top surface of the first gate structure 121 further has a first gate protection layer 131 , and the top surface of the second gate structure 122 further has a second gate protection layer 132 . The material of the first gate protection layer 131 and the second gate protection layer 132 is SiN, SiCN, SiBN or SiON.

Next, a first initial doped layer located in the first fin portion 111 is formed.

In this embodiment, it also includes: before performing the subsequent groove treatment process, forming first fin sidewalls, the first fin sidewalls are located on both sides of the first initial doping layer in the width direction of the first fin portion 111 sidewalls and expose the top surface of the first initial doped layer. The method for forming the first fin sidewall and the first initial doped layer includes: forming a first fin sidewall on the surface of the isolation layer 103 on the sidewall of the first replacement region; etching and removing the first fin sidewall covered by the first fin sidewall. A replacement region, forming a first initial replacement groove in the first fin portion 111, in the width direction of the first fin portion 111, the sidewalls on both sides of the first initial replacement groove respectively have first fin sidewalls; etching the first The first fin sidewall of the inner wall of the initial replacement groove is used to increase the size of the first initial replacement groove in the width direction of the first fin 111 to form a first replacement groove; the first initial doping is formed in the first replacement groove layer.

In this embodiment, it further includes: before forming the first initial doped layer and the first fin sidewall, forming a second doped layer located in the second fin portion 112 .

In this embodiment, it also includes: forming a second fin sidewall located on the surface of the isolation layer 103 on the sidewall of the second replacement region of the second fin part 112; etching and removing the second replacement region covered by the second fin sidewall; A second initial replacement groove is formed in the second fin portion 112. In the width direction of the second fin portion 112, the sidewalls on both sides of the second initial replacement groove respectively have second fin sidewalls; the inner wall of the second initial replacement groove is etched. The second fin sidewall is used to increase the size of the second initial replacement groove in the width direction of the second fin portion 112 to form a second replacement groove; form a second doped layer in the second replacement groove; remove the second doped layer sidewall of the second fin sidewall.

Referring to FIG. 3 and FIG. 4 together, FIG. 3 is a schematic diagram based on FIG. 1 , and FIG. 4 is a schematic diagram based on FIG. 2 . 111 the surface of the first replacement region, the first gate structure 121 and the sidewall of the first gate protection layer 131, the top of the first gate protection layer 131, the second fin 112 the surface of the second replacement region, the second gate structure 122 and the sidewall of the second gate protection layer 132, and the top of the second gate protection layer 132 to form a first sidewall film 140; etch back the first sidewall film 140 of the second region B until the second region B is exposed Layer 103, the second gate protection layer 132 and the top surface of the second fin portion 112 form a second fin sidewall 142 and a second gate sidewall 141, and the second fin sidewall 142 is located in the second replacement region of the second fin portion 112 The sidewalls are located on the surface of the isolation layer 103 , and the second gate spacers 141 are located on the sidewalls of the second gate structure 122 .

In this embodiment, it also includes: before etching back the first sidewall film 140 in the second region B, forming a first mask layer on the first region A, the first mask layer covering the first mask layer in the first region A One side wall film 140, and the first mask layer does not cover the first side wall film 140 of the second region B; use the first mask layer as a mask to etch the first side wall film 140 of the second region B until exposed The top surfaces of the second region B isolation layer 103 , the second gate protection layer 132 and the second fin portion 112 are formed to form a second fin spacer 142 and a second gate spacer 141 .

The material of the first sidewall film 140 is SiN, SiCN, SiBN or SiON. The process for forming the first sidewall film 140 is a deposition process, such as a plasma chemical vapor deposition process or an atomic layer deposition process.

The material of the first mask layer includes photoresist.

Referring to FIG. 5 and FIG. 6 together, FIG. 5 is a schematic diagram based on FIG. 3, and FIG. 6 is a schematic diagram based on FIG. A second initial replacement groove (not shown) is formed in the portion 112. In the width direction of the second fin portion 112, the sidewalls on both sides of the second initial replacement groove respectively have second fin sidewalls 142; the second initial replacement groove is etched. The second fin sidewall 142 on the inner wall of the groove increases the size of the second initial replacement groove in the width direction of the second fin portion 112 to form a second replacement groove; a second doped layer 182 is formed in the second replacement groove.

Specifically, after etching the first spacer film 140 in the second region B by using the first mask layer as a mask, the second replacement film covered by the second fin spacer 142 is etched and removed by using the first mask layer as a mask. area to form a second initial replacement groove; use the first mask layer as a mask to etch the second fin sidewall 142 on the inner wall of the second initial replacement groove to increase the width of the second initial replacement groove in the direction of the width of the second fin 112 Afterwards, the first mask layer is removed; after the first mask layer is removed, the second doped layer 182 is formed. The process of etching the second fin sidewall 142 on the inner wall of the second initial displacement trench is a wet etching process.

The process of forming the second doped layer 182 includes an epitaxial growth process. The second doped layer 182 is respectively located in the second fin portion 112 on both sides of the second gate structure 122 .

In this embodiment, the material of the second doped layer 182 is silicon germanium doped with second ions, and the conductivity type of the second ions is P type.

The second initial replacement groove is formed by removing the second replacement region covered by the second fin sidewall 142. The second replacement groove is formed to expand the size of the second initial replacement groove in the width direction of the second fin portion 112. The second doping Layer 182 is formed in the second displacement trench. Therefore, the size of the second doped layer 182 in the width direction of the second fin portion 112 is larger than the width of the second replacement region of the second fin portion 112 , so that the surface area of the second doped layer 182 increases. Because during the formation of the second doped layer 182 , the second fin sidewall 142 limits the formation space of the second doped layer 182 , thus preventing the second doped layer 182 from protruding outward along the width direction of the second fin portion 112 , Furthermore, the distance between adjacent edges of the second doped layer 182 in the width direction of the second fin portion 112 is prevented from being too small. The material of the subsequent second plug and the second metal silicide layer can easily fill the area between the adjacent second doped layers 182 in the width direction of the second fin 112 .

Referring to FIG. 7 and FIG. 8 in conjunction, FIG. 7 is a schematic diagram based on FIG. 5, and FIG. 8 is a schematic diagram based on FIG. 6. After the second doped layer 182 is formed, on the surface of the isolation layer 103 in the second region B, The surface of the second fin spacer 142 and the second doped layer 182, the top of the second gate protective layer 132, the surface of the second gate spacer 141, and the surface of the first spacer film 140 of the first region A form the second side. Wall film 190.

The material and forming method of the second side wall film 190 refer to the material and forming method of the first side wall film 140 .

Referring to FIG. 9 and FIG. 10 together, FIG. 9 is a schematic diagram based on FIG. 7 , and FIG. 10 is a schematic diagram based on FIG. 8 , etching back the second side wall film 190 and the first side wall film in the first region A. 140 until the surface of the isolation layer 103 of the first region A is exposed, as well as the top surface of the first gate protection layer 131 and the first fin portion 111, forming the first fin sidewall 191 and the first gate sidewall 192, and the first fin sidewall The wall 191 is located on the sidewall of the first replacement region of the first fin 111 and on the surface of the isolation layer 103 , and the first gate spacer 192 is located on the sidewall of the first gate structure 121 .

In this embodiment, it also includes: before etching back the second side wall film 190 and the first side wall film 140 of the first area A, forming a second mask layer on the second area B, the second mask layer The second sidewall film 190 of the second region B is covered, and the second mask layer does not cover the second sidewall film 190 of the first region A. The second sidewall film 190 and the first sidewall film 140 of the first region A are etched using the second mask layer as a mask to form a first fin spacer 191 and a first gate spacer 192 . The material of the second mask layer refers to the material of the first mask layer.

In this embodiment, the first gate spacer 192 includes a first sub-gate spacer 140 a located on a sidewall of the first gate structure 121 , and a second sub-gate spacer 190 a located on a sidewall of the first sub-gate spacer 140 a. Wherein, the first sub-gate spacer 140 a is formed by the first sidewall film 140 in the first region A, and the second sub-gate spacer 190 a is formed by the second sidewall film 190 in the first region A.

In this embodiment, the first fin sidewall 191 includes a first sub-fin sidewall 140b located on the sidewall of the first replacement region of the first fin portion 111 and located on the surface of the isolation layer 103, and a first sub-fin sidewall 140b located on the side of the first sub-fin sidewall 140b. The second sub-fin sidewall 190b of the wall. Wherein, the first sub-fin sidewall 140 b is formed by the first sidewall film 140 in the first region A, and the second sub-fin sidewall 190 b is formed by the second sidewall film 190 in the first region A.

Referring to FIG. 11 and FIG. 12 together, FIG. 11 is a schematic diagram based on FIG. 9, and FIG. 12 is a schematic diagram based on FIG. Form the first initial replacement groove, in the width direction of the first fin portion 111, the sidewalls on both sides of the first initial replacement groove respectively have first fin sidewalls 191; etch the first fin side of the inner wall of the first initial replacement groove The wall 191 increases the size of the first initial replacement groove in the width direction of the first fin portion 111 to form a first replacement groove; the first initial doped layer 181 is formed in the first replacement groove.

Specifically, after etching the second side wall film 190 and the first side wall film 140 of the first region A by using the second mask layer as a mask, the first fin side is etched and removed by using the second mask layer as a mask. The first replacement area covered by the wall 191; using the second mask layer as a mask to etch the first fin sidewall 191 on the inner wall of the first initial replacement groove to increase the width direction of the first initial replacement groove in the first fin portion 111 Afterwards, the second mask layer is removed; after removing the second mask layer, the first initial doped layer 181 is formed. The process of etching the first fin sidewall 191 on the inner wall of the first initial displacement trench is a wet etching process.

The process of forming the first initial doped layer 181 includes an epitaxial growth process. The first initial doped layer 181 is respectively located in the first fin portion 111 on both sides of the first gate structure 121 . In this embodiment, the material of the first initial doping layer 181 is silicon doped with first ions, and the conductivity type of the first ions is N type.

The thickness of the first fin sidewall 191 on the sidewall of the first initial doped layer 181 is 2 nm˜8 nm.

In the process of forming the first initial doped layer 181 , the first fin sidewall 191 limits the formation space of the first initial doped layer 181 , preventing the first initial doped layer 181 from protruding outward along the width direction of the first fin portion 111 , so as to prevent the distance between adjacent edges of the first initial doped layer 181 in the width direction of the first fin portion 111 from being too small. The material of the subsequent first plug and the first metal silicide layer can easily fill the area between the adjacent first doped layers in the width direction of the first fin 111 .

13 and FIG. 14 in combination, FIG. 13 is a schematic diagram based on FIG. 11, and FIG. 14 is a schematic diagram based on FIG. 12. After forming the first initial doped layer 181, a bottom dielectric layer 211 is formed. The layer 211 is located on the semiconductor substrate 100, the first initial doped layer 181 and the second doped layer 182; a first dielectric opening 231 penetrating through the underlying dielectric layer 211 is formed in the underlying dielectric layer 211, and the first dielectric opening 231 is located at the second On an initial doped layer 181 ; a second dielectric opening 232 penetrating through the bottom dielectric layer 211 is formed in the bottom dielectric layer 211 , and the second dielectric opening 232 is located on the second doped layer 182 .

Specifically, after the first initial doped layer 181 is formed, an underlying dielectric layer 211 is formed, and the underlying dielectric layer 211 is located on the isolation layer 103 in the first region A, the first fin sidewall 191 and the first initial doped layer 181, and the sidewalls of the first gate spacers 191, the underlying dielectric layer 211 is also located on the isolation layer 103 in the second region B, the second fin spacers 142 and the second doped layer 182, and the sidewalls of the second gate spacers 141 ; In the process of forming the underlying dielectric layer 211, the first gate protection layer 131 and the second gate protection layer 132 are removed, exposing the top surface of the first gate structure 121 and the top surface of the second gate structure 122; forming the bottom dielectric layer After layer 211, the first gate structure 121 is removed, the first gate opening is formed in the underlying dielectric layer 211 in the first region A, the second gate structure 122 is removed, and the second gate is formed in the underlying dielectric layer 211 in the second region B. Opening; a first metal gate structure 221 is formed in the first gate opening, and a second metal gate structure 222 is formed in the second gate opening; in the first metal gate structure 221, the first gate spacer 191, the second The top dielectric layer 212 is formed on the metal gate structure 222, the second gate spacer 141 and the bottom dielectric layer 211, and the top dielectric layer 212 and the bottom dielectric layer 211 form an interlayer dielectric layer 210; on both sides of the first metal gate structure 221 The first dielectric opening 231 penetrating through the interlayer dielectric layer 210 is formed in the interlayer dielectric layer 210, and the first initial doped layer 181 and the first fin spacer 191 are located at the bottom of the first dielectric opening 231; A second dielectric opening 232 penetrating through the interlayer dielectric layer 210 is formed in the interlayer dielectric layer 210 on both sides of the pole structure 222 , and the second doped layer 182 and the second fin spacer 142 are located at the bottom of the second dielectric opening 232 .

After the first metal gate structure 221 is formed, the first initial doped layer 181 is respectively located in the first fins 111 on both sides of the first metal gate structure 221 . After the second metal gate structure 222 is formed, the second doped layer 182 is respectively located in the second fins 112 on both sides of the second metal gate structure 122 .

After the first dielectric opening 231 and the second dielectric opening 232 are formed, a groove treatment process is performed, so that the first initial doped layer 181 forms a first doped layer, the first doped layer has grooves, and the first doped layer 181 forms a first doped layer. The top surface of the impurity layer exposes a groove, and the sidewall surfaces on both sides of the groove in the width direction of the first fin portion 111 are surfaces of the first doped layer.

In this embodiment, after the first dielectric opening 231 and the second dielectric opening 232 are formed, and before the groove treatment process is performed, the sidewall of the second doped layer 182 has the second fin sidewall 142, and the second doped layer Layer 182 and second fin sidewall 142 have a second sidewall film 190 thereon.

During the groove processing process, the second sidewall film 190 and the second fin spacer 142 in the second region B can protect the second doped layer 182 . The first dielectric opening 231 also exposes the isolation layer 103 of the first region A before the groove treatment process is performed.

The process of the groove treatment process will be described in detail below with reference to FIGS. 15 to 18 .

Referring to FIG. 15, FIG. 15 is a schematic diagram based on FIG. 14. Part of the first initial doped layer 181 is etched back to reduce the height of the first initial doped layer 181, so that the first initial doped layer 181 forms a first transition Doped layer 184, the first transition doped layer 184 has a recess 240 located in the first fin portion 111, and the side walls of the recess 240 in the width direction of the first fin portion 111 have first fin sidewalls 191 .

The depth of etching back part of the first initial doped layer 181 is 3nm˜10nm. If the depth of etching the first initial doped layer 181 is too large, the height of the first transitional doped layer 184 will be smaller, and the sidewall height of the first doped layer formed by the first transitional doped layer 184 will be smaller. , the increase in the total area of the first doped layer surface will be affected; if the depth of etching the first initial doped layer 181 is too small, the depth of the recess 240 will be small, and the depth of the recess 240 determines the subsequent mask side The height of the wall causes the height of the mask sidewall to be too small, and the function of the mask sidewall as a mask for etching the first transition doped layer 184 is reduced.

The process of etching back part of the first initial doped layer 181 to reduce the height of the first initial doped layer 181 is a dry etching process, and the parameters include: the gas used includes fluorocarbon-based gas.

Referring to FIG. 16 , a mask spacer 250 is formed on a sidewall of the recess 240 , and the mask spacer 250 is in contact with the first fin spacer 191 .

The material of the mask spacer 250 is SiN, SiCN, SiBN or SiON.

The thickness of the mask sidewall 250 is 2nm˜10nm. The thickness of the mask spacer 250 refers to the size of the mask spacer 250 in the width direction of the first fin 111 . The significance of choosing this range for the thickness of the mask sidewall 250 is that if the thickness of the mask sidewall 250 is greater than 10 nm, the distance between the mask sidewall 250 on both sides of the recess 240 in the width direction of the first fin 111 Smaller, the area of the first transitional doped layer 184 exposed by the mask spacer 250 is smaller, the process window for subsequent etching of the first transitional doped layer 184 to form the first doped layer is smaller, and the subsequent etching During the process of the first transitional doped layer 184, it is difficult for the etching gas to reach the etching region, resulting in the limitation of the etching depth of the first transitional doped layer 184; During the process of etching the first transition doped layer 184, the masking effect of the mask spacer 250 is relatively small.

The step of forming the mask sidewall 250 on the sidewall of the recess 240 includes: forming a mask sidewall material layer on the sidewall and bottom of the recess 240, the surface of the first fin sidewall 191 and the semiconductor substrate 100; The mask spacer material layer is etched until the top surface of the first transition doped layer 184 and the top surface of the first fin spacer 191 are exposed to form the mask spacer 250 .

It should be noted that, in the process of forming the mask sidewall 250, the outer sidewall of the first fin sidewall 191, the sidewall of the first dielectric opening 231, the sidewall of the first dielectric opening 231, the second sidewall Part of the surface of the wall film 190 forms the material of the mask sidewall 250 , and after the recess processing process is performed, the corresponding material of the mask sidewall 250 is removed.

Referring to FIG. 17, the first transition doped layer 184 is etched using the mask spacer 250 and the first fin spacer 191 as a mask, so that the first transition doped layer 184 forms a first doped layer 183, and the first doped There is a groove in the layer 183, and the top surface of the first doped layer 183 exposes the groove, and the sidewall surfaces on both sides of the groove in the width direction of the first fin portion 111 are the surface of the first doped layer 183 .

The process of etching the first transition doped layer 184 using the mask spacer 250 and the first fin spacer 191 as a mask includes an anisotropic dry etching process, and the parameters include: the gas used includes fluorocarbon-based gas.

In one embodiment, the etching depth of the first transitional doped layer 184 occupies 20%-100% of the thickness of the first transitional doped layer 184 by using the mask sidewall 250 and the first fin sidewall 191 as a mask. The thickness of a transition doped layer 184 is the dimension along the normal direction of the surface of the semiconductor substrate 100 . The significance of choosing this range is: if the depth of etching the first transitional doped layer 184 occupies the thickness of the first transitional doped layer 184 is less than 20%, resulting in the first doped layer 183 surface area relative to the first transitional doped layer 184 The surface area is increased to a lesser extent, and the contact resistance between the first doped layer 183 and the subsequent first metal silicide layer is lowered to a lesser extent.

In this embodiment, the cross-sectional shape of the groove in the first doped layer 183 in the width direction of the first fin 111 is "U". In other implementations, the cross-sectional shape of the groove in the first doped layer along the width direction of the first fin is other shapes.

For the case where the top surface of the first doped layer protrudes outward, the increase in the surface area of the first doped layer is limited by the growth rate of the first doped layer in the direction normal to the (100) crystal plane. However, in this embodiment, the first doped layer 183 with the groove is formed by etching the first transition doped layer 184, so the depth of the groove can be controlled by the etching process, and the first doped layer The increase of the surface area of the layer 183 does not need to be limited by the growth rate of the first doped layer 183 , the depth of the groove can be made deeper, which is beneficial to the increase of the surface area of the first doped layer 183 .

In this embodiment, the first region A is used to form an N-type fin field effect transistor, the second region B is used to form a P-type fin field effect transistor, and the material of the first doped layer 183 is doped first ions of silicon, the material of the second doped layer 182 is silicon germanium doped with the second ions. Correspondingly, the groove is only formed in the first doped layer 183, and the corresponding groove is not formed in the second doped layer 183, thus avoiding the impact of the second doped layer 183 on the P-type fin field effect transistor. The stress loss in the channel avoids reducing the mobility of carriers in the channel of the P-type fin field effect transistor due to the stress loss.

Referring to FIG. 18 , after etching the first transition doped layer 184 using the mask spacer 250 and the first fin spacer 191 as a mask, the mask spacer 250 is removed (refer to FIG. 17 ).

The process of removing the mask spacer 250 is a wet etching process or a dry etching process.

In this embodiment, further includes: removing the first fin sidewall 191 after etching the first transition doped layer 184 by using the mask sidewall 250 and the first fin sidewall 191 as a mask. The first fin sidewall 191 and the mask sidewall 250 are removed to expose the top surface and the sidewall surface of the first doped layer 183 .

In this embodiment, it also includes: removing the second fin sidewall 142 and the second fin sidewall 142 at the bottom of the second dielectric opening 232 after etching the first transition doped layer 184 by using the mask sidewall 250 and the first fin sidewall 191 as a mask. The second sidewall film 190 in the second region B exposes the top surface and the sidewall surface of the second doped layer 182 , and the bottom of the second dielectric opening 232 also exposes the isolation layer 103 in the second region B.

In this embodiment, the mask sidewall 250 , the first fin sidewall 191 , the second fin sidewall 142 and the second sidewall film 190 are removed in one etching process, which simplifies the process.

After performing the groove treatment process, a first metal silicide layer is formed on the outer sidewall and top surface of the first doped layer 183 and the inner wall of the groove, and a first metal silicide layer is formed on the top surface and side surfaces of the second doped layer 182. A second metal silicide layer is formed on the wall surface. Specifically, after removing the first fin spacer 191 and the mask spacer 250, a first metal silicide layer is formed on the surface of the first doped layer 183; the second fin spacer on the side wall of the second doped layer 182 is removed After 142 , a second metal silicide layer is formed on the surface of the second doped layer 182 .

The method for forming the first metal silicide layer and the second metal silicide layer will be described below with reference to FIGS. 19 to 20 .

19, on the sidewall and bottom of the first dielectric opening 231, the outer sidewall and top surface of the first doped layer 183, the inner wall surface of the groove, the sidewall and bottom of the second dielectric opening 232, the second The sidewall surface and the top surface of the second doped layer 182 and the top surface of the interlayer dielectric layer 210 form the metal layer 260 .

The material of the metal layer 260 is Ti, Co or Ni. In this embodiment, the material of the metal layer 260 is Ti. The process for forming the metal layer 260 is a deposition process, such as a sputtering process.

In this embodiment, it further includes: forming a barrier layer 270 on the surface of the metal layer 260 . The barrier layer 270 is made of titanium nitride or tantalum nitride. The process for forming the barrier layer 270 is a deposition process, such as a chemical vapor deposition process.

Referring to FIG. 20, an annealing process is performed to make the outer sidewall and top surface of the first doped layer 183, and the metal layer 260 of the inner wall of the groove react with the surface material of the first doped layer 183 to form a first metal silicide layer 281 , making the metal layer 260 on the sidewall surface and the top surface of the second doped layer 182 react with the material on the surface of the second doped layer 182 to form a second metal silicide layer 282 .

In this embodiment, the barrier layer 270 is formed before the annealing process. During the annealing process, the barrier layer 270 can protect the metal layer 260 and prevent the metal layer 260 from being oxidized. In other embodiments, the barrier layer is formed after the annealing process.

In this embodiment, it also includes: after forming the first metal silicide layer 281 and the second metal silicide layer 282 , forming a first plug in the first dielectric opening 231 , forming a second plug in the second dielectric opening 232 stuffed.

Referring to FIG. 21 , after forming the first metal silicide layer 281 and the second metal silicide layer 282 , a plug material layer 290 is formed in the first dielectric opening 231 and the second dielectric opening 232 and on the interlayer dielectric layer 210 .

The material of the plug material layer 290 is metal, such as tungsten. The process of forming the plug material layer 290 is a deposition process. In this embodiment, the plug material layer 290 is located on the surface of the barrier layer 270 .

Referring to FIG. 22, the plug material layer 290, the barrier layer 270 and the metal layer 260 are planarized until the top surface of the interlayer dielectric layer 210 is exposed, so that the plug material layer 290 in the first dielectric opening 231 forms a first plug. plug 291 , so that the plug material layer 290 in the second dielectric opening 232 forms a second plug 292 .

There are barriers between the first plug 291 and the first metal silicide layer 281, between the first plug 291 and the interlayer dielectric layer 210, and between the first plug 291 and the first region A isolation layer 103. Layer 270. The blocking layer 270 of the first region A is used to block atomic diffusion of the first plug 291 .

There are barriers between the second plug 292 and the second metal silicide layer 282, between the second plug 292 and the interlayer dielectric layer 210, and between the second plug 292 and the second region B isolation layer 103. Layer 270. The blocking layer 270 of the second region B functions to block atomic diffusion of the second plug 292 .

Correspondingly, this embodiment also provides a semiconductor device formed by the above method, please refer to FIG. 20 , which includes: a semiconductor substrate 100 with a first fin 111 on it; The first doped layer 183 has a groove in the first doped layer 183, the top surface of the first doped layer 183 exposes the groove, and the groove is on both sides of the width direction of the first fin portion 111 The wall surface is the surface of the first doped layer 183 ; the first metal silicide layer 281 located on the outer wall and top surface of the first doped layer 183 and the inner wall surface of the groove.

The cross-sectional shape of the groove in the first doped layer 183 in the width direction of the first fin 111 includes a "U" shape.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims (17)

1. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate is provided with a first fin part;

forming a first initial doping layer in the first fin portion;

performing a groove treatment process to enable the first initial doping layer to form a first doping layer, wherein a groove is formed in the first doping layer, the groove is exposed out of the top surface of the first doping layer, and the surfaces of the side walls of the groove in the width direction of the first fin portion are the surfaces of the first doping layer;

forming a first metal silicide layer on the outer side wall and the top surface of the first doping layer and the inner wall surface of the groove; before the groove processing technology is carried out, first fin side walls are formed, and the first fin side walls are located on the side walls of the first initial doping layer on the two sides of the first fin portion in the width direction and expose the top surface of the first initial doping layer;

the step of performing the groove treatment process includes: etching back part of the first initial doping layer to reduce the height of the first initial doping layer, so that the first initial doping layer forms a first transition doping layer, a recess located in the first fin part is formed in the first transition doping layer, and first fin side walls are arranged on two side walls of the recess in the width direction of the first fin part; forming a mask side wall on the side wall of the recess, wherein the mask side wall is in contact with the first fin side wall; etching the first transition doping layer by taking the mask side wall and the first fin side wall as masks, so that the first transition doping layer forms the first doping layer; removing the mask side wall after etching the first transition doping layer by taking the mask side wall and the first fin side wall as masks;

the method for forming the semiconductor device further comprises the following steps: removing the first fin side wall after etching the first transition doping layer by taking the mask side wall and the first fin side wall as masks; and after removing the first fin side wall and the mask side wall, forming the first metal silicide layer.

2. The method for forming a semiconductor device according to claim 1, further comprising: before forming the first initial doping layer, forming an isolation layer covering partial side walls of the first fin part on the semiconductor substrate, wherein the first fin part exposed by the isolation layer comprises a first replacement region;

the method for forming the first fin sidewall and the first initial doping layer comprises the following steps: forming a first fin side wall positioned on the surface of the isolation layer on the side wall of the first replacement region; etching to remove a first replacement region covered by the first fin side wall, forming a first initial replacement groove in the first fin part, wherein the side walls of two sides of the first initial replacement groove are respectively provided with the first fin side wall in the width direction of the first fin part; etching the first fin side wall on the inner wall of the first initial replacement groove to increase the size of the first initial replacement groove in the width direction of the first fin part to form a first replacement groove; forming the first preliminary doping layer in a first replacement trench.

3. The method of claim 1, wherein the first fin sidewall spacer is made of SiN, siCN, siBN, or SiON; the mask side wall is made of SiN, siCN, siBN or SiON.

4. The method for forming the semiconductor device according to claim 1, wherein the thickness of the mask sidewall is 2nm to 10nm.

5. The method of claim 1, wherein the first fin sidewall has a thickness of 2nm to 8nm.

6. The method of claim 1, wherein the step of forming the mask sidewall spacers on the sidewalls of the recess comprises: forming a mask side wall material layer on the side wall and the bottom of the recess, the surface of the first fin side wall and the semiconductor substrate; and etching the mask side wall material layer until the top surface of the first transition doping layer and the top surface of the first fin side wall are exposed to form the mask side wall.

7. The method of claim 1, wherein the etching the first transition doped layer using the mask sidewall and the first fin sidewall as masks comprises an anisotropic dry etching process.

8. The method for forming a semiconductor device according to claim 1, wherein the depth of etching the first transition doped layer using the mask sidewall and the first fin sidewall as masks occupies 20% to 100% of the thickness of the first transition doped layer.

9. The method for forming a semiconductor device according to claim 1, wherein the depth of the back-etched portion of the first preliminary doping layer is 3nm to 10nm.

10. The method of claim 1, wherein the first fin sidewall spacer is removed during the process of removing the mask sidewall spacer.

11. The method as claimed in claim 1, wherein a cross-sectional shape of the recess in a width direction of the first fin portion includes a "U" shape.

12. The method for forming a semiconductor device according to claim 1, further comprising: before the first initial doping layer is formed, forming a first grid electrode structure crossing the first fin portion on the semiconductor substrate, wherein the first grid electrode structure covers part of the top surface and part of the side wall surface of the first fin portion; the first initial doping layers are respectively positioned in the first fin parts at two sides of the first gate structure; after the first doping layer is formed, the first doping layer is respectively positioned in the first fin parts at two sides of the first gate structure.

13. The method of claim 1, wherein the semiconductor substrate comprises a first region and a second region, the first fin is located on the first region of the semiconductor substrate, and the second fin is located on the second region of the semiconductor substrate; the method for forming the semiconductor device further comprises the following steps: forming a second doped layer in the second fin portion before forming the first preliminary doped layer; and after the first doping layer is formed, forming a second metal silicide layer on the surface of the second doping layer.

14. The method as claimed in claim 13, wherein the semiconductor substrate has an isolation layer covering a portion of sidewalls of the second fin, and the second fin exposed by the isolation layer includes a second replacement region; the method for forming the semiconductor device further comprises the following steps: forming a second fin side wall positioned on the surface of the isolation layer on the side wall of the second replacement region of the second fin part; etching to remove a second replacement region covered by the second fin side wall, forming a second initial replacement groove in the second fin part, wherein the side walls of two sides of the second initial replacement groove are respectively provided with the second fin side wall in the width direction of the second fin part; etching the second fin side wall of the inner wall of the second initial replacement groove to increase the size of the second initial replacement groove in the width direction of the second fin part to form a second replacement groove; forming a second doping layer in the second replacement tank; and after removing the second fin side wall on the side wall of the second doping layer, forming the second metal silicide layer.

15. The method as claimed in claim 13, wherein the first region is used to form an N-type transistor and the second region is used to form a P-type transistor.

16. The method according to claim 13, wherein after the first preliminary doping layer is formed and before the recess treatment process is performed, a bottom dielectric layer is formed on the semiconductor substrate, the first preliminary doping layer, and the second doping layer; forming a first dielectric opening penetrating through the bottom dielectric layer in the bottom dielectric layer, wherein the first dielectric opening is positioned on the first initial doping layer; forming a second medium opening penetrating through the bottom medium layer in the bottom medium layer, wherein the second medium opening is positioned on the second doping layer; after a first medium opening and a second medium opening are formed, the groove processing technology is carried out; and after the groove processing technology is carried out, a first metal silicide layer is formed on the outer side wall and the top surface of the first doping layer and the inner wall of the groove, and a second metal silicide layer is formed on the top surface and the side wall surface of the second doping layer.

17. The method for forming a semiconductor device according to claim 16, further comprising: after the first metal silicide layer and the second metal silicide layer are formed, a first plug is formed in the first dielectric opening, and a second plug is formed in the second dielectric opening.

Images