CN114695255A - Display panel, array substrate and production method thereof - Google Patents

Abstract

The present application provides a display panel, an array substrate and a production method thereof. The production method of the array substrate includes: forming a first polysilicon layer on the substrate; forming a second polysilicon layer on the side of the first polysilicon layer away from the substrate For the silicon layer, the thickness of the second polysilicon layer is smaller than the thickness of the first polysilicon layer. The display panel, the array substrate and the production method thereof provided by the present application can effectively reduce the height of the protrusions on the surface of the polysilicon film layer in the array substrate, thereby reducing the surface roughness of the polysilicon film layer, which is beneficial to reducing the trenches of transistors in the array substrate Risk of leakage in the channel area.

Description

Display panel, array substrate and production method thereof

technical field

The present application relates to the technical field of display panel manufacturing, and in particular, to a display panel, an array substrate and a production method thereof.

Background technique

Thin film transistors are important components in the array substrate of display panels. Compared with amorphous silicon thin film transistors, polysilicon thin film transistors have higher electron mobility, faster response time and higher resolution, and have been widely used. In display devices, it is used as a switching element in the driving circuit part. When fabricating the active layer of the polysilicon thin film alarm tube, a low temperature polysilicon film (Low Temperature Poly Silicon, LTPS) is usually used.

In the production process of the array substrate, the surface roughness of the polysilicon film is usually high, and a large protrusion is formed on the surface of the polysilicon film, which will affect the conduction performance of the channel region of the thin film transistor, and even cause leakage in the channel region.

SUMMARY OF THE INVENTION

The present application provides a display panel, an array substrate and a production method thereof, so as to improve the leakage problem of the thin film transistor channel region of the array substrate.

In a first aspect, an embodiment of the present application provides a method for producing an array substrate, comprising: forming a first polysilicon layer on a substrate; forming a second polysilicon layer on a side of the first polysilicon layer away from the substrate. A crystalline silicon layer, the thickness of the second polycrystalline silicon layer is smaller than that of the first polycrystalline silicon layer.

In some embodiments, the step of forming the first polysilicon layer on the substrate includes: forming a first amorphous silicon layer on the substrate; and performing laser crystallization on the first amorphous silicon layer to transforming the first amorphous silicon layer into a first polysilicon layer; optionally, using a plasma-enhanced chemical vapor deposition method to generate the first amorphous silicon layer on the substrate; optionally and using an excimer laser annealing process to perform laser crystallization on the first amorphous silicon layer.

In some embodiments, the step of forming a second polysilicon layer on a side of the first polysilicon layer away from the substrate includes: forming a second polysilicon layer on a side of the first polysilicon layer away from the substrate A second amorphous silicon layer is formed on the side, and the thickness of the second amorphous silicon layer is smaller than that of the first amorphous silicon layer; laser crystallization is performed on the second amorphous silicon layer, so that the first amorphous silicon layer is The second amorphous silicon layer is transformed into the second polysilicon layer; optionally, a plasma enhanced chemical vapor deposition method is used to form the second polysilicon layer on the side of the first polysilicon layer away from the substrate. Two amorphous silicon layers; optionally, laser crystallization is performed on the second amorphous silicon layer by using an excimer laser annealing process.

In some embodiments, the thickness of the first amorphous silicon layer is h1, the thickness of the second amorphous silicon layer is h2, and the relationship between h1 and h2 satisfies: 0.4h1≤h2≤0.8h1; optionally , h2=0.5h1.

In some embodiments, the scanning direction for performing laser crystallization on the first amorphous silicon layer is a first direction, and the scanning direction for performing laser crystallization on the second amorphous silicon layer is a second direction, and the The first direction, the second direction and the thickness direction of the array substrate intersect in pairs; optionally, the first direction, the second direction and the thickness direction of the array substrate are perpendicular to each other.

In some embodiments, before the step of forming a second polysilicon layer on the side of the first polysilicon layer away from the substrate, the method for producing the array substrate further includes: cleaning with a first solution For the first polysilicon layer, the first solution includes ozone; the first polysilicon layer is cleaned with a second solution, and the second solution includes hydrofluoric acid; optionally, the first solution The concentration of ozone is 5 ppm to 20 ppm; optionally, the concentration of hydrofluoric acid in the second solution is 0.5 wt % to 5 wt %.

In some embodiments, after the step of cleaning the first polysilicon layer with the second solution, the production method of the array substrate further includes: cleaning the first polysilicon layer with a third solution, The third solution includes ozone, and the concentration of ozone in the third solution is greater than the concentration of ozone in the first solution.

In some embodiments, the method for producing an array substrate further includes: cleaning the second polysilicon layer with a first solution, the first solution including ozone; cleaning the second polysilicon layer with a second solution, The second solution includes hydrofluoric acid.

In a second aspect, an embodiment of the present application provides an array substrate, which is manufactured by using the production method for an array substrate provided by any one of the above embodiments.

In a third aspect, an embodiment of the present application uses a display panel, which includes the array substrate mentioned in the above embodiment.

The display panel, the array substrate, and the production method thereof provided by the embodiments of the present application can effectively generate the first polysilicon layer and the second polysilicon layer on the substrate, that is, the polysilicon film is divided into multiple film formations. Reducing the height of the protrusion on the surface of the polysilicon film layer in the array substrate, thereby reducing the surface roughness of the polysilicon film layer, is beneficial to reducing the risk of leakage in the channel region of the transistor in the array substrate.

Description of drawings

The features, advantages and technical effects of the exemplary embodiments of the present application will be described below with reference to the accompanying drawings. In the drawings, the same components are given the same reference numerals. The drawings are not drawn to actual scale.

FIG. 1 is a flowchart of a method for producing an array substrate according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a middle part of an array substrate produced by using the method for producing an array substrate provided in an embodiment of the present application;

3 is a flowchart of another method for producing an array substrate according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of the array substrate after the formation of the first amorphous silicon film layer in the production process of the array substrate provided by the embodiment of the present application;

FIG. 5 is a schematic structural diagram of the array substrate after the formation of the second amorphous film layer in the production process of the array substrate provided by the embodiment of the present application;

FIG. 6 is a flowchart of another method for producing an array substrate provided by an embodiment of the present application;

FIG. 7 is a flow chart of still another method for producing an array substrate according to an embodiment of the present application.

Description of reference numbers:

10 substrate; 20, polysilicon film layer; 21', first amorphous silicon layer; 21, first polysilicon layer; 22', second amorphous silicon layer; 22, second polysilicon layer;

X, thickness direction.

Detailed ways

Features and exemplary embodiments of various aspects of the present application are described in detail below. In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely to provide a better understanding of the present application by illustrating examples of the present application. In the drawings and the following description, at least some well-known structures and techniques are not shown in order to avoid unnecessarily obscuring the present application; and, the dimensions of some structures may be exaggerated for clarity. Furthermore, the features, structures or characteristics described below may be combined in any suitable manner in one or more embodiments.

In addition, the size and thickness of each configuration shown in the drawings are arbitrarily shown for understanding and ease of description, but the concept of the present application is not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. In the figures, the thicknesses of some layers and regions are exaggerated for better understanding and ease of description.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is described as being "directly on" another element, there are no intervening elements present. Furthermore, throughout the specification, the word "on" a target element means being positioned above or below the target element, and does not necessarily mean being positioned "at the upper side" based on the direction of gravity.

Furthermore, unless explicitly described to the contrary, the word "comprising" will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

At present, the active layer of the LTPS transistor usually includes a polysilicon film layer. The polysilicon film layer is usually formed by an amorphous silicon film layer after laser crystallization. During the laser crystallization process, the surface of the amorphous silicon film layer will form bumps. , and then the formed polysilicon layer has protrusions on the surface, which affects the surface roughness of the polysilicon film layer. In the process of using the LTPS transistor, the existence of the protrusion on the polysilicon film layer will affect the conduction performance of the channel region of the active layer, and even cause the leakage of the channel region.

In view of this, embodiments of the present application provide a method for producing an array substrate, an array substrate produced by using the production method, and a display panel using the array substrate, where the display panel may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel. Embodiments of the display panel and the display device will be described below with reference to the accompanying drawings.

FIG. 1 shows a flowchart of a method for producing an array substrate provided by an embodiment of the present application; FIG. 2 shows a middle part of an array substrate manufactured by using the method for producing an array substrate used in an embodiment of the present application. Schematic diagram of the structure of the piece.

As shown in FIG. 1 and FIG. 2 , the production method of the array substrate provided according to the embodiment of the present application includes:

S10, forming a first polysilicon layer 21 on the substrate 10;

S20 , a second polysilicon layer 22 is formed on the side of the first polysilicon layer 21 away from the substrate 10 , and the thickness of the second polysilicon layer 22 is smaller than that of the first polysilicon layer 21 .

Specifically, the first polysilicon layer 21 and the second polysilicon layer 22 may be produced on the substrate 10 from other materials, such as amorphous silicon materials, or may be directly lined with polysilicon materials. The bottom is formed by deposition or the like. That is to say, the first polysilicon layer 21 and the second polysilicon layer 22 may be formed on the substrate 10 after chemical reactions, or may only be formed on the substrate 10 through changes in physical structures such as shapes and states. , which can be selected as required.

The substrate 10 may include a substrate made of a glass material, or may include a substrate made of a flexible material such as PI (Polyimide, polyimide). The first polysilicon layer 21 can be directly formed on the substrate, or a buffer layer made of insulating material can be formed on the substrate, the first polysilicon layer 21 is formed on the buffer layer, and the insulating material can be an organic insulating material. The material can also be an inorganic insulating material. The organic insulating material has better flexibility, and the inorganic insulating material has better performance of blocking water and oxygen. Exemplarily, the insulating material is a compound including silicon oxide and silicon nitride, specifically You can choose according to your needs.

The “thickness” of the first polysilicon layer 21 and the second polysilicon layer 22 mentioned in this application refers to the thickness along the stacking direction of the substrate 10 , the first polysilicon layer 21 and the second polysilicon layer 22 . A size of the polysilicon layer 21 and the second polysilicon layer 22 .

It should be noted that, in the array substrate described in this application, the first polysilicon layer 21 and the second polysilicon layer 22 are sequentially formed on the substrate 10 , and it is not limited to only generate two polysilicon layers. In fact, the first polysilicon layer 21 and the second polysilicon layer 22 described in this application only represent the order in which they are formed, and the thickness of the polysilicon layer generated later is smaller than the thickness of the polysilicon layer generated earlier . Therefore, the method for producing an array substrate provided by the embodiments of the present application may include two, three or more polysilicon layers, and the thickness of the polysilicon layer generated each time is smaller than that of the polysilicon layer generated previously. In actual production, the number of polysilicon layers to be generated can be specifically determined according to information such as the thickness of the polysilicon layer in the active layer of the array substrate and the surface roughness requirements. By generating multiple polysilicon layers, the polysilicon film layer 20 of the array substrate is finally formed.

It can be understood that, the smaller the thickness of the first polysilicon layer 21 or the second polysilicon layer 22, the smaller the height of the protrusions formed on the surface thereof. Therefore, by dividing the polysilicon film layer 20 of the array substrate into multiple moldings, the heights of the protrusions on the surfaces of the first polysilicon layer 21 and the second polysilicon layer 22 can be simultaneously reduced, and the second polysilicon The layer 22 can be filled in the raised gaps formed on the first polysilicon layer 21 , so that the surface roughness of the polysilicon film layer 20 produced is much smaller than that of the polysilicon film layer 20 formed once.

In the production method of the array substrate provided by the embodiment of the present application, the first polysilicon layer 21 and the second polysilicon layer 22 are sequentially formed on the substrate 10, that is, the polysilicon film layer 20 is divided into multiple film formations, which can effectively The height of the protrusion on the surface of the polysilicon film layer 20 is reduced, thereby reducing the surface roughness of the polysilicon film layer 20 in the array substrate, which is beneficial to reduce the risk of leakage in the channel region of the transistor in the array substrate.

FIG. 3 shows a flow chart of the method for producing an array substrate provided in an embodiment of the present application, and FIG. 4 shows a schematic structural diagram of an array substrate middleware produced by the method for producing an array substrate as shown in FIG. 3 , FIG. 5 is a schematic structural diagram of another middle part of an array substrate produced by using the production method of an array substrate as shown in FIG. 3 .

As shown in FIG. 3 and FIG. 4 , in some embodiments, S10 , the step of forming the first polysilicon layer 21 on the substrate 10 includes:

S11, generating a first amorphous silicon layer 21' on the substrate 10;

S12. Perform laser crystallization on the first amorphous silicon layer 21', so that the first amorphous silicon layer 21' is transformed into the first polysilicon layer 21.

Specifically, in the process of generating the first polysilicon layer 21, the first amorphous silicon layer 21' may be deposited on the substrate 10 by a chemical vapor deposition method.

The first amorphous silicon layer 21' is subjected to laser crystallization, that is, the high energy generated by the instantaneous laser pulse is incident on the first amorphous silicon layer 21', and the laser can instantly increase the first amorphous silicon layer 21' to more than 1000 degrees Celsius. At about 100 degrees, it is transformed into a crystalline state, that is, the first polysilicon layer 21 is formed.

By forming the first amorphous silicon layer 21 ′ on the substrate 10 and performing laser crystallization on the first amorphous silicon layer 21 ′ to transform it into the first polysilicon layer 21 , the In the process of forming 21, it can be carried out at a relatively low temperature, and other structures such as the substrate 10 will not be damaged, and the first polysilicon layer 21 formed has large crystal grains, good spatial selectivity, high doping efficiency, and high crystallinity. It has few internal defects, good electrical properties and high mobility.

In some embodiments, in step S11, a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) method is used to form the first amorphous silicon layer 21' on the substrate 10.

Specifically, the PECVD method uses the electrons of the glow discharge to activate the chemical vapor deposition reaction at the same time as the low-pressure chemical vapor deposition. In the deposition process of the amorphous silicon film, silane can be decomposed by radio frequency glow discharge method, etc. Under the action of radio frequency power, the silane gas is decomposed into a variety of new particles: atoms, free radicals and various ions, etc. plasma. These new particles are deposited after a series of complex processes such as migration and dehydrogenation.

In the process of generating the first amorphous silicon layer 21' by the PECVD method, the deposition temperature is low, the influence on the structure and physical properties of the substrate 10 is small, and the thickness and composition uniformity of the generated first amorphous silicon layer 21' are good, The structure is dense, the pinholes are few, and the adhesion of the first amorphous silicon layer 21 ′ to the substrate 10 is strong.

In some embodiments, in S12, in the step of performing laser crystallization on the first amorphous silicon layer 21', an excimer laser annealing (Excimer Laser Annealing, ELA) process is used to perform laser crystallization on the first amorphous silicon layer 21' change.

Specifically, the ELA method utilizes a high-energy excimer laser to irradiate the first amorphous silicon layer 21 ′, so that after absorbing the energy of the excimer laser, the first amorphous silicon layer 21 ′ is in a melted state, and crystallizes after cooling to form the first amorphous silicon layer 21 ′. A polysilicon layer 21 . The preparation process is generally performed at a temperature of 400° C.˜600° C., which can effectively reduce the risk of deformation of the substrate 10 .

In this way, by using the ELA method to transform the first amorphous silicon layer 21 ′ into the first polycrystalline silicon layer 21 , the transformation from the first amorphous silicon layer 21 ′ to the first polycrystalline silicon layer 21 can be completed at a lower temperature. The transformation reduces the risk of deformation of structures such as the substrate 10 during the laser crystallization process, and is beneficial to ensure the stability of the structure and physical properties of the structures such as the substrate 10 .

As shown in FIG. 3 and FIG. 5 , in some embodiments, in step S20 , the step of forming the second polysilicon layer 22 on the side of the first polysilicon layer 21 away from the substrate 10 includes:

S21. A second amorphous silicon layer 22' is formed on the side of the first polysilicon layer 21 away from the substrate 10, and the thickness of the second amorphous silicon layer 22' is smaller than that of the first amorphous silicon layer 21'.

S22. Perform laser crystallization on the second amorphous silicon layer 22', so that the second amorphous silicon layer 22' is transformed into the second polysilicon layer 22.

Specifically, the second amorphous silicon layer 22' may be deposited on the first polysilicon layer 21 by means of deposition. After the first polysilicon layer 21 is formed by laser crystallization, there are protrusions on the surface, so that the surface roughness of the first polysilicon layer 21 is relatively high. In the process of depositing the second amorphous silicon layer 22 ′ on the first polysilicon layer 21 , the second amorphous silicon layer 22 ′ can be filled between the protrusions, and the protrusions on the first polysilicon layer 21 The height of the protruding second amorphous silicon layer 22' is reduced. After the second amorphous silicon layer 22' is transformed into the second polysilicon layer 22 through laser crystallization, due to the thickness of the second amorphous silicon layer 22' is smaller than the thickness of the first amorphous silicon layer 21 ′, the formed protrusions on the second polysilicon layer 22 are smaller than those on the first polysilicon layer 21 , and the protrusions on the first polysilicon layer 21 are smaller than those on the first polysilicon layer 21 . Since it is filled with the second polysilicon layer 22, the height of the protrusions on the first polysilicon layer 21 protruding from the surface of the second polysilicon layer 22 is reduced, thereby reducing the total amount of the second polysilicon layer 22. The height of the protrusion is reduced, that is, the surface roughness of the polysilicon film layer 20 is reduced.

In some embodiments, the plasma-enhanced chemical vapor deposition method is used to form the second amorphous silicon layer 22' on the side of the first polysilicon layer 21 away from the substrate 10. That is, in step S21, the PECVD method is used to form the second amorphous silicon layer 22'.

In the process of using PECVD to generate the first amorphous silicon layer 21' and using the PECVD method to generate the second amorphous silicon layer 22', the deposition temperature is low, which has little influence on the structure and physical properties of the substrate 10, and the generated second amorphous silicon layer 22' has a low deposition temperature. The thickness and composition uniformity of the amorphous silicon layer 22 ′ is good, the structure is dense, and the pinholes are few, and the adhesion of the second amorphous silicon layer 22 ′ to the substrate 10 is strong.

In some embodiments, the second amorphous silicon layer 22' is laser crystallized using an excimer laser annealing process. That is, in step S22, laser crystallization is performed on the second amorphous silicon layer 22' by the ELA method.

Using the ELA method to perform laser crystallization on the first amorphous silicon layer 21 ′ has the same effect, and using the ELA method to transform the second amorphous silicon layer 22 ′ into the second polysilicon layer 22 can be performed at a lower The transformation of the second amorphous silicon layer 22 ′ to the second polysilicon layer 22 is completed at a temperature of low temperature, which reduces the risk of deformation of the substrate 10 and other structures during the laser crystallization process, and is beneficial to ensure the structure of the substrate 10 and other structures. and stability of physical properties.

It can be understood that as long as the thickness of the second amorphous silicon layer 22' is smaller than the thickness of the first amorphous silicon layer 21', the purpose of reducing the surface roughness of the generated polycrystalline silicon film layer 20 can be achieved.

As shown in FIG. 4 and FIG. 5 , in some embodiments, the thickness of the first amorphous silicon layer 21 ′ is h1 , the thickness of the second amorphous silicon layer 22 ′ is h2 , and the relationship between h1 and h2 satisfies: 0.4h1 ≤h2≤0.8h1. Specifically, h2 may be 0.4h1, 0.5h1, 0.6h1, 0.7h1, or 0.8h1, etc.

Since the thickness of the amorphous silicon layer is larger, the height of the protrusions on the polysilicon layer formed after crystallization is also higher. Ideally, after the second polysilicon layer 22 is formed, the protrusion height of the second polysilicon layer 22 itself and the protrusion formed by the first polysilicon layer 21 protrude from the second polysilicon layer 22 . The same height is more favorable for reducing the surface roughness of the formed polysilicon film layer 20 .

Therefore, if 0.4h1≤h2≤0.8h1 is set, after the second polysilicon layer 22 is formed, the height of the protrusions of the second polysilicon itself and the protrusions formed by the first polysilicon layer 21 can be the second higher. The height of the crystalline silicon layer 22 is approximately the same, which is beneficial to reduce the surface roughness of the polycrystalline silicon film layer 20 in the array substrate.

In some embodiments, h2=0.5h1. That is, the second amorphous silicon layer 22 ′ is half the thickness of the first amorphous silicon layer 21 ′. In this way, for some amorphous silicon materials, during the crystallization process, the surface of the generated polysilicon film layer 20 can be further reduced roughness.

In some embodiments, the scanning direction for laser crystallization on the first amorphous silicon layer 21' is the first direction, and the scanning direction for laser crystallization on the second amorphous silicon layer 22' is the second direction. The first direction, the second direction and the thickness direction X of the array substrate intersect each other two by two.

Specifically, arranging that both the first direction and the second direction intersect the thickness direction X of the array substrate is favorable for effective laser crystallization of the first amorphous silicon layer 21' and the second amorphous silicon layer 22'. However, setting the second direction to intersect with the first direction can effectively reduce the surface roughness of the second polysilicon layer 22 to be generated.

It should be noted that, if more amorphous silicon film layers are provided and multiple times of laser crystallization are required, the scanning direction of each laser crystallization intersects the scanning direction of the previous laser crystallization to further reduce the generation of the surface roughness of the polysilicon film layer 20 .

In some embodiments, the first direction, the second direction and the thickness direction X of the array substrate are perpendicular to each other.

It can be understood that setting both the first direction and the second direction perpendicular to the thickness direction X of the array substrate is conducive to further improving the efficiency of laser crystallization. However, setting the first direction and the second direction to be vertical is beneficial to reduce the surface roughness of the second polysilicon layer 22 to the greatest extent under the premise of other inconvenience.

Optionally, after step S10, step S20 may be directly performed, and other steps, such as cleaning, may also be set between steps S10 and S20.

FIG. 6 shows another flowchart of the method for producing an array substrate provided by the present application.

As shown in FIG. 6 , in some embodiments, in S20 , before the step of forming the second polysilicon layer 22 on the side of the first polysilicon layer 21 away from the substrate 10 , the production method of the array substrate further includes:

S31, using a first solution to clean the first polysilicon layer 21, and the first solution includes ozone;

S32, the first polysilicon layer 21 is cleaned with a second solution, and the second solution includes hydrofluoric acid.

Specifically, after the first polysilicon layer 21 is generated, the first polysilicon layer 21 is cleaned with a first solution, and the first polysilicon layer 21 is combined with ozone in the first solution to make the first polysilicon layer 21 The surface of the polysilicon layer 21 is oxidized to form oxides such as silicon oxide. Then the first polysilicon layer 21 is cleaned by the second solution, and the hydrofluoric acid in the second solution chemically reacts with the oxide on the surface of the first polysilicon layer 21 to form an oxide on the surface of the first polysilicon layer 21 etched away. In this way, impurities on the surface of the first polysilicon layer 21 can be removed through two steps of oxidation and etching. In addition, in the process of oxidizing the first polysilicon layer 21, the protrusions formed on the surface of the first polysilicon layer 21 can also be oxidized, and then the oxidized protrusions can be cleaned by the second solution. A part is etched away, thereby reducing the surface roughness of the first polysilicon layer 21 . That is to say, by cleaning the first polysilicon layer 21 with the first solution and the second solution in steps S31 and S32, not only impurities on the surface of the first polysilicon layer 21 can be removed, but also the first polysilicon layer 21 can be effectively reduced. The surface roughness of a polysilicon layer 21 is further beneficial to reduce the surface roughness of the polysilicon film layer 20 in the array substrate.

The concentration of ozone in the first solution is not limited as long as oxides can be formed on the surface of the first polysilicon layer 21 .

In some embodiments, the concentration of ozone in the first solution is 5 ppm to 20 ppm. Specifically, the concentration of ozone in the first solution may be 5 ppm, 10 ppm, 15 ppm, 20 ppm, or the like.

Setting the concentration of ozone in the first solution to be 5 ppm to 20 ppm can ensure that oxides are formed on the surface of the first polysilicon, which is easy to be etched away by the second solution in subsequent steps.

The concentration of hydrofluoric acid in the second solution is not limited, as long as the oxide formed after being cleaned by the first solution can be etched away.

In some embodiments, the concentration of hydrofluoric acid in the second solution is 0.5 Wt % to 5 Wt %. Specifically, the concentration of hydrofluoric acid in the second solution may be 0.5Wt%, 1Wt%, 1.5Wt%, 2Wt%, 2.5Wt%, 3Wt%, 4Wt%, or 5Wt%. The second solution thus formed can ensure that the oxide formed after the cleaning of the first solution is etched away, and will not cause damage to the substrate 10 or the second polysilicon layer 22 due to the high concentration of hydrofluoric acid in the second solution. Corrosion of other structures.

In some embodiments, S32, after the step of cleaning the first polysilicon layer 21 with the second solution, the production method of the array substrate further includes:

S33, using a third solution to clean the first polysilicon layer 21, the third solution includes ozone, and the concentration of ozone in the third solution is greater than the concentration of ozone in the first solution.

It can be understood that, after the second solution is used to clean the surface of the first polysilicon layer 21, the third solution is used to clean the first polysilicon layer 21, and the ozone concentration in the third solution is set higher than The concentration of ozone in the first solution can, on the one hand, clean off the residual hydrofluoric acid on the surface of the first polysilicon layer 21 and reduce the corrosion of the residual on the first polysilicon layer 21; The formation of a uniform and dense oxide layer on the surface of the first polysilicon layer 21 is beneficial to the smooth progress of the process of forming the second polysilicon layer 22 on the first polysilicon layer 21 .

FIG. 7 shows yet another flowchart of the method for producing an array substrate provided by an embodiment of the present application.

As shown in FIG. 7 , in some embodiments, the production method of the array substrate further includes:

S41 , using a first solution to clean the second polysilicon layer 22 , and the first solution includes ozone.

S42 , cleaning the second polysilicon layer 22 with a second solution, where the second solution includes hydrofluoric acid.

It has the same effect as using the first solution and the second solution to clean the first polysilicon layer 21 in turn. Using the first solution and the second solution to clean the second polysilicon layer 22 in turn can clear the surface of the second polysilicon. At the same time, the surface roughness of the second polysilicon layer 22 is effectively reduced, which is beneficial to reduce the surface roughness of the polysilicon film layer 20 in the array substrate.

In some embodiments, after step S42, the second polysilicon layer 22 may also be cleaned with a third solution, so as to form a uniform and dense oxide layer on the second polysilicon layer 22, which is beneficial to ensure the second polysilicon layer 22. Performance stability of the crystalline silicon layer 22 .

The array substrate provided according to the embodiment of the present application is manufactured by using the production method of the array substrate provided by any one of the above embodiments. The surface roughness of the active layer of the thin film transistor in the array substrate thus produced is relatively low, which effectively reduces the risk of channel leakage in the thin film transistor.

The display panel provided according to the embodiments of the present application includes the array substrate provided by the above embodiments.

Since the display panel provided by the embodiment of the present application adopts the array substrate provided by the above-mentioned embodiment, it has the same technical effect, which is not repeated here.

While the application has been described with reference to the preferred embodiments, various modifications may be made and equivalents may be substituted for parts thereof without departing from the scope of the application. In particular, as long as there is no structural conflict, each technical feature mentioned in each embodiment can be combined in any manner. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

Claims (10)

1. A method for producing an array substrate, comprising:

generating a first polysilicon layer on a substrate;

and generating a second polysilicon layer on one side of the first polysilicon layer, which is far away from the substrate, wherein the thickness of the second polysilicon layer is smaller than that of the first polysilicon layer.

2. The method for manufacturing an array substrate of claim 1, wherein the step of growing the first polysilicon layer on the substrate comprises:

generating a first amorphous silicon layer on the substrate;

performing laser crystallization on the first amorphous silicon layer to convert the first amorphous silicon layer into a first polycrystalline silicon layer;

preferably, the first amorphous silicon layer is generated on the substrate by adopting a plasma enhanced chemical vapor deposition method;

preferably, the first amorphous silicon layer is laser crystallized by an excimer laser annealing process.

3. The method for manufacturing the array substrate according to claim 2, wherein the step of forming a second polysilicon layer on a side of the first polysilicon layer away from the substrate comprises:

generating a second amorphous silicon layer on one side of the first polycrystalline silicon layer, which is far away from the substrate, wherein the thickness of the second amorphous silicon layer is smaller than that of the first amorphous silicon layer;

performing laser crystallization on the second amorphous silicon layer to transform the second amorphous silicon layer into the second polycrystalline silicon layer;

preferably, a plasma enhanced chemical vapor deposition method is adopted to generate the second amorphous silicon layer on the side of the first polycrystalline silicon layer far away from the substrate;

preferably, the second amorphous silicon layer is laser crystallized by an excimer laser annealing process.

4. The method for manufacturing an array substrate of claim 3, wherein the first amorphous silicon layer has a thickness h1, the second amorphous silicon layer has a thickness h2, and the relationship between h1 and h2 satisfies: h2 is more than or equal to 0.4h1 and less than or equal to 0.8h 1;

preferably, h2 is 0.5h 1.

5. The method for manufacturing an array substrate according to claim 3, wherein a scanning direction for performing laser crystallization on the first amorphous silicon layer is a first direction, a scanning direction for performing laser crystallization on the second amorphous silicon layer is a second direction, and the first direction, the second direction and a thickness direction of the array substrate intersect with each other;

preferably, the first direction, the second direction, and the thickness direction of the array substrate are perpendicular to each other.

6. The method for manufacturing an array substrate according to claim 1, wherein before the step of generating the second polysilicon layer on the side of the first polysilicon layer away from the substrate, the method for manufacturing an array substrate further comprises:

cleaning the first polysilicon layer by using a first solution, wherein the first solution comprises ozone;

cleaning the first polycrystalline silicon layer by using a second solution, wherein the second solution comprises hydrofluoric acid;

preferably, the concentration of ozone in the first solution is 5ppm to 20 ppm;

preferably, the concentration of the hydrofluoric acid in the second solution is 0.5 Wt% to 5 Wt%.

7. The method for manufacturing an array substrate according to claim 6, wherein after the step of cleaning the first polysilicon layer with the second solution, the method further comprises:

and cleaning the first polycrystalline silicon layer by using a third solution, wherein the third solution comprises ozone, and the concentration of the ozone in the third solution is greater than that of the ozone in the first solution.

8. The method for manufacturing an array substrate according to claim 1, further comprising:

cleaning the second polysilicon layer by using a first solution, wherein the first solution comprises ozone;

and cleaning the second polycrystalline silicon layer by adopting a second solution, wherein the second solution comprises hydrofluoric acid.

9. An array substrate manufactured by the method for manufacturing an array substrate according to any one of claims 1 to 8.

10. A display panel comprising the array substrate according to claim 9.

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