CN106601593A - Method for reducing the polysilicon surface roughness - Google Patents
Method for reducing the polysilicon surface roughness Download PDFInfo
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 127
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 126
- 238000000034 method Methods 0.000 title claims abstract description 79
- 230000003746 surface roughness Effects 0.000 title claims abstract description 32
- 238000011282 treatment Methods 0.000 claims abstract description 74
- 230000003647 oxidation Effects 0.000 claims abstract description 59
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 59
- 238000005530 etching Methods 0.000 claims abstract description 39
- 230000008569 process Effects 0.000 claims abstract description 35
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 20
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 41
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 26
- 238000005224 laser annealing Methods 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 12
- 239000000377 silicon dioxide Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 11
- 238000010438 heat treatment Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 5
- 239000013078 crystal Substances 0.000 claims description 5
- 239000001301 oxygen Substances 0.000 claims description 5
- 229910052760 oxygen Inorganic materials 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000000630 rising effect Effects 0.000 claims 1
- 239000010408 film Substances 0.000 abstract description 56
- 239000010409 thin film Substances 0.000 abstract description 21
- 230000001590 oxidative effect Effects 0.000 abstract description 2
- 238000007715 excimer laser crystallization Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 10
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 9
- 238000002844 melting Methods 0.000 description 8
- 230000008018 melting Effects 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 229910000077 silane Inorganic materials 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000004151 rapid thermal annealing Methods 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 238000002425 crystallisation Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000002131 composite material Substances 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000012071 phase Substances 0.000 description 2
- 230000006798 recombination Effects 0.000 description 2
- 238000005215 recombination Methods 0.000 description 2
- 229920006395 saturated elastomer Polymers 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000010301 surface-oxidation reaction Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 208000032750 Device leakage Diseases 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- VZPPHXVFMVZRTE-UHFFFAOYSA-N [Kr]F Chemical compound [Kr]F VZPPHXVFMVZRTE-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- ISQINHMJILFLAQ-UHFFFAOYSA-N argon hydrofluoride Chemical compound F.[Ar] ISQINHMJILFLAQ-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 230000006837 decompression Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000006356 dehydrogenation reaction Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000003344 environmental pollutant Substances 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 229910000040 hydrogen fluoride Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 238000004093 laser heating Methods 0.000 description 1
- 239000007791 liquid phase Substances 0.000 description 1
- 238000011068 loading method Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 235000013842 nitrous oxide Nutrition 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 231100000719 pollutant Toxicity 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000001131 transforming effect Effects 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- HGCGQDMQKGRJNO-UHFFFAOYSA-N xenon monochloride Chemical compound [Xe]Cl HGCGQDMQKGRJNO-UHFFFAOYSA-N 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
- H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
- H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
- H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
- H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H01L21/3105—After-treatment
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Abstract
本发明涉及一种降低多晶硅表面粗糙度的方法,其包括如下步骤:i)将O3水与多晶硅层的表面接触进行氧化处理,在多晶硅层的表面形成表面氧化层;ii)将多晶硅层的表面形成的表面氧化层与HF溶液接触进行蚀刻处理,得到经氧化处理和刻蚀处理的多晶硅层;iii)依次重复步骤i)的氧化处理和步骤ii)的蚀刻处理过程n次,直至多晶硅界面处凸起的高度小于30nm,其中n为正整数。本发明方法利用O3水对多晶硅层表面进行氧化处理,O3具有强氧化性,大幅缩短氧化时间;然后经多次氧化处理和蚀刻处理显著提高多晶硅膜表面的平整度,以减少薄膜晶体管的漏电流,优化其电性。
The invention relates to a method for reducing the surface roughness of polysilicon, which comprises the following steps: i) O 3 water is contacted with the surface of the polysilicon layer for oxidation treatment, and a surface oxide layer is formed on the surface of the polysilicon layer; ii) the surface of the polysilicon layer is oxidized The surface oxide layer formed on the surface is contacted with HF solution for etching treatment to obtain a polysilicon layer through oxidation treatment and etching treatment; iii) repeating the oxidation treatment of step i) and the etching treatment process of step ii) n times in sequence until the polysilicon interface The height of the protrusion is less than 30nm, wherein n is a positive integer. The method of the present invention utilizes O 3 water to carry out oxidation treatment to the polysilicon layer surface, O 3 has strong oxidizing property, greatly shortens the oxidation time; Then significantly improves the flatness of the polysilicon film surface through multiple oxidation treatment and etching treatment, to reduce thin film transistor Leakage current, optimize its electrical properties.
Description
技术领域technical field
本发明属于液晶面板制造技术领域,具体涉及一种降低薄膜晶体管中多晶硅表面粗糙度的方法。The invention belongs to the technical field of liquid crystal panel manufacture, and in particular relates to a method for reducing the surface roughness of polysilicon in thin film transistors.
背景技术Background technique
液晶显示元件的薄膜晶体管(TFT)是由在绝缘基板上形成的硅膜构成,作为液晶显示元件的像素中设置的开关元件或外围电路部分中形成的驱动元件来使用。作为构成TFT的硅膜,大多使用非晶硅膜,但近年来越来越多地使用具有更好特性的多晶硅膜,现在在这方面正在进行很多的开发工作。而多晶硅膜的形成需要在高温下进行,但又由于绝缘基板的耐热度较低,容易造成基板变形,因此,在制作薄膜晶体管有源层时通常采用低温多晶硅薄膜(Low Temperature Polysilicon Thin Film)。A thin film transistor (TFT) of a liquid crystal display element is composed of a silicon film formed on an insulating substrate, and is used as a switching element provided in a pixel of a liquid crystal display element or a driving element formed in a peripheral circuit portion. As a silicon film constituting a TFT, an amorphous silicon film is mostly used, but in recent years, a polysilicon film having better characteristics has been increasingly used, and much development work is currently being carried out in this regard. The formation of polysilicon film needs to be carried out at high temperature, but because the heat resistance of the insulating substrate is low, it is easy to cause substrate deformation. Therefore, low temperature polysilicon thin film (Low Temperature Polysilicon Thin Film) is usually used when making the active layer of TFT .
现有制备多晶硅膜时一般采用准分子激光退火(Excimer Laser Annealing,可缩写为ELA)的方法,其利用高能量的准分子激光照射非晶硅薄膜,使其吸收准分子激光的能量后,使非晶硅薄膜呈融化状态,冷却后结晶后形成多晶硅膜,制备过程一般是在400℃~600℃的温度下进行的,能够有效防止基板的变形。采用准分子激光发生器的脉冲激光,在非晶硅层上进行扫描形成一照射区域,该脉冲激光扫描完成后向前移动一段距离,使形成的多个照射区域相互重叠,由于重叠部分温度较未重叠部分温度高,在重叠部分与未重叠部分的界面发生非均匀成核,通常重叠部分与其他未重叠部分产生的横向温度梯度,晶核将沿温度较高的方向即从未重叠部分至重叠部分的方向长大,并最终结晶成低温多晶硅薄膜。Excimer laser annealing (abbreviated as ELA) method is generally used in the existing preparation of polysilicon film, which utilizes high-energy excimer laser to irradiate amorphous silicon film to make it absorb the energy of excimer laser, and make it The amorphous silicon film is in a melting state, and after cooling, it crystallizes to form a polysilicon film. The preparation process is generally carried out at a temperature of 400°C to 600°C, which can effectively prevent the deformation of the substrate. The pulse laser of the excimer laser generator is used to scan the amorphous silicon layer to form an irradiation area. After the pulse laser scanning is completed, it moves forward for a certain distance, so that the formed multiple irradiation areas overlap each other. Because the temperature of the overlapping part is relatively high The temperature of the non-overlapping part is high, and non-uniform nucleation occurs at the interface between the overlapping part and the non-overlapping part. Usually, the transverse temperature gradient generated between the overlapping part and other non-overlapping parts will lead to crystal nuclei along the direction of higher temperature, that is, from the non-overlapping part to The direction of the overlapping portion grows and eventually crystallizes into a low-temperature polysilicon film.
准分子激光退火工艺是一种相对比较复杂的退火过程。对于多晶硅薄膜中,薄膜表面平坦性,晶粒尺寸及晶粒均匀性的控制一直是该退火工艺中的研究热点。目前由于普通激光退火过程中引起的多晶硅晶粒的不均匀性生长,导致非常大的薄膜粗糙度,且多晶硅薄膜的晶粒尺寸偏小,分布不均匀。Excimer laser annealing process is a relatively complicated annealing process. For polysilicon thin films, the control of film surface flatness, grain size and grain uniformity has always been a research hotspot in the annealing process. At present, due to the non-uniform growth of polysilicon grains caused by the ordinary laser annealing process, the film roughness is very large, and the grain size of the polysilicon film is small and unevenly distributed.
低温多晶硅薄膜晶体管的沟道区所覆盖的多晶硅晶粒数量及分布情况均匀性,以及多晶硅薄膜表面平坦性(或者说表面粗糙度),都将直接影响低温多晶硅薄膜晶体管的电学性能,如迁移率大小、漏电流大小、迁移率及阈值电压的均匀性等。The number and distribution uniformity of polysilicon grains covered by the channel region of the low temperature polysilicon thin film transistor, and the surface flatness (or surface roughness) of the polysilicon film will directly affect the electrical properties of the low temperature polysilicon thin film transistor, such as mobility Size, leakage current size, mobility and uniformity of threshold voltage, etc.
而在现有的LTPS生产制程中,在多晶硅膜与闸极膜之间会镀有一层SiOx/SiNx膜,又因为多晶硅膜表面的粗糙度(roughness)过高(晶界处最高高度超过40nm)。易形成寄生电容和尖端放电,造成TFT漏电流过大现象,且易刺穿栅绝缘膜(GI),所以为了避免抑制这些现象的产生,在生产时会采用增加GI膜的厚度的方式,GI膜厚度的增加必然造成GI镀膜机台tact time的增加,也会造成后续IMP doping困难。In the existing LTPS production process, a layer of SiO x /SiN x film will be plated between the polysilicon film and the gate film, and because the surface roughness of the polysilicon film is too high (the highest height at the grain boundary exceeds 40nm). It is easy to form parasitic capacitance and tip discharge, resulting in excessive leakage current of TFT, and it is easy to pierce the gate insulating film (GI). Therefore, in order to avoid suppressing these phenomena, the method of increasing the thickness of the GI film will be adopted during production. GI The increase of film thickness will inevitably increase the tact time of GI coating machine, and will also cause difficulties in subsequent IMP doping.
公开号为:CN102655089,名称为《一种低温多晶硅薄膜的制作方法》的专利中公开的多晶硅薄膜的制作方法如下:首先在基板上依次沉积缓冲层和非晶硅层,再对非晶硅层进行高温加热,并对非晶硅层进行准分子激光退火,形成多晶硅层,然后依次进行氧化和刻蚀,得到多晶硅薄膜。其中的氧化过程是将经准分子激光退火后形成的多晶硅层,放置在温度为700℃的氧气气氛下的快速热退火装置中进行快速热退火,这样能使得未晶化的非晶硅氧化成二氧化硅。其中另一氧化处理方法是在笑气等离子体(N2O plasma)气氛下对多晶硅层进行氧化,具体过程是在PECVD气相沉积设备中进行。The publication number is: CN102655089, and the manufacturing method of the polysilicon thin film disclosed in the patent titled "A Method for Making a Low-Temperature Polysilicon Thin Film" is as follows: first, a buffer layer and an amorphous silicon layer are sequentially deposited on the substrate, and then the amorphous silicon layer is Heating at high temperature, and performing excimer laser annealing on the amorphous silicon layer to form a polysilicon layer, followed by oxidation and etching in sequence to obtain a polysilicon film. The oxidation process is to place the polysilicon layer formed after excimer laser annealing in a rapid thermal annealing device under an oxygen atmosphere at a temperature of 700°C for rapid thermal annealing, which can oxidize the uncrystallized amorphous silicon into silica. Another oxidation treatment method is to oxidize the polysilicon layer under the atmosphere of laughing gas plasma (N 2 O plasma), and the specific process is carried out in PECVD vapor deposition equipment.
而其中的刻蚀过程采用氢氟酸溶液对氧化后的多晶硅层进行刻蚀,由于二氧化硅与氢氟酸发生化学反应,所以多晶硅层上的二氧化硅会与多晶硅层脱离,从而形成多晶硅薄膜。In the etching process, hydrofluoric acid solution is used to etch the oxidized polysilicon layer. Due to the chemical reaction between silicon dioxide and hydrofluoric acid, the silicon dioxide on the polysilicon layer will be separated from the polysilicon layer to form a polysilicon layer. film.
该专利中对多晶硅层的氧化过程是在温度为700℃的氧气气氛下的快速热退火装置中进行快速热退火,从而使未晶化的非晶硅氧化成二氧化硅。但通过氧气进行氧化处理的效率低,氧化处理时间较长。The oxidation process of the polysilicon layer in this patent is to perform rapid thermal annealing in a rapid thermal annealing device under an oxygen atmosphere at a temperature of 700° C., so that uncrystallized amorphous silicon is oxidized into silicon dioxide. However, the efficiency of oxidation treatment by oxygen is low, and the oxidation treatment time is relatively long.
发明内容Contents of the invention
本发明的目的是为了解决现有LTPS生产制程得到的多晶硅膜表面的粗糙度过高,易形成寄生电容,造成TFT漏电流过大的问题,而提供降低多晶硅表面粗糙度的方法。The purpose of the present invention is to provide a method for reducing the surface roughness of polysilicon to solve the problem that the surface roughness of the polysilicon film obtained by the existing LTPS production process is too high, which is easy to form parasitic capacitance and cause excessive TFT leakage current.
本发明降低多晶硅表面粗糙度的方法包括如下步骤:The method for reducing the surface roughness of polysilicon in the present invention comprises the following steps:
i)将O3水与多晶硅层的表面接触进行氧化处理,在多晶硅层的表面形成表面氧化层;i) O 3 water is contacted with the surface of the polysilicon layer for oxidation treatment, forming a surface oxide layer on the surface of the polysilicon layer;
ii)将在多晶硅层的表面形成的表面氧化层与HF溶液接触进行蚀刻处理,得到经氧化处理和蚀刻处理的多晶硅层;ii) contacting the surface oxide layer formed on the surface of the polysilicon layer with an HF solution for etching treatment to obtain an oxidized and etched polysilicon layer;
iii)依次重复步骤i)的氧化处理和步骤ii)的蚀刻处理过程n次,直至多晶硅界面处凸起的高度小于30nm,其中,n为正整数。iii) repeating the oxidation treatment of step i) and the etching treatment of step ii) n times in sequence until the height of the protrusion at the polysilicon interface is less than 30 nm, wherein n is a positive integer.
本发明步骤i)中所述的多晶硅层可以采用等离子体增强化学反应气相沉积(PECVD)法、准分子激光晶化(ELA)法或低压气相化学气相沉积(LPCVD)等方法得到。The polysilicon layer described in step i) of the present invention can be obtained by methods such as plasma enhanced chemical reaction vapor deposition (PECVD), excimer laser crystallization (ELA) or low pressure vapor phase chemical vapor deposition (LPCVD).
在一个实施例中,步骤i)中所述的多晶硅层采用低压气相化学气相沉积法在石英玻璃基底上得到的。LPCVD沉积法具有生长速度快,成膜致密、均匀、装片容量大等特点。多晶硅薄膜可采用硅烷气体通过LPCVD法直接沉积在衬底上,控制沉积参数一般为:硅烷压力为13.3~26.6Pa,沉积温度Td=580~650℃,生长速率5~10nm/min。In one embodiment, the polysilicon layer described in step i) is obtained on the quartz glass substrate by low-pressure gas-phase chemical vapor deposition. The LPCVD deposition method has the characteristics of fast growth, dense and uniform film formation, and large loading capacity. The polysilicon film can be directly deposited on the substrate by LPCVD using silane gas, and the deposition parameters are generally controlled as follows: silane pressure is 13.3-26.6Pa, deposition temperature Td=580-650°C, and growth rate is 5-10nm/min.
LPCVD法生长的多晶硅薄膜,晶粒具有择优取向,形貌呈“V”字形,内含高密度的微挛晶缺陷,且晶粒尺寸小,载流子迁移率不够大而使其在器件应用方面受到一定限制。虽然减少硅烷压力有助于增大晶粒尺寸,但往往伴随着表面粗糙度的增加,对载流子的迁移率与TFT器件的电学稳定性产生不利影响。The polysilicon thin film grown by LPCVD method has a preferred orientation of grains, a "V" shape, contains high-density micro-twin crystal defects, and the grain size is small, and the carrier mobility is not large enough to make it suitable for use in devices. subject to certain restrictions. Although reducing the silane pressure helps to increase the grain size, it is often accompanied by an increase in surface roughness, which adversely affects the mobility of carriers and the electrical stability of TFT devices.
在另一个实施例中,步骤i)中所述的多晶硅层采用等离子体增强化学反应气相沉积(PECVD)法在非晶硅表面上沉积得到的。PECVD法是在低压化学气相沉积的同时,利用辉光放电的电子来激活化学气相沉积反应。在多晶硅薄膜的沉积过程中,通过射频辉光放电法(Radio Frequency Glow Discharge)分解硅烷,在射频功率的作用下,硅烷气体被分解成多种新的粒子:原子、自由基团以及各种离子等等离子体。这些新的粒子通过迁移、脱氢等一系列复杂的过程后进行沉积。整体上多晶硅薄膜的沉积过程可以分为两个步骤:即SiH4气体的分解以及基团的沉积。此方法所需要的沉积温度较低,在300~450℃左右即可获得多晶硅,但用CVD法制备得多晶硅晶粒尺寸小,一般不超过50nm,晶内缺陷多,晶界多,需要进行后续的氧化处理和蚀刻处理。In another embodiment, the polysilicon layer described in step i) is deposited on the surface of amorphous silicon by plasma enhanced chemical reaction vapor deposition (PECVD). The PECVD method uses glow discharge electrons to activate the chemical vapor deposition reaction at the same time as low-pressure chemical vapor deposition. During the deposition process of polysilicon film, silane is decomposed by radio frequency glow discharge method (Radio Frequency Glow Discharge). Under the action of radio frequency power, silane gas is decomposed into a variety of new particles: atoms, free radicals and various ions Wait for the plasma. These new particles are deposited after a series of complex processes such as migration and dehydrogenation. On the whole, the deposition process of polysilicon film can be divided into two steps: the decomposition of SiH 4 gas and the deposition of groups. The deposition temperature required by this method is relatively low, and polysilicon can be obtained at about 300-450°C. However, the polysilicon grain size prepared by the CVD method is small, generally not exceeding 50nm, and there are many defects in the grain and many grain boundaries, so follow-up is required. oxidation and etching treatments.
在优选的实施例中,步骤i)中所述的多晶硅层采用准分子激光晶化(ELA)法在非晶硅表面上沉积得到。准分子激光晶化方法中,非晶硅薄膜的熔化结晶过程非常短,对衬底的热冲击很小,可以使用不耐高温的廉价玻璃甚至塑料衬底,大大降低了制作大面积显示器的成本。In a preferred embodiment, the polysilicon layer described in step i) is deposited on the surface of amorphous silicon by excimer laser crystallization (ELA). In the excimer laser crystallization method, the melting and crystallization process of the amorphous silicon film is very short, and the thermal impact on the substrate is very small, and cheap glass or even plastic substrates that are not resistant to high temperatures can be used, which greatly reduces the cost of making large-area displays .
准分子激光晶化是利用瞬间激光脉冲产生的高能量入射到非晶硅薄膜表面,仅在薄膜表层约100nm厚的深度产生热能效应,使a-Si薄膜在瞬间达到1000℃左右,从而实现a-Si向p-Si的转变。在此过程中,激光脉冲的瞬间(15~50ns)能量被a-Si薄膜吸收并转化为相变能,因此,不会有过多的热能传导到薄膜衬底,合理选择激光的波长和功率,使用激光加热就能够使a-Si薄膜达到熔化的温度且保证基片的温度低于500℃,可满足LCD及OEL对透明衬底的要求。其主要优点为脉冲宽度短(15~50ns),衬底发热小。通过选择还可获得混合晶化,即多晶硅和非晶硅的混合体。Excimer laser crystallization is to use the high energy generated by the instantaneous laser pulse to be incident on the surface of the amorphous silicon film, and only generate a thermal effect at a depth of about 100nm thick on the surface of the film, so that the a-Si film can reach about 1000°C in an instant, thereby realizing a -Si to p-Si transformation. During this process, the instantaneous (15-50ns) energy of the laser pulse is absorbed by the a-Si film and converted into phase transition energy. Therefore, there will not be too much thermal energy conducted to the film substrate, and the wavelength and power of the laser should be selected reasonably , using laser heating can make the a-Si film reach the melting temperature and ensure that the temperature of the substrate is lower than 500 ° C, which can meet the requirements of LCD and OEL for transparent substrates. Its main advantage is that the pulse width is short (15-50ns), and the substrate generates less heat. Mixed crystallization can also be obtained by selection, that is, a mixture of polycrystalline silicon and amorphous silicon.
准分子激光退火晶化的机理:激光辐射到a-Si的表面,使其表面在温度到达熔点时即达到了晶化域值能量密度Ec。a-Si在激光辐射下吸收能量,激发了不平衡的电子-空穴对,增加了自由电子的导电能量,热电子-空穴对在热化时间内用无辐射复合的途径将自身的能量传给晶格,导致近表层极其迅速的升温,由于非晶硅材料具有大量的隙态和深能级,无辐射跃迁是主要的复合过程,因而具有较高的光热转换效率,若激光的能量密度达到域值能量密度Ec时,即半导体加热至熔点温度,薄膜的表面会熔化,熔化的前沿会以约10m/s的速度深入材料内部,经过激光照射,薄膜形成一定深度的融层,停止照射后,融层开始以108~1010K/s的速度冷却,而固相和液相之间的界面将以1~2m/s的速度回到表面,冷却之后薄膜晶化为多晶,随着激光能量密度的增大,晶粒的尺寸增大,当非晶薄膜完全熔化时,薄膜晶化为微晶或多晶,若激光能量密度小于域值能量密度Ec,即所吸收的能量不足以使表面温度升至熔点,则薄膜不发生晶化。The mechanism of excimer laser annealing and crystallization: the laser irradiates the surface of a-Si, so that the surface reaches the crystallization threshold energy density Ec when the temperature reaches the melting point. a-Si absorbs energy under laser radiation, excites unbalanced electron-hole pairs, increases the conduction energy of free electrons, and heat electron-hole pairs recombine their own energy by non-radiative recombination within the thermalization time. Passed to the crystal lattice, resulting in an extremely rapid temperature rise near the surface. Since the amorphous silicon material has a large number of gap states and deep energy levels, the non-radiative transition is the main recombination process, so it has a high photothermal conversion efficiency. If the laser When the energy density reaches the threshold energy density Ec, that is, the semiconductor is heated to the melting point temperature, the surface of the film will melt, and the melting front will penetrate into the material at a speed of about 10m/s. After laser irradiation, the film forms a certain depth of melting layer. After stopping the irradiation, the molten layer starts to cool at a speed of 108-1010K/s, and the interface between the solid phase and the liquid phase returns to the surface at a speed of 1-2m/s. After cooling, the thin film crystallizes into polycrystalline, and then As the laser energy density increases, the grain size increases. When the amorphous film is completely melted, the film crystallizes into microcrystalline or polycrystalline. If the laser energy density is less than the threshold energy density Ec, the absorbed energy is insufficient. In order to raise the surface temperature to the melting point, the film does not crystallize.
一般认为ELA法制备得到的多晶硅薄膜晶粒大、空间选择性好,掺杂效率高、晶内缺陷相对较少、电学特性好、迁移率高达到400cm2/v.s,是目前综合性能最好的低温多晶硅薄膜。工艺成熟度高,已有大型的生产线设备,但存在晶粒尺寸对激光功率敏感的不足。It is generally believed that the polysilicon film prepared by the ELA method has large grains, good space selectivity, high doping efficiency, relatively few intragranular defects, good electrical properties, and a mobility as high as 400cm 2 /vs, which is the best comprehensive performance at present. Low temperature polysilicon thin film. The process maturity is high, and there are large-scale production line equipment, but there is a deficiency that the grain size is sensitive to the laser power.
具体的,采用准分子激光晶化(ELA)法制备多晶硅层的过程如下:Specifically, the process of preparing the polysilicon layer by using the excimer laser crystallization (ELA) method is as follows:
S1,采用CVD法在玻璃基板上依次沉积缓冲层(buffer layer)和非晶硅层(amorphous silicon layer);S1, sequentially depositing a buffer layer (buffer layer) and an amorphous silicon layer (amorphous silicon layer) on the glass substrate by CVD;
S2,对步骤S1中所述的非晶硅层进行高温加热处理以及准分子激光退火处理,形成多晶硅层。S2, performing high-temperature heating treatment and excimer laser annealing treatment on the amorphous silicon layer described in step S1 to form a polysilicon layer.
采用准分子激光晶化法制备多晶硅层的过程中在沉积缓冲层和非晶硅层之前,还可以预先对基板进行清洗,使基板保持洁净。In the process of preparing the polysilicon layer by adopting the excimer laser crystallization method, before depositing the buffer layer and the amorphous silicon layer, the substrate can also be cleaned in advance to keep the substrate clean.
其中S1步骤在基板上沉积缓冲层和非晶硅层的方法可以采用溅射、真空蒸镀或者减压CVD法。The method for depositing the buffer layer and the amorphous silicon layer on the substrate in the step S1 can be sputtering, vacuum evaporation or decompression CVD.
在一个实施例中,所述的缓冲层由氮化硅层(SiNx)和二氧化硅层(SiO2)组成复合缓冲层,缓冲层能够防止基板中的杂质在后续加热过程中扩散到多晶硅层中。首先沉积氮化硅层,厚度控制在50~150nm,然后再沉积二氧化硅层,其厚度控制在100~300nm。In one embodiment, the buffer layer is composed of a silicon nitride layer (SiN x ) and a silicon dioxide layer (SiO 2 ), and the buffer layer can prevent impurities in the substrate from diffusing into the polysilicon during subsequent heating. layer. A silicon nitride layer is firstly deposited with a thickness controlled at 50-150 nm, and then a silicon dioxide layer is deposited with a thickness controlled at 100-300 nm.
在基板上形成上述复合缓冲层的方法可为:The method for forming the above-mentioned composite buffer layer on the substrate can be:
在基板上先采用PECVD(Plasma Enhanced Chemical Vapor Deposition,等离子体增强化学气相沉积法)法或者其它沉积方法沉积一层SiNx层;再采用PECVD法或者其它沉积方法沉积一层SiO2层,从而在基板上形成复合缓冲层。A layer of SiNx is deposited on the substrate by PECVD (Plasma Enhanced Chemical Vapor Deposition) or other deposition methods; then a layer of SiO 2 is deposited by PECVD or other deposition methods, so that A composite buffer layer is formed on the substrate.
在另一个实施例中,缓冲层亦可为SiO2缓冲层。此时,在基板上形成该SiO2缓冲层的方法可为:在基板上采用PECVD法或者其它沉积方法沉积一层100~350nm厚的SiO2层作为SiO2缓冲层。In another embodiment, the buffer layer can also be a SiO 2 buffer layer. At this time, the method for forming the SiO 2 buffer layer on the substrate may be: deposit a 100-350 nm thick SiO 2 layer on the substrate as the SiO 2 buffer layer by using PECVD or other deposition methods.
在一个实施例中,所述的非晶硅层采用PECVD法沉积得到,优选非晶硅层的厚度为30~150nm。In one embodiment, the amorphous silicon layer is deposited by PECVD, and the thickness of the amorphous silicon layer is preferably 30-150 nm.
其中,S2步骤中所述的高温加热过程一般是在400℃~600℃的温度下处理0.5~3小时。Wherein, the high-temperature heating process described in step S2 is generally at a temperature of 400° C. to 600° C. for 0.5 to 3 hours.
所述S2步骤中的准分子激光退火处理采用氯化氙准分子激光器,可以根据非晶硅层的材质、厚度等特性,选择对非晶硅层进行一次、两次或者更多次的准分子激光退火以及设置每次准分子激光退火的工艺参数。The excimer laser annealing treatment in the S2 step adopts a xenon chloride excimer laser, and can select an excimer that performs one, two or more times on the amorphous silicon layer according to the characteristics such as the material and thickness of the amorphous silicon layer. Laser annealing and setting process parameters for each excimer laser annealing.
除此之外还可以采用氟化氪(KrF)、氟化氩(ArF)等准分子激光器。ArF、KrF和XeCl准分子激光器,输出波长分别为193nm、248nm和308nm,脉宽在10~50ns之间。In addition, excimer lasers such as krypton fluoride (KrF) and argon fluoride (ArF) can also be used. The output wavelengths of ArF, KrF and XeCl excimer lasers are 193nm, 248nm and 308nm respectively, and the pulse width is between 10 and 50ns.
在一个实施例中,进行一次准分子激光退火处理,控制激光能量密度为300~500mJ/cm2,激光脉冲频率可以为300Hz,优选的重叠率为92%~98%。In one embodiment, an excimer laser annealing treatment is performed once, the laser energy density is controlled to be 300-500 mJ/cm 2 , the laser pulse frequency may be 300 Hz, and the preferred overlap rate is 92%-98%.
在另一个实施例中对非晶硅层进行两次准分子激光退火,其中,第一次准分子激光退火的工艺参数为:激光脉冲频率为300Hz,重叠率为92%~98%,激光能量密度为300~500mJ/cm2;第二次准分子激光退火的工艺参数为:激光脉冲频率为300Hz,重叠率为5%~10%,激光能量密度为50~150mJ/cm2。In another embodiment, the amorphous silicon layer is subjected to excimer laser annealing twice, wherein the process parameters of the first excimer laser annealing are: the laser pulse frequency is 300 Hz, the overlap ratio is 92% to 98%, and the laser energy The density is 300-500mJ/cm 2 ; the technological parameters of the second excimer laser annealing are: the laser pulse frequency is 300Hz, the overlap rate is 5%-10%, and the laser energy density is 50-150mJ/cm 2 .
经准分子激光退火后形成多晶硅层,其表面会产生未晶化的非晶硅突起,存在比较明显的晶界,造成薄膜表面的不平坦,粗糙度升高。After excimer laser annealing, the polysilicon layer is formed, and uncrystallized amorphous silicon protrusions will appear on the surface, and there are relatively obvious grain boundaries, resulting in uneven surface of the film and increased roughness.
因此,本发明步骤i)先利用O3水与多晶硅层的表面接触进行氧化处理,通过O3水对多晶硅层的表面进行氧化,从而形成表面氧化层,通过控制氧化处理的时间来调节氧化层的厚度。Therefore, step i) of the present invention first utilizes O 3 water to contact the surface of the polysilicon layer for oxidation treatment, and oxidizes the surface of the polysilicon layer by O 3 water to form a surface oxide layer, and adjust the oxide layer by controlling the time of oxidation treatment thickness of.
在一个实施例中,氧化层的厚度为1~8nm,氧化处理的时间为3~100秒,优选氧化处理的时间为10~30秒。In one embodiment, the thickness of the oxide layer is 1-8 nm, and the oxidation treatment time is 3-100 seconds, preferably, the oxidation treatment time is 10-30 seconds.
由于O3水还具有清洗作用,因此利用O3水氧化的同时还能起到对多晶硅层清洗的作用,除去表面污染物,氧化处理后使非晶硅转化成二氧化硅。Since O 3 water also has a cleaning effect, the use of O 3 water to oxidize can also play a role in cleaning the polysilicon layer, removing surface pollutants, and transforming amorphous silicon into silicon dioxide after oxidation treatment.
本发明步骤ii)再通过HF溶液对氧化后的多晶硅层进行刻蚀,所述的HF溶液的浓度为0.5wt%~10wt%,优选的浓度为1wt%~5wt%,使二氧化硅与多晶硅脱离,在其中一个实施例中,HF溶液的(质量)浓度为1wt%~3wt%,优选蚀刻处理的时间为10~80秒。In step ii) of the present invention, the oxidized polysilicon layer is etched by HF solution, the concentration of the HF solution is 0.5wt% to 10wt%, and the preferred concentration is 1wt% to 5wt%, so that silicon dioxide and polysilicon For detachment, in one embodiment, the (mass) concentration of the HF solution is 1 wt% to 3 wt%, and the etching treatment time is preferably 10 to 80 seconds.
本发明步骤iii)的多次氧化/蚀刻处理能够显著降低多晶硅层表面的粗糙度,但多晶膜下面一般为SiOx膜,与晶界氧化后物质相似,易被蚀刻药剂蚀刻掉,形成空洞,因此不能过多进行表面氧化及蚀刻工艺。The multiple oxidation/etching treatments in step iii) of the present invention can significantly reduce the roughness of the surface of the polysilicon layer, but the polycrystalline film is generally under the SiOx film, which is similar to the substance after grain boundary oxidation, and is easily etched away by the etchant to form cavities , so the surface oxidation and etching processes cannot be performed too much.
本发明步骤iii)依次重复氧化处理和蚀刻处理过程1~5次,优选的,依次重复氧化处理和蚀刻处理过程1~3次,并精确控制蚀刻厚度。In step iii) of the present invention, the oxidation treatment and etching treatment are repeated 1 to 5 times in sequence, preferably, the oxidation treatment and etching treatment are repeated 1 to 3 times in sequence, and the etching thickness is precisely controlled.
本发明步骤i)所述的O3水是将臭氧溶解到水中得到的,O3水中臭氧的溶解浓度一般在5mg/L~20mg/L的范围中,优选的浓度控制在8mg/L~15mg/L,氧化处理的时间短。通过O3水的氧化处理的方式能够在多晶硅层的表面形成厚度均匀的氧化层,并且不会对下层的多晶硅造成不良影响。解决了现有采用高温氧气气氛热退火进行氧化的方式所存在的氧化效率低,时间长的问题。The O3 water described in step i) of the present invention is obtained by dissolving ozone into water, and the dissolved concentration of ozone in O3 water is generally in the range of 5 mg/L to 20 mg/L, and the preferred concentration is controlled at 8 mg/L to 15 mg /L, the oxidation treatment time is short. O 3 water oxidation treatment can form an oxide layer with a uniform thickness on the surface of the polysilicon layer without causing adverse effects on the underlying polysilicon layer. The method solves the problems of low oxidation efficiency and long time in the existing method of oxidation by thermal annealing in a high-temperature oxygen atmosphere.
本发明步骤ii)由于二氧化硅与氢氟酸发生化学反应,所以多晶硅层上的二氧化硅会与多晶硅层脱离,从而形成多晶硅薄膜。然后通过多次的氧化/蚀刻处理能够显著降低多晶硅层表面的粗糙度,但多晶膜下面一般为SiOx膜,与晶界氧化后物质相似,易被蚀刻药剂蚀刻掉,形成空洞,因此不能过多进行表面氧化及蚀刻工艺,且需精确控制蚀刻厚度。In step ii) of the present invention, due to the chemical reaction between silicon dioxide and hydrofluoric acid, the silicon dioxide on the polysilicon layer will separate from the polysilicon layer, thereby forming a polysilicon film. Then, the surface roughness of the polysilicon layer can be significantly reduced by multiple oxidation/etching treatments, but the polycrystalline film is generally under the SiO x film, which is similar to the substance after grain boundary oxidation, and is easily etched away by the etchant to form voids, so it cannot Excessive surface oxidation and etching processes are performed, and the etching thickness needs to be precisely controlled.
采用本发明提供的降低多晶硅表面粗糙度的方法得到的低温多晶硅薄膜,其晶粒分布均匀,并且具有非常低的表面粗糙度,从而解决了应用于低温多晶硅显示器背板中,迁移率较低,薄膜晶体管的漏电流较大,迁移率及阈值电压不均匀性的问题,并降低后续GI镀膜机台及IMP机台的工序时间,增加了产能。The low-temperature polysilicon thin film obtained by adopting the method for reducing the surface roughness of polysilicon provided by the present invention has uniform distribution of crystal grains and a very low surface roughness, thereby solving the problem of low mobility when applied to the backplane of a low-temperature polysilicon display. Thin film transistors have large leakage current, mobility and threshold voltage non-uniformity, and reduce the process time of subsequent GI coating machines and IMP machines, increasing production capacity.
采用本发明提供的降低多晶硅表面粗糙度的方法制备的低温多晶硅薄膜可以作为低温多晶硅薄膜晶体管的有源层,适用于有源矩阵有机发光二极管显示器(AMOLED)及低温多晶硅薄膜晶体管液晶显示器(LTPS TFT-LCD)等的生产。The low-temperature polysilicon film prepared by the method for reducing the surface roughness of polysilicon provided by the invention can be used as the active layer of a low-temperature polysilicon thin-film transistor, and is applicable to an active matrix organic light-emitting diode display (AMOLED) and a low-temperature polysilicon thin-film transistor liquid crystal display (LTPS TFT) -LCD) etc. production.
与现有技术相比,本发明的有益效果是:本发明利用O3水对多晶硅层表面进行氧化处理,由于O3的强氧化性,能够大幅缩短氧化时间。后续通过多次的氧化/蚀刻处理能够显著降低多晶硅膜表面的粗糙度,以减少薄膜晶体管(TFT device)的漏电流,优化其电性,并减少后续GI(栅绝缘层)镀膜机台及IMP机台的操作工序时间(tact time),增加产能。Compared with the prior art, the beneficial effect of the present invention is: the present invention uses O 3 water to oxidize the surface of the polysilicon layer, and due to the strong oxidizing property of O 3 , the oxidation time can be greatly shortened. Subsequent oxidation/etching treatments can significantly reduce the surface roughness of the polysilicon film to reduce the leakage current of the thin film transistor (TFT device), optimize its electrical properties, and reduce the subsequent GI (gate insulating layer) coating machine and IMP The operating process time (tact time) of the machine increases the production capacity.
附图说明Description of drawings
下面结合附图来对本发明作进一步详细说明。The present invention will be described in further detail below in conjunction with the accompanying drawings.
图1为本发明实施例2中未经氧化处理和蚀刻处理的多晶硅层的表面粗糙度示意图;1 is a schematic diagram of the surface roughness of a polysilicon layer without oxidation treatment and etching treatment in Example 2 of the present invention;
图2为本发明实施例2中经1次氧化处理和蚀刻处理后多晶硅层的表面粗糙度示意图;2 is a schematic diagram of the surface roughness of the polysilicon layer after one oxidation treatment and etching treatment in Example 2 of the present invention;
图3为本发明实施例2经n次氧化处理和蚀刻处理后多晶硅层的表面粗糙度示意图,其中n≥2且n为正整数。3 is a schematic diagram of the surface roughness of the polysilicon layer after n times of oxidation treatment and etching treatment in Example 2 of the present invention, wherein n≥2 and n is a positive integer.
具体实施方式detailed description
以下将结合附图及实施例来详细说明本发明的实施方式,借此对本发明如何应用技术手段来解决技术问题,并达成技术效果的实现过程充分理解并据以实施。需要说明的是,只要不构成冲突,本发明中的各个实施例中的各个特征可以相互结合,所形成的技术方案均在本发明的保护范围之内。The implementation of the present invention will be described in detail below in conjunction with the drawings and examples, so as to fully understand and implement the process of how to apply technical means to solve technical problems and achieve technical effects in the present invention. It should be noted that, as long as there is no conflict, each feature in each embodiment of the present invention can be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.
实施例Example
实施例1Example 1
本实施例中降低多晶硅表面粗糙度的方法包括以下步骤:The method for reducing the surface roughness of polysilicon in this embodiment comprises the following steps:
一、采用浓度为5mg/L的O3水与多晶硅层的表面接触进行氧化处理15秒,从而形成表面氧化层;1. Use O3 water with a concentration of 5 mg/L to contact the surface of the polysilicon layer for oxidation treatment for 15 seconds, thereby forming a surface oxide layer;
二、再将多晶硅层表面形成的表面氧化层与浓度为1wt%的HF溶液接触进行蚀刻处理40秒,得到经氧化处理和蚀刻处理的多晶硅层;2. Contacting the surface oxide layer formed on the surface of the polysilicon layer with an HF solution with a concentration of 1 wt% for 40 seconds to obtain an oxidized and etched polysilicon layer;
三、依次重复步骤一的氧化处理和步骤二的蚀刻处理过程3次,从而降低多晶硅表面粗糙度。3. Repeat the oxidation treatment of step 1 and the etching treatment of step 2 three times in sequence, thereby reducing the surface roughness of the polysilicon.
本实施例控制O3水的浓度较低,使每次氧化处理后的表面氧化层的厚度也较薄,后续采用浓度较低的HF溶液对表面具有氧化层的多晶硅进行刻蚀,由于二氧化硅与氢氟酸发生化学反应,所以多晶硅层上的二氧化硅与多晶硅层脱离,并控制氧化处理和蚀刻处理的时间,使晶界达到饱和氧化及蚀刻,但由于每次氧化处理得到的氧化层厚度较薄,因此步骤三重复的次数较多,从而达到实现降低多晶硅表面粗糙度的效果。In this embodiment, the concentration of O3 water is controlled to be low, so that the thickness of the surface oxide layer after each oxidation treatment is also relatively thin, and subsequent use of a lower concentration of HF solution to etch the polysilicon with an oxide layer on the surface, due to the oxidation Silicon and hydrofluoric acid react chemically, so the silicon dioxide on the polysilicon layer is separated from the polysilicon layer, and the time of oxidation treatment and etching treatment is controlled to make the grain boundary reach saturated oxidation and etching, but due to the oxidation of each oxidation treatment The thickness of the layer is relatively thin, so step 3 is repeated more times, so as to achieve the effect of reducing the surface roughness of the polysilicon.
本实施例选取的O3水和HF溶液均不会对薄膜晶体管的电性产生影响,其中更优化的O3水浓度、HF溶液浓度以及氧化/蚀刻处理时间,是使晶界达到饱和氧化及蚀刻。The O3 water and HF solution selected in this embodiment will not affect the electrical properties of the thin film transistor, and the more optimized O3 water concentration, HF solution concentration and oxidation/etching treatment time are to make the grain boundary reach saturated oxidation and etch.
实施例2Example 2
本实施例降低多晶硅表面粗糙度的方法按以下步骤实现:The method for reducing the surface roughness of polysilicon in this embodiment is realized in the following steps:
一、采用PECVD法在玻璃基板上依次沉积缓冲层和非晶硅层;1. The buffer layer and the amorphous silicon layer are sequentially deposited on the glass substrate by PECVD method;
二、对步骤一所述的非晶硅层在500℃下加热处理1.5小时,然后再对非晶硅层进行一次准分子激光退火处理,形成多晶硅层;2. Heat the amorphous silicon layer described in step 1 at 500° C. for 1.5 hours, and then carry out an excimer laser annealing treatment to the amorphous silicon layer to form a polysilicon layer;
三、采用浓度为10mg/L的O3水与步骤二形成的多晶硅层的表面接触进行氧化处理15秒,从而形成表面氧化层; 3. Oxidation treatment is carried out for 15 seconds in contact with the surface of the polysilicon layer formed in step 2 by using concentration of 10 mg/L of O water to form a surface oxide layer;
四、再将多晶硅层表面形成的表面氧化层与浓度为2wt%HF溶液接触进行蚀刻处理50秒,得到经氧化处理和蚀刻处理的多晶硅层;4. Contact the surface oxide layer formed on the surface of the polysilicon layer with a concentration of 2wt% HF solution for etching for 50 seconds to obtain a polysilicon layer that has been oxidized and etched;
五、依次再重复步骤三的氧化处理和步骤四的蚀刻处理过程n(n为正整数)次,从而降低多晶硅表面粗糙度。Fifth, repeating the oxidation treatment of step three and the etching treatment process of step four n (n is a positive integer) times in sequence, thereby reducing the surface roughness of the polysilicon.
本实施例优选O3水的HF溶液的浓度,并优化氧化处理和蚀刻处理的时间,使最终得到多晶硅的表面平整,晶界处最高高度小于25nm,显著降低了表面的粗糙度,从而减少了器件的漏电流。In this embodiment, the concentration of HF solution of O3 water is preferred, and the time of oxidation treatment and etching treatment is optimized, so that the surface of the finally obtained polysilicon is smooth, and the highest height at the grain boundary is less than 25nm, which significantly reduces the roughness of the surface, thereby reducing the device leakage current.
本实施例步骤五重复氧化处理和蚀刻处理的过程,结合附图1至3所示,图1中L代表多晶硅层,a代表基板,b代表缓冲层,d0代表未经氧化处理和蚀刻处理的非晶硅突起的高度,图2中d1代表经一次氧化处理和蚀刻处理后非晶硅突起的高度,类推,图3中dn代表经n次氧化处理和蚀刻处理后非晶硅突起的高度,可知经多次氧化处理和蚀刻处理能够使多晶硅表面更加平整,减少薄膜晶体管的漏电流,优化薄膜晶体管的电性。但多晶膜下面为SiOx膜,与晶界氧化后物质相似,易被蚀刻药剂蚀刻掉,形成空洞,难以干燥,因此不宜过多进行表面氧化及蚀刻工艺,且需精确控制蚀刻厚度,本实施例中优选再重复氧化处理和步骤四的蚀刻处理的次数为1次,即一共进行2次氧化处理和蚀刻处理。Step 5 of this embodiment repeats the process of oxidation treatment and etching treatment, as shown in conjunction with accompanying drawings 1 to 3, in Figure 1, L represents the polysilicon layer, a represents the substrate, b represents the buffer layer, d 0 represents no oxidation treatment and etching treatment The height of the amorphous silicon protrusions, d 1 in Figure 2 represents the height of the amorphous silicon protrusions after one oxidation treatment and etching treatment, and by analogy, d n in Figure 3 represents the amorphous silicon protrusions after n times of oxidation treatment and etching treatment It can be seen that the surface of the polysilicon can be made smoother after multiple oxidation treatments and etching treatments, the leakage current of the thin film transistor can be reduced, and the electrical properties of the thin film transistor can be optimized. However, under the polycrystalline film is a SiO x film, which is similar to the substance after grain boundary oxidation. It is easy to be etched away by etchant, forming cavities, and difficult to dry. In the embodiment, it is preferable to repeat the oxidation treatment and the etching treatment in Step 4 once more, that is, perform the oxidation treatment and the etching treatment twice in total.
本实施例对得到的降低粗糙度之后的多晶硅层(膜)进行微影蚀刻制程,通过光阻图案使多晶硅膜层图案化,以形成欲作为N-TFT和P-TFT的一多晶硅岛状物,然后接着沉积一栅极绝缘层。In this embodiment, a lithographic etching process is performed on the obtained polysilicon layer (film) after the roughness is reduced, and the polysilicon film layer is patterned through a photoresist pattern to form a polysilicon island to be used as an N-TFT and a P-TFT , and then deposit a gate insulating layer.
本实施例完成多晶硅膜层图案化后,再采用等离子CVD法在多晶硅表面沉积栅绝缘层(GI),该栅绝缘层可以为复合栅极绝缘层,复合栅极绝缘层由第一介电层、第二介电层和第三介电层组成,且第一介电层为SiO2,第二介电层为SiON,第三介电层为SiNx。由于此时多晶硅层的表面已足够平整,因此后续栅绝缘膜的厚度可以相对较薄,缩短后续GI镀膜机台及IMP机台的操作工序时间(tact time),增加其产能,并且还可直接利用现有生产线的激光退火前氟化氢清洗机进行处理。In this embodiment, after the patterning of the polysilicon film layer is completed, a gate insulating layer (GI) is deposited on the surface of the polysilicon by plasma CVD. , the second dielectric layer and the third dielectric layer, and the first dielectric layer is SiO 2 , the second dielectric layer is SiON, and the third dielectric layer is SiN x . Since the surface of the polysilicon layer is sufficiently flat at this time, the thickness of the subsequent gate insulating film can be relatively thin, which shortens the operating process time (tact time) of the subsequent GI coating machine and IMP machine, increases its production capacity, and can also directly Use the hydrogen fluoride cleaning machine before laser annealing in the existing production line for processing.
应当注意的是,以上所述的实施例仅用于解释本发明,并不构成对本发明的任何限制。通过参照典型实施例对本发明进行了描述,但应当理解为其中所用的词语为描述性和解释性词汇,而不是限定性词汇。可以按规定在本发明权利要求的范围内对本发明作出修改,以及在不背离本发明的范围和精神内对本发明进行修订。尽管其中描述的本发明涉及特定的方法、材料和实施例,但是并不意味着本发明限于其中公开的特定例,相反,本发明可扩展至其他所有具有相同功能的方法和应用。It should be noted that the above-mentioned embodiments are only used to explain the present invention, and do not constitute any limitation to the present invention. The invention has been described with reference to typical embodiments, but the words which have been used therein are words of description and explanation rather than words of limitation. The present invention can be modified within the scope of the claims of the present invention as prescribed, and the present invention can be revised without departing from the scope and spirit of the present invention. Although the invention described therein refers to specific methods, materials and examples, it is not intended that the invention be limited to the specific examples disclosed therein, but rather, the invention extends to all other methods and applications having the same function.
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