CN114664756A - A kind of silicon carbide power device and preparation method thereof - Google Patents

Abstract

The invention relates to a silicon carbide power device and a preparation method thereof, wherein the silicon carbide power device comprises a chip, a PA passivation layer and a PI passivation layer; the chip comprises N connected in sequence from bottom to top⁺Substrate, N^‑An epitaxial layer and a metal layer; the area of the metal layer is smaller than N^‑The area of the epitaxial layer; the PA passivation layer is deposited on the surface of the metal layer and exposed N^‑A first concave window is arranged in the middle of the PA passivation layer on the surface of the epitaxial layer, and the bottom surface of the first concave window is the surface of the metal layer; a second concave window is arranged in the edge area of the PA passivation layer close to the silicon carbide power device, and the bottom surface of the second concave window is N^‑A surface of the epitaxial layer; a PI passivation layer is deposited on the material surface of the PA passivation layer and filled in the second recess window. The capacity of the device for preventing water vapor from entering the device to corrode the chip is improved, and the reliability of the device in a limit application scene is enhanced.

Description

A kind of silicon carbide power device and preparation method thereof

technical field

The invention relates to the technical field of preparation of silicon carbide power devices, in particular to a silicon carbide power device and a preparation method thereof.

Background technique

Silicon carbide power devices have the advantages of high blocking voltage, low on-state resistance, high frequency, and high temperature resistance, and have wide application prospects.

Silicon carbide power devices mainly include chips and passivation structures deposited on the chips. Among them, as shown in FIG. 1, the chip 1 includes an N ⁺ substrate (N ⁺ Substrate) 11, an N ^- epitaxial layer (N ^- EPI ⁾ 12 and a metal layer 13 in order from bottom to top ^. ) 12 The exposed part and the surface of the metal layer 13 are deposited with a passivation structure, the passivation structure is PA passivation layer 2 and PI passivation layer 3 from bottom to top, and in the middle of PA passivation layer 2 and PI passivation layer 3 The location etch leaks out the metal layer 13, that is, the anode metal contact window. A PA passivation layer 2 and a PI passivation layer 3 are formed around the chip. The PI passivation layer is mainly used to block the water vapor in the air outside the device from entering the device and eroding the chip inside the device when the device is applied.

However, due to the different thermal expansion coefficients of the PI passivation layer and the PA passivation layer, as the chip works, the chip temperature rises to dissipate heat, which causes the PA passivation layer and the PI passivation layer to be heated and the temperature rises. In extreme application scenarios ( For example, under high temperature and high humidity environment), the local area between the PI passivation layer and the PA passivation layer is more prone to separation, edge warping and delamination, etc. The PI passivation layer prevents the water vapor in the air outside the device from entering the device and corroding The capability of the chip is weakened, thereby affecting the reliability of the long-term operation of the device.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a silicon carbide power device and a preparation method thereof in view of the problems that the PA passivation layer and the PI passivation layer in the prior art silicon carbide power device will be separated due to heating, edge warping and delamination. It solves the problems of separation, edge warping and delamination when heated, thereby improving the device's ability to prevent water vapor from entering the device and eroding the chip, and enhancing the reliability of the device in extreme application scenarios.

In order to achieve the above object, the technical scheme adopted in the present invention is:

A silicon carbide power device, comprising a chip, a PA passivation layer and a PI passivation layer;

The chip includes an N ⁺ substrate ^, an N- epitaxial layer and a metal layer connected in sequence from bottom to top; the area of the metal layer is smaller than the area ^of the N- epitaxial layer;

The PA passivation layer is deposited on the surface of the metal layer and the surface of the exposed N ^- epitaxial layer, the middle of the PA passivation layer is provided with a first concave window, and the bottom surface of the first concave window is metal The surface of the layer; the PA passivation layer is provided with a second recessed window near the edge region of the silicon carbide power device, and the bottom surface of the second recessed window is the surface of the N ^- epitaxial layer; the second recessed window surrounds the metal Connecting grooves provided by the layer;

A PI passivation layer is deposited on the material surface of the PA passivation layer and filled inside the second recessed window.

In the silicon carbide power device provided by this application, a second recessed window is set in the PA passivation layer, the PI passivation layer is deposited on the material surface of the PA passivation layer, filled in the inside of the second window, and the glue of the PI passivation layer is cured Then, the PI passivation layer is directly embedded in the PA passivation layer to form a mechanical interlocking structure, which enhances the tight connection between the PI passivation layer and the PA passivation layer, and increases the limit ability of the two passivation layers to resist the force together. It solves the problems of separation, edge warping and delamination when heated; thereby improving the device's ability to prevent water vapor from entering the device and eroding the chip, and enhancing the reliability of the device in extreme application scenarios.

Further, the area of the first recessed window is smaller than that of the metal layer.

Further, the second recessed window is an annular communication groove provided around the metal layer.

Further, the PA passivation layer is provided with at least two second recess windows arranged at intervals near the edge region, and the distance between adjacent second recess windows is more than 5um. A suitable spacing distance can ensure the tightness of the PI passivation layer and the PA passivation layer.

Further, the width of the groove of the second recessed window is more than 5um. Appropriate groove width can ensure that the PI passivation layer can be completely filled into the groove of the PA passivation layer.

Further, the length of the second recessed window from the edge of the silicon carbide power device is more than 5um. Further, the surface of the N ^- epitaxial layer is divided into an active region, a terminal region and a safety distance region in turn from the inside to the outside; the second recessed window is located within the safety distance region. The safety distance is due to the fact that the silicon carbide material is harder than the silicon material, and the silicon carbide chip is more prone to edge cracking during slicing. For the reliability and yield of the chip, even if there are some small cracks on the edge of the slicing, it will not extend to the terminal area. A safe distance is reserved between the terminal area and the slicing lane. The second recessed window is arranged within the safe distance area, which can be completely avoided. Some potential hidden dangers may be brought to the chip terminal area due to the addition of the second recessed window.

Further, the length distance between the second recessed window and the edge of the silicon carbide power device is more than 5um; the length of the second recessed window from the terminal region of the N ^- epitaxial layer (N ^- EPI) is more than 5um.

Further, the chip further includes a field oxide layer, the field oxide layer is disposed on the surface of the exposed N ^- epitaxial layer, and the PA passivation layer is deposited on the surface of the metal layer and the surface of the field oxide layer , the bottom surface of the second recessed window is the surface of the field oxygen layer, and the second recessed window is located in the vertical virtual space of the safe distance area. The adhesion between the PI glue and the field oxygen layer is better, and the stability of the PI glue and the PA passivation layer is increased.

Further, the field oxygen layer is a silicon dioxide material layer.

Further, the PA passivation layer is a silicon dioxide material layer and/or a silicon nitride material layer; the thickness of the PA passivation layer is 0.5um-3um; the PI passivation layer is a polyimide material layer; PI passivation layer The thickness of the chemical layer is more than 1um.

Another object of the present invention is to provide a method for preparing the above silicon carbide power device.

A method for preparing a silicon carbide power device as above, comprising the following steps:

Step 1. Deposit PA passivation layer material on the surface of the chip;

Step 2: Perform photoresist coating on the surface of the PA passivation layer material in the step 1, and then perform exposure and development processing, so that the developed photoresist surface forms the mask area of the first recessed window and the first recessed window. 2. The mask area of the recessed window;

Step 3. Using dry etching, along the mask area of the first recessed window and the mask area of the second recessed window, the surface of the PA passivation layer material is downwardly formed to form a first recessed window and a second recessed window; remove photoresist to form a PA passivation layer on the surface of the chip;

Step 4. Coat the PI glue on the PA passivation layer, so that the PI glue covers the surface of the PA passivation layer material and the top of the first recessed window and fills the inside of the second recessed window, and then apply the PI glue Expose and develop to remove the PI glue on the top of the first recessed window to form a PI passivation layer;

Step 5, curing the structural member obtained in the step 4.

The preparation method of the silicon carbide power device provided by the present application cleverly utilizes the good flatness characteristics of PI glue during coating, and the PI glue will completely fill into the groove during coating, which is a simple and direct , Effective preparation method, no need to add additional process at all, only need to modify the mask lithography pattern of the PA passivation layer, the whole preparation method is simple and reliable, and does not affect the performance and yield of the finished product.

Further, in the step 5, the curing temperature is 350° C.˜450° C.; and the curing time is 120 min˜180 min. Preferably, in the step 5, the curing temperature is 400°C to 450°C, and the curing time is 150min to 180min.

To sum up, due to the adoption of the above-mentioned technical solutions, the beneficial effects of the present invention are:

1. In the silicon carbide power device provided by this application, a second recessed window is set in the PA passivation layer, the PI passivation layer is deposited on the material surface of the PA passivation layer, and filled in the interior of the second recessed window, and the PI passivation layer is After the adhesive is cured, the PI passivation layer is directly embedded in the PA passivation layer to form a mechanical interlocking structure, which enhances the tight connection between the PI passivation layer and the PA passivation layer, and increases the resistance of the two passivation layers to the opposing force. The ultimate ability solves the problems of separation, edge warping and delamination when heated; thereby improving the device's ability to prevent water vapor from entering the device and eroding the chip, and enhancing the reliability of the device in extreme application scenarios. 2. Compared with the original device structure, the silicon carbide power device prepared in this application is only changed in the PA passivation layer and the PI passivation layer above the safety distance. This change will not bring about the performance and yield of the chip itself. Any adverse effects, instead, enhance the reliability in extreme application scenarios.

3. The preparation method of the silicon carbide power device provided in this application cleverly utilizes the good flatness characteristics of PI glue during coating, and the PI glue will completely fill into the groove during coating, which is a simple , Direct and effective preparation method, does not need to add additional process at all, only needs to modify the mask lithography pattern of the PA passivation layer, the whole preparation method is simple and reliable, and does not affect the performance and yield of the finished product.

Description of drawings

FIG. 1 is a schematic structural diagram of a silicon carbide power device in the prior art.

FIG. 2 is a schematic diagram of structural changes of the silicon carbide power device prepared in Example 1. FIG.

FIG. 3 is a schematic structural diagram of the silicon carbide power device prepared in Example 1. FIG.

Figure 4 is a schematic top view of Figure 2e.

Icons: 1-chip; 11-N ⁺ substrate; 12-N ^- epitaxial layer; 121-active region; 122-terminal region; 123-safety distance region; 13-metal layer; 14-field oxygen layer; 2- PA passivation layer; 21-first recessed window; 22-second recessed window; 3-PI passivation layer; 4-photoresist.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings.

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

Example 1

Fabrication of silicon carbide power devices

as shown in picture 2.

Step 1, depositing a PA passivation layer material on the surface of the chip 1; as shown in FIG. 2a-FIG. 2b.

Step 2, apply photoresist 4 on the surface of the PA passivation layer material in step 1, and then perform exposure and development processing, so that the developed photoresist surface forms the mask area of the first recessed window and Mask area of the second recessed window; as shown in Figure 2c.

Step 3. Use dry etching to form a first recessed window 21 and a second recessed window 22 from the surface of the PA passivation layer material along the mask area of the first recessed window and the masked area of the second recessed window. ; Remove the photoresist 4, thereby forming a PA passivation layer 2 on the surface of the chip;

Step 4. Coat the PI glue on the PA passivation layer 2, so that the PI glue covers the surface of the PA passivation layer material and the top of the first recessed window 21 and fills the interior of the second recessed window 22, and then The PI glue is exposed and developed to remove the PI glue on the top of the first recessed window 21 to form a PI passivation layer 3; as shown in FIG. 2f.

Step 5. Perform curing treatment on the structural member obtained in the step 4, and the curing temperature is 350° C.; and the curing time is 180 minutes.

A schematic diagram of the finished product structure of the silicon carbide power device prepared in Example 1 is shown in FIG. 3 .

Silicon carbide power device, including chip 1, PA passivation layer 2 and PI passivation layer 3;

The chip 1 includes an N ⁺ substrate 11 ^, an N- epitaxial layer 12 and a metal layer 13 connected in sequence from bottom to top; the area of the metal layer 13 is smaller than the area ^of the N- epitaxial layer 12; the chip 1 also comprising a field oxide layer 14, the field oxide layer 14 is disposed on the surface of the exposed N ^- epitaxial layer 12;

The PA passivation layer 2 is deposited on the surface of the metal layer 13 and the surface of the field oxide layer 14 . A first recessed window 21 is provided in the middle of the PA passivation layer 2 . The bottom surface is the surface of the metal layer 13; the edge region of the PA passivation layer 2 close to the silicon carbide power device is provided with two second recessed windows 22 spaced from the outside to the inside, and the second recessed windows 22 are surrounding the metal. The annular communication groove provided in the layer 13, the bottom surface of the second concave window 22 is the surface of the field oxygen layer 14; the groove width of the second concave window 22 is 5um; adjacent to the second concave window 22 The spacing is 5um.

Wherein, the surface of the N ^- epitaxial layer 12 is divided into an active region 121, a terminal region 122 and a safety distance region 123 in turn from the inside to the outside; the length of the safety distance region 123 is 30um, and the second recessed window 22 is located in the within the vertical virtual space of the safety distance area 123; the length distance between the second recessed window 22 and the edge of the silicon carbide power device is 5um; the distance between the second recessed window 22 and the N ^- epitaxial layer (N ^- EPI) 12 The length of the terminal area 122 is 5um.

Wherein, the PA passivation layer 2 is a 1um silicon dioxide material layer and a 1um silicon nitride material layer. The PI passivation layer 3 is a 5um thick polyimide material layer. The field oxygen layer 14 is a 1um silicon dioxide material layer.

After testing, the silicon carbide power device prepared in Example 1 solves the problems of separation, edge warping and delamination when heated; it improves the device's ability to prevent water vapor from entering the device and erodes the chip, and enhances the device in extreme application scenarios. reliability.

Example 2

Fabrication of silicon carbide power devices

The silicon carbide power device was prepared by the same method as in Example 1, except that the process parameters and the material thickness of the PA passivation layer and the PI passivation layer were changed.

Step 1, depositing a PA passivation layer material on the surface of the chip 1 .

Step 2: Apply photoresist 4 on the surface of the PA passivation layer material in step 1, and then perform exposure and development processing, so that the developed photoresist surface forms the mask area of the first recessed window and the Mask area of the second recessed window.

Step 3. Use dry etching to form a first recessed window 21 and a second recessed window 22 from the surface of the PA passivation layer material along the mask area of the first recessed window and the masked area of the second recessed window. ; Remove the photoresist 4, thereby forming the PA passivation layer 2 on the surface of the chip;

Step 4. Coat the PI glue on the PA passivation layer 2, so that the PI glue covers the surface of the PA passivation layer material and the top of the first recessed window 21 and fills the interior of the second recessed window 22, and then The PI glue is exposed and developed to remove the PI glue on the top of the first recessed window 21 to form the PI passivation layer 3 .

Step 5. Perform curing treatment on the structural member obtained in the step 4, and the curing temperature is 450°C; the curing time is 120°C.

Silicon carbide power device prepared in Example 2

Silicon carbide power device, including chip 1, PA passivation layer 2 and PI passivation layer 3;

The chip 1 includes, from bottom to top, an N ⁺ substrate 11 , an N ⁻ epitaxial layer 12 and a metal layer 13 connected in sequence; the area of the metal layer 13 is smaller than the area of the N ⁻ epitaxial layer 12 ;

The PA passivation layer 2 is deposited on the surface of the metal layer 13 and on the surface of the exposed N ^- epitaxial layer 12. A first recess window 21 is provided in the middle of the PA passivation layer 2. The first recess The bottom surface of the window 21 is the surface of the metal layer 13; the PA passivation layer 2 is provided with several second recessed windows 22 arranged at intervals near the edge region of the silicon carbide power device, and the bottom surface of the second recessed window 22 is N ^- the surface of the epitaxial layer 12; the distance between the adjacent second recess windows 22 is 5um.

Wherein, the surface of the N- epitaxial layer 12 is divided into an active region 121 , a terminal region 122 and a safety distance region 123 sequentially from inside to outside; the second recessed window 22 is located within the safety distance region 123 .

Among them, the PA passivation layer 2 is a 0.5um silicon dioxide material layer and a 1um silicon nitride material layer. The PI passivation layer 3 is a 4um thick polyimide material layer.

After testing, the silicon carbide power device prepared in Example 2 solves the problems of separation, edge warping and delamination when heated; it improves the device's ability to prevent water vapor from entering the device and erodes the chip, and enhances the device in extreme application scenarios. reliability.

In the silicon carbide power device provided by this application, a second recessed window is set in the PA passivation layer, the PI passivation layer is deposited on the material surface of the PA passivation layer, and filled in the inside of the second window, after the PI passivation layer is cured, The PI passivation layer is directly embedded in the PA passivation layer to form a mechanical interlocking structure, which enhances the close connection between the PI passivation layer and the PA passivation layer, increases the limit ability of the two passivation layers to resist the force together, and solves the problem. When heated, problems such as separation, edge warping and delamination will occur; thus, the ability of the device to prevent water vapor from entering the device and eroding the chip is improved, and the long-term reliability of the device in extreme application scenarios is enhanced.

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (10)

1. A silicon carbide power device, characterized by comprising a chip (1), a PA passivation layer (2) and a PI passivation layer (3); The chip (1) includes an N ⁺ substrate (11), an N ^- epitaxial layer (12) and a metal layer (13) connected in sequence from bottom to top; the metal layer (13) is smaller in area than the N ^- epitaxial layer the area of the layer (12); The PA passivation layer (2) is deposited on the surface of the metal layer (13) and on the surface of the exposed N ^- epitaxial layer (12), and a first depression is provided in the middle of the PA passivation layer (2) A window (21), the bottom surface of the first recessed window (21) is the surface of the metal layer (13); the PA passivation layer (2) is provided with a second recessed window (22) near the edge region of the silicon carbide power device ), the bottom surface of the second recessed window (22) is the surface of the N ^- epitaxial layer (12); the second recessed window (22) is a communication groove provided around the metal layer (13); A PI passivation layer (3) is deposited on the material surface of the PA passivation layer (2) and filled inside the second recessed window (22). 2 . The silicon carbide power device according to claim 1 , wherein the second recessed window ( 22 ) is an annular communication groove provided around the metal layer ( 13 ). 3 . 3 . The silicon carbide power device according to claim 1 , wherein the groove width of the second recessed window ( 22 ) is more than 5um. 4 . 4 . The silicon carbide power device according to claim 1 , characterized in that, the PA passivation layer ( 2 ) is provided with at least two second recess windows ( 22 ) arranged at intervals adjacent to the edge region. 5 . The spacing of the second recessed windows (22) is more than 5um. 5 . The silicon carbide power device according to claim 1 , wherein the surface of the N ^- epitaxial layer ( 12 ) is divided into an active region ( 121 ), a terminal region ( 122 ) and a safety distance in turn from inside to outside. 6 . zone (123); the second recessed window (22) is located within the safety distance zone (123). 6 . The silicon carbide power device according to claim 5 , wherein the length distance between the second recessed window ( 22 ) and the edge of the silicon carbide power device is more than 5um; the distance between the second recessed window ( 22 ) The length of the terminal region (122) of the N ^- epitaxial layer (12) is 5um or more. 7 . The silicon carbide power device according to claim 6 , wherein the chip ( 1 ) further comprises a field oxygen layer ( 14 ), and the field oxygen layer ( 14 ) is arranged on the exposed N ^- epitaxial layer ( 7 . 12), the PA passivation layer (2) is deposited on the surface of the metal layer (13) and the surface of the field oxide layer (14), and the bottom surface of the second recessed window (22) is a field On the surface of the oxygen layer (14), the second concave window (22) is located in the vertical virtual space of the safe distance zone (123). 8. The silicon carbide power device according to any one of claims 1-7, wherein the PA passivation layer (2) is a silicon dioxide material layer and/or a silicon nitride material layer; the PA passivation layer ( 2) The thickness is 0.5 um-3 um; the PI passivation layer (3) is a polyimide material layer; the thickness of the PI passivation layer (3) is 1 um or more. 9. A preparation method of a silicon carbide power device according to any one of claims 1-8, characterized in that, comprising the following steps: Step 1, depositing a PA passivation layer material on the surface of the chip (1); Step 2: Coating the photoresist (4) on the surface of the PA passivation layer material in the step 1, and then performing exposure and development processing, so that a mask for the first recessed window is formed on the surface of the developed photoresist area and mask area of the second recessed window; Step 3. Using dry etching, the surface of the PA passivation layer material is formed downward along the mask area of the first recess window and the mask area of the second recess window to form a first recess window (21) and a second recess window (22); removing the photoresist (4), thereby forming a PA passivation layer (2) on the surface of the chip; Step 4. Coat the PI glue on the PA passivation layer (2), so that the PI glue covers the surface of the PA passivation layer material and the top of the first recessed window (21) and fills the second recessed window ( 22), then expose the PI glue and develop it to remove the PI glue on the top of the first recessed window (21) to form a PI passivation layer (3); Step 5, curing the structural member obtained in the step 4. 10 . The method for preparing a silicon carbide power device according to claim 9 , wherein, in the step 5, the curing temperature is 350° C.˜450° C.; and the curing time is 120 min˜180 min. 11 .

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