CN114613873A - Transistor photodetector and preparation method thereof - Google Patents
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Abstract
本公开提供一种晶体管型光电探测器,包括:第一电极;第二电极,第二电极与第一电极间隔开;沟道层,沟道层至少设置在第一电极与第二电极之间;光敏层,光敏层设计为p‑i‑n异质结结构,光敏层的材料由需要探测的波段所决定;以及介质层,介质层设置沟道层与光敏层之间。本公开还提供了一种晶体管型光电探测器及其制备方法。
The present disclosure provides a transistor-type photodetector, comprising: a first electrode; a second electrode, the second electrode being spaced apart from the first electrode; a channel layer, the channel layer being disposed at least between the first electrode and the second electrode ; a photosensitive layer, the photosensitive layer is designed as a p-i-n heterojunction structure, and the material of the photosensitive layer is determined by the wavelength band to be detected; and a dielectric layer, the dielectric layer is arranged between the channel layer and the photosensitive layer. The present disclosure also provides a transistor-type photodetector and a preparation method thereof.
Description
技术领域technical field
本公开涉及一种晶体管型光电探测器及其制备方法。The present disclosure relates to a transistor-type photodetector and a preparation method thereof.
背景技术Background technique
光电探测器是一种把光信号转换为电信号的功能器件。根据探测光的波长,可以分为紫外、可见光、红外、太赫兹探测器。特别是,红外探测器在军事(遥感、瞄准、夜视、隐身、制导)、航天、生物诊断、民用(自动驾驶、手机红外镜头、智能家居、无线感应、气体监测)等诸多领域具有重要的应用价值。A photodetector is a functional device that converts optical signals into electrical signals. According to the wavelength of the detected light, it can be divided into ultraviolet, visible light, infrared, and terahertz detectors. In particular, infrared detectors have important applications in military (remote sensing, aiming, night vision, stealth, guidance), aerospace, biodiagnosis, civil (autonomous driving, mobile phone infrared lenses, smart home, wireless sensing, gas monitoring) and many other fields. Value.
目前商用光电探测器基于硅、锗、铟镓砷、碲化铟、碲镉汞等半导体材料。但是硅的截止波长短(只有1100nm),只能用于可见、近红外探测。锗的截止波长达到1.7um,但是性能差(间接带隙、暗电流大、饱和电流低),目前大多已经被铟镓砷取代。而铟镓砷、碲镉汞需要在三五族、CdTe或ZnCdTe基底上进行外延生长,合成难度大、工艺复杂且成本高,并且与硅基读出电路不兼容,需要用铜柱或铟柱进行异质键合(bonding),且大多需要额外的制冷装置,这导致目前高性能的红外探测器和芯片价格昂贵。Commercial photodetectors are currently based on semiconductor materials such as silicon, germanium, indium gallium arsenide, indium telluride, and mercury cadmium telluride. However, the cut-off wavelength of silicon is short (only 1100nm) and can only be used for visible and near-infrared detection. The cut-off wavelength of germanium reaches 1.7um, but its performance is poor (indirect band gap, large dark current, low saturation current), and most of them have been replaced by indium gallium arsenide. However, indium gallium arsenide and mercury cadmium telluride need to be epitaxially grown on III-V, CdTe or ZnCdTe substrates, which are difficult to synthesize, complex in process and high in cost, and incompatible with silicon-based readout circuits, requiring copper pillars or indium pillars. Heterogeneous bonding is performed, and additional cooling devices are mostly required, which makes current high-performance infrared detectors and chips expensive.
为了提升外量子效率,目前设计了Photogating(光门控)型光电探测器,即采用高吸收系数的PbS、钙钛矿等量子点与碳纳米管形成Ⅱ类异质结,光生载流子在两者的界面分离而形成额外电场调制。这类器件往往能获得较高增益,但响应和恢复速度较慢。2017年,Frank Koppens等人报道了基于石墨烯/PbS量子点的Photogating型短波红外探测器及其288×388像素规模的焦平面图像传感器,器件的响应度高达107A/W、比探测率最高为7×1013Jones,但是存在速度慢(响应时间10ms,需要栅压脉冲强制恢复)、动态范围小、开关比低等问题。2021年,中国科学院金属研究所的孙东明等采用CsPbBr3与碳纳米管构建Photogating型光电探测器,对可见光405、516nm的响应度达到107A/W、D*达到1016Jones,但响应时间为数十ms-s,还需要加额外的栅压脉冲强制探测器恢复到基线。In order to improve the external quantum efficiency, a Photogating (light-gating) type photodetector is currently designed, that is, quantum dots such as PbS and perovskite with high absorption coefficient are used to form a type II heterojunction with carbon nanotubes. The interface of the two separates to form additional electric field modulation. Such devices tend to achieve higher gain, but slower response and recovery. In 2017, Frank Koppens et al. reported a photogating short-wave infrared detector based on graphene/PbS quantum dots and a focal plane image sensor with a scale of 288 × 388 pixels. The highest is 7×10 13 Jones, but there are problems such as slow speed (response time 10ms, forced recovery of gate voltage pulse), small dynamic range, and low switching ratio. In 2021, Sun Dongming and others from the Institute of Metal Research, Chinese Academy of Sciences used CsPbBr 3 and carbon nanotubes to build a Photogating photodetector, with a responsivity of 10 7 A/W for visible light at 405 and 516 nm, and a D* of 10 16 Jones, but the response The time is tens of ms-s, and additional grid voltage pulses are required to force the detector to return to the baseline.
此外,随着碳纳米管技术的发展,碳纳米管逐渐用于器件中。但是碳纳米管在诸如红外的光电探测领域至今未研究出实用的光电探测器,主要原因有以下几点:1、单根或薄膜碳纳米管的光吸收有限,外量子效率低;2、BFBD是较为理想的碳纳米管二极管架构,但内建电场仅在源漏接触附近约50nm的区域,受衍射极限的限制红外探测器的像元尺寸多大于1um,因此BFBD器件很难得获得较高的信噪比;3、Photogating结构是克服量子效率低、内建电场范围小的一个重要途径,但是在当前的Photogating型器件架构下,光电探测器的性能欠佳,且存在响应度/外量子效率和速度的矛盾。In addition, with the development of carbon nanotube technology, carbon nanotubes are gradually used in devices. However, carbon nanotubes have not yet developed practical photodetectors in the field of photodetection such as infrared. The main reasons are as follows: 1. The light absorption of single or thin-film carbon nanotubes is limited and the external quantum efficiency is low; 2. BFBD It is an ideal carbon nanotube diode structure, but the built-in electric field is only in the area of about 50nm near the source-drain contact, limited by the diffraction limit, the pixel size of infrared detectors is mostly larger than 1um, so it is difficult for BFBD devices to obtain higher. Signal-to-noise ratio; 3. Photogating structure is an important way to overcome low quantum efficiency and small built-in electric field range, but under the current photogating device architecture, the performance of photodetectors is not good, and there is a responsivity/external quantum efficiency conflict with speed.
因此,如何设计新的光电探测器结构来突破当前的困境是所需要解决的问题。Therefore, how to design a new photodetector structure to break through the current predicament is a problem that needs to be solved.
发明内容SUMMARY OF THE INVENTION
为了解决上述技术问题之一,本公开提供了一种晶体管型光电探测器及其制备方法。根据本公开的技术方案,可以获得较快的相应速度、较高的响应度/外量子效率和较大的信噪比。In order to solve one of the above technical problems, the present disclosure provides a transistor-type photodetector and a preparation method thereof. According to the technical solution of the present disclosure, a faster corresponding speed, a higher responsivity/external quantum efficiency and a larger signal-to-noise ratio can be obtained.
根据本公开的一个方面,一种晶体管型光电探测器,包括:According to one aspect of the present disclosure, a transistor-type photodetector includes:
第一电极;the first electrode;
第二电极,所述第二电极与所述第一电极间隔开;a second electrode spaced apart from the first electrode;
沟道层,所述沟道层至少设置在所述第一电极与所述第二电极之间;a channel layer, the channel layer is at least disposed between the first electrode and the second electrode;
光敏层,所述光敏层设计为p-i-n异质结结构,所述光敏层的材料由需要探测的波段所决定;以及A photosensitive layer, the photosensitive layer is designed as a p-i-n heterojunction structure, and the material of the photosensitive layer is determined by the wavelength band to be detected; and
介质层,所述介质层设置所述沟道层与所述光敏层之间。A dielectric layer is provided between the channel layer and the photosensitive layer.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述介质层用于将所述光敏层的内建电场的电场信号变化以电容耦合方式作用至所述沟道层。According to the transistor-type photodetector of at least one embodiment of the present disclosure, the dielectric layer is used for applying the electric field signal change of the built-in electric field of the photosensitive layer to the channel layer in a capacitive coupling manner.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述介质层为高介电常数介质层。According to the transistor-type photodetector of at least one embodiment of the present disclosure, the dielectric layer is a high dielectric constant dielectric layer.
根据本公开的至少一个实施方式的晶体管型光电探测器,还包括:栅极及栅绝缘层,所述栅绝缘层配置在所述沟道层与所述栅极之间。The transistor-type photodetector according to at least one embodiment of the present disclosure further includes a gate electrode and a gate insulating layer, the gate insulating layer being disposed between the channel layer and the gate electrode.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述晶体管型光电探测器配置为全局底栅结构,所述全局底栅结构中的基底为掺杂的基底并且作为所述栅极;或者A transistor-type photodetector according to at least one embodiment of the present disclosure, the transistor-type photodetector being configured as a global bottom gate structure in which a substrate is a doped substrate and serves as the gate; or
所述晶体管型光电探测器配置为局部底栅结构,其中所述局部底栅结构包括基底,所述栅极形成于该基底中。The transistor-type photodetector is configured as a partial bottom gate structure, wherein the partial bottom gate structure includes a substrate in which the gate is formed.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述晶体管型光电探测器配置为顶栅结构,在所述顶栅结构包括基底,所述基底为透明基底且设置在所述光敏层之下,所述栅绝缘层设置在所述沟道层之上。A transistor-type photodetector according to at least one embodiment of the present disclosure, the transistor-type photodetector is configured as a top gate structure, the top gate structure includes a substrate, the substrate is a transparent substrate and is disposed on the photosensitive layer Below, the gate insulating layer is disposed on the channel layer.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述光敏层的外侧设计有功能层,所述功能层为滤光层、减反膜和封装层中的至少一种。According to the transistor-type photodetector of at least one embodiment of the present disclosure, a functional layer is designed on the outer side of the photosensitive layer, and the functional layer is at least one of a filter layer, an antireflection film, and an encapsulation layer.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述光敏层的p-i-n异质结结构中的p-i结与i-n之间设计有功能层,所述功能层用于实现能带匹配、或提高机械和电学稳定性。According to the transistor-type photodetector of at least one embodiment of the present disclosure, a functional layer is designed between the p-i junction and the i-n in the p-i-n heterojunction structure of the photosensitive layer, and the functional layer is used to achieve energy band matching, or Improve mechanical and electrical stability.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述基底与所述光敏层之间设计有第一功能层,所述第一功能层为滤光层、减反膜和钝化层中的至少一种;和/或According to the transistor-type photodetector of at least one embodiment of the present disclosure, a first functional layer is designed between the substrate and the photosensitive layer, and the first functional layer is a filter layer, an antireflection film and a passivation layer at least one of; and/or
所述光敏层与所述介质层之间设计有第二功能层,所述第二功能层用于调节所述晶体管型光电探测器的阈值电压。A second functional layer is designed between the photosensitive layer and the dielectric layer, and the second functional layer is used to adjust the threshold voltage of the transistor-type photodetector.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述介质层为由高介电常数材料制成的单层介质层或者由不同高介电常数材料制成的两层以上介质层。According to the transistor-type photodetector of at least one embodiment of the present disclosure, the dielectric layer is a single-layer dielectric layer made of a high dielectric constant material or two or more dielectric layers made of different high dielectric constant materials.
根据本公开的另一方面,一种晶体管型光电探测器,包括:According to another aspect of the present disclosure, a transistor-type photodetector includes:
第一电极;the first electrode;
第二电极,所述第二电极与所述第一电极间隔开;a second electrode spaced apart from the first electrode;
碳纳米管沟道层,所述碳纳米管沟道层至少设置在所述第一电极与所述第二电极之间;a carbon nanotube channel layer, the carbon nanotube channel layer is at least disposed between the first electrode and the second electrode;
光敏层,所述光敏层设计为p-i-n异质结、p-n反型异质结、n-n同型异质结、p-p同型异质结、n-p-n双异质结、p-n-p双异质结和肖特基结中的一种,所述光敏层的材料由需要探测的波段所决定;以及Photosensitive layer, the photosensitive layer is designed in p-i-n heterojunction, p-n inversion heterojunction, n-n homoheterojunction, p-p homoheterojunction, n-p-n double heterojunction, p-n-p double heterojunction and Schottky junction One, the material of the photosensitive layer is determined by the wavelength band to be detected; and
介质层,所述介质层设置所述碳纳米管沟道层与所述光敏层之间。A dielectric layer is provided between the carbon nanotube channel layer and the photosensitive layer.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述介质层用于将所述光敏层的内建电场的电场信号变化以电容耦合方式作用至所述碳纳米管沟道层。According to the transistor-type photodetector of at least one embodiment of the present disclosure, the dielectric layer is configured to act on the carbon nanotube channel layer by capacitively coupling the electric field signal change of the built-in electric field of the photosensitive layer.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述介质层为高介电常数介质层。According to the transistor-type photodetector of at least one embodiment of the present disclosure, the dielectric layer is a high dielectric constant dielectric layer.
根据本公开的至少一个实施方式的晶体管型光电探测器,还包括:栅极及栅绝缘层,所述栅绝缘层配置在所述碳纳米管沟道层与所述栅极之间。The transistor-type photodetector according to at least one embodiment of the present disclosure further includes a gate electrode and a gate insulating layer, the gate insulating layer being disposed between the carbon nanotube channel layer and the gate electrode.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述晶体管型光电探测器配置为全局底栅结构,所述全局底栅结构中的基底为掺杂的基底并且作为所述栅极;或者A transistor-type photodetector according to at least one embodiment of the present disclosure, the transistor-type photodetector being configured as a global bottom gate structure in which a substrate is a doped substrate and serves as the gate; or
所述晶体管型光电探测器配置为局部底栅结构,其中所述局部底栅结构包括基底,所述栅极形成于该基底中。The transistor-type photodetector is configured as a partial bottom gate structure, wherein the partial bottom gate structure includes a substrate in which the gate is formed.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述晶体管型光电探测器配置为顶栅结构,在所述顶栅结构包括基底,所述基底为透明基底且设置在所述光敏层之下,所述栅绝缘层设置在所述碳纳米管沟道层之上。A transistor-type photodetector according to at least one embodiment of the present disclosure, the transistor-type photodetector is configured as a top gate structure, the top gate structure includes a substrate, the substrate is a transparent substrate and is disposed on the photosensitive layer Below, the gate insulating layer is disposed on the carbon nanotube channel layer.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述光敏层的外侧设计有功能层,所述功能层为滤光层、减反膜和封装层中的至少一种。According to the transistor-type photodetector of at least one embodiment of the present disclosure, a functional layer is designed on the outer side of the photosensitive layer, and the functional layer is at least one of a filter layer, an antireflection film, and an encapsulation layer.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述光敏层的结结构之间设计有功能层,所述功能层用于实现能带匹配、或提高机械和电学稳定性。According to the transistor-type photodetector of at least one embodiment of the present disclosure, a functional layer is designed between the junction structures of the photosensitive layer, and the functional layer is used to achieve energy band matching or improve mechanical and electrical stability.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述基底与所述光敏层之间设计有第一功能层,所述第一功能层为滤光层、减反膜和钝化层中的至少一种;和/或According to the transistor-type photodetector of at least one embodiment of the present disclosure, a first functional layer is designed between the substrate and the photosensitive layer, and the first functional layer is a filter layer, an antireflection film and a passivation layer at least one of; and/or
所述光敏层与所述介质层之间设计有第二功能层,所述第二功能层用于调节所述晶体管型光电探测器的阈值电压。A second functional layer is designed between the photosensitive layer and the dielectric layer, and the second functional layer is used to adjust the threshold voltage of the transistor-type photodetector.
根据本公开的至少一个实施方式的晶体管型光电探测器,所述介质层为由高介电常数材料制成的单层介质层或者由不同高介电常数材料制成的两层以上介质层。According to the transistor-type photodetector of at least one embodiment of the present disclosure, the dielectric layer is a single-layer dielectric layer made of a high dielectric constant material or two or more dielectric layers made of different high dielectric constant materials.
根据本公开的又一方面,一种晶体管型光电探测器的制备方法,包括:According to yet another aspect of the present disclosure, a method for fabricating a transistor-type photodetector includes:
在掺杂的基底之上制备栅绝缘层,其中所述基座作为栅极;forming a gate insulating layer over the doped substrate, wherein the pedestal serves as a gate;
在所述栅绝缘层之上制备沟道层;preparing a channel layer on the gate insulating layer;
制备第一电极及第二电极;preparing a first electrode and a second electrode;
在所述沟道层之上制备高介电常数材料以形成介质层;以及preparing a high dielectric constant material over the channel layer to form a dielectric layer; and
在所述介质层之上制备光敏层。A photosensitive layer is prepared on the dielectric layer.
根据本公开的又一方面,一种晶体管型光电探测器的制备方法,包括:According to yet another aspect of the present disclosure, a method for fabricating a transistor-type photodetector includes:
在基底中制备栅极;preparing the gate in the substrate;
在所述基底及栅极之之上制备之上栅绝缘层;preparing an upper gate insulating layer over the substrate and the gate;
在所述栅绝缘层制备沟道层;preparing a channel layer on the gate insulating layer;
制备第一电极及第二电极;preparing a first electrode and a second electrode;
在所述沟道层之上制备高介电常数材料以形成介质层;以及preparing a high dielectric constant material over the channel layer to form a dielectric layer; and
在所述介质层之上制备光敏层。A photosensitive layer is prepared on the dielectric layer.
根据本公开的又一方面,一种晶体管型光电探测器的制备方法,包括:According to yet another aspect of the present disclosure, a method for fabricating a transistor-type photodetector includes:
在透明的基底之上制备光敏层;Prepare a photosensitive layer on a transparent substrate;
在所述光敏层之上制备高介电常数材料以形成介质层;preparing a high dielectric constant material on the photosensitive layer to form a dielectric layer;
在所述介质层之上制备沟道层;preparing a channel layer on the dielectric layer;
制备第一电极及第二电极;preparing a first electrode and a second electrode;
在所述沟道层至少制备栅绝缘层;以及Prepare at least a gate insulating layer on the channel layer; and
在所述栅绝缘之上制备栅极。A gate is fabricated over the gate insulation.
根据本公开的至少一个实施方式的制备方法,所述光敏层为p-i-n异质结结构,并且所述光敏层的材料由需要探测的波段所决定。According to the preparation method of at least one embodiment of the present disclosure, the photosensitive layer is a p-i-n heterojunction structure, and the material of the photosensitive layer is determined by the wavelength band to be detected.
根据本公开的至少一个实施方式的制备方法,所述沟道层为碳纳米管沟道层。According to the preparation method of at least one embodiment of the present disclosure, the channel layer is a carbon nanotube channel layer.
附图说明Description of drawings
附图示出了本公开的示例性实施方式,并与其说明一起用于解释本公开的原理,其中包括了这些附图以提供对本公开的进一步理解,并且附图包括在本说明书中并构成本说明书的一部分。The accompanying drawings illustrate exemplary embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure, are included to provide a further understanding of the disclosure, and are incorporated in and constitute the present specification part of the manual.
图1是根据本公开实施方式的光电探测器的结构示意图。FIG. 1 is a schematic structural diagram of a photodetector according to an embodiment of the present disclosure.
图2是根据本公开实施方式的光电探测器的结构示意图。FIG. 2 is a schematic structural diagram of a photodetector according to an embodiment of the present disclosure.
图3是根据本公开实施方式的光电探测器的结构示意图。FIG. 3 is a schematic structural diagram of a photodetector according to an embodiment of the present disclosure.
图4是根据本公开实施方式的光电探测器的结构示意图。FIG. 4 is a schematic structural diagram of a photodetector according to an embodiment of the present disclosure.
图5是根据本公开实施方式的光电探测器的结构示意图。FIG. 5 is a schematic structural diagram of a photodetector according to an embodiment of the present disclosure.
图6是根据本公开实施方式的光电探测器的结构示意图。FIG. 6 is a schematic structural diagram of a photodetector according to an embodiment of the present disclosure.
图7是根据本公开实施方式的制备方法的流程图。FIG. 7 is a flowchart of a preparation method according to an embodiment of the present disclosure.
图8是根据本公开实施方式的制备方法的流程图。FIG. 8 is a flowchart of a manufacturing method according to an embodiment of the present disclosure.
图9是根据本公开实施方式的制备方法的流程图。FIG. 9 is a flowchart of a preparation method according to an embodiment of the present disclosure.
图10是根据本公开实施方式的制备方法的流程图。FIG. 10 is a flowchart of a manufacturing method according to an embodiment of the present disclosure.
图11是根据本公开实施方式的光电探测器的结构示意图。11 is a schematic structural diagram of a photodetector according to an embodiment of the present disclosure.
图12至图16是根据本公开实施方式的光电探测器的性能指标示意图。12 to 16 are schematic diagrams of performance indicators of photodetectors according to embodiments of the present disclosure.
具体实施方式Detailed ways
下面结合附图和实施方式对本公开作进一步的详细说明。可以理解的是,此处所描述的具体实施方式仅用于解释相关内容,而非对本公开的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与本公开相关的部分。The present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the related content, but not to limit the present disclosure. In addition, it should be noted that, for the convenience of description, only the parts related to the present disclosure are shown in the drawings.
需要说明的是,在不冲突的情况下,本公开中的实施方式及实施方式中的特征可以相互组合。下面将参考附图并结合实施方式来详细说明本公开的技术方案。It should be noted that the embodiments of the present disclosure and the features of the embodiments may be combined with each other unless there is conflict. The technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.
除非另有说明,否则示出的示例性实施方式/实施例将被理解为提供可以在实践中实施本公开的技术构思的一些方式的各种细节的示例性特征。因此,除非另有说明,否则在不脱离本公开的技术构思的情况下,各种实施方式/实施例的特征可以另外地组合、分离、互换和/或重新布置。Unless otherwise stated, the illustrated exemplary embodiments/embodiments are to be understood as exemplary features providing various details of some ways in which the technical concept of the present disclosure may be implemented in practice. Therefore, unless otherwise stated, the features of various embodiments/embodiments may be additionally combined, separated, interchanged and/or rearranged without departing from the technical concept of the present disclosure.
在附图中使用交叉影线和/或阴影通常用于使相邻部件之间的边界变得清晰。如此,除非说明,否则交叉影线或阴影的存在与否均不传达或表示对部件的具体材料、材料性质、尺寸、比例、示出的部件之间的共性和/或部件的任何其它特性、属性、性质等的任何偏好或者要求。此外,在附图中,为了清楚和/或描述性的目的,可以夸大部件的尺寸和相对尺寸。当可以不同地实施示例性实施例时,可以以不同于所描述的顺序来执行具体的工艺顺序。例如,可以基本同时执行或者以与所描述的顺序相反的顺序执行两个连续描述的工艺。此外,同样的附图标记表示同样的部件。The use of cross-hatching and/or hatching in the drawings is generally used to clarify boundaries between adjacent components. As such, unless stated, the presence or absence of cross-hatching or shading does not convey or represent any particular material, material properties, dimensions, proportions, commonalities between the illustrated components and/or any other characteristics of the components, any preferences or requirements for attributes, properties, etc. Furthermore, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. When example embodiments may be implemented differently, the specific process sequence may be performed in a different order than described. For example, two consecutively described processes may be performed substantially concurrently or in the reverse order of that described. In addition, the same reference numerals denote the same components.
当一个部件被称作“在”另一部件“上”或“之上”、“连接到”或“结合到”另一部件时,该部件可以直接在所述另一部件上、直接连接到或直接结合到所述另一部件,或者可以存在中间部件。然而,当部件被称作“直接在”另一部件“上”、“直接连接到”或“直接结合到”另一部件时,不存在中间部件。为此,术语“连接”可以指物理连接、电气连接等,并且具有或不具有中间部件。When an element is referred to as being "on" or "over", "connected to" or "coupled to" another element, the element can be directly on, directly connected to, the other element Either directly coupled to the other component, or intermediate components may be present. However, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. To this end, the term "connected" may refer to a physical connection, electrical connection, etc., with or without intervening components.
为方便起见,在以下描述中,根据本发明的实施例的各种器件几何形状在附图中示出的取向上关于器件进行描述。在描述中使用诸如“之上”、“上方”、“横向”、“垂直”等术语的情况下,不应将这些解释为意味着此类实施例限于在附图中示出的特定方向。应当容易理解,无论器件的物理方向或包括有该器件的装置的物理方向如何,本文描述的器件都将能够正确运行,因此应当相应地解释以下描述。另外,根据本发明的实施例的晶体管包括半导体区域,该半导体区域可包括半导体、半金属或简并掺杂的半导体、或其组合。因此,应相应地解释本文中对“半导体区域”的引用。For convenience, in the following description, various device geometries according to embodiments of the present invention are described with respect to the devices in the orientations shown in the figures. Where terms such as "above," "over," "lateral," "vertical," etc. are used in the description, these should not be construed to imply that such embodiments are limited to the particular orientation shown in the figures. It should be readily understood that the devices described herein will function correctly regardless of the physical orientation of the device or the device in which it is incorporated, and the following description should be interpreted accordingly. Additionally, transistors according to embodiments of the present invention include semiconductor regions, which may include semiconductors, semi-metals, or degenerately doped semiconductors, or combinations thereof. Accordingly, references herein to "semiconductor regions" should be interpreted accordingly.
这里使用的术语是为了描述具体实施例的目的,而不意图是限制性的。如这里所使用的,除非上下文另外清楚地指出,否则单数形式“一个(种、者)”和“所述(该)”也意图包括复数形式。此外,当在本说明书中使用术语“包含”和/或“包括”以及它们的变型时,说明存在所陈述的特征、整体、步骤、操作、部件、组件和/或它们的组,但不排除存在或附加一个或更多个其它特征、整体、步骤、操作、部件、组件和/或它们的组。还要注意的是,如这里使用的,术语“基本上”、“大约”和其它类似的术语被用作近似术语而不用作程度术语,如此,它们被用来解释本领域普通技术人员将认识到的测量值、计算值和/或提供的值的固有偏差。The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a" and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Furthermore, when the terms "comprising" and/or "comprising" and their variants are used in this specification, it is indicated that the stated features, integers, steps, operations, parts, components and/or groups thereof are present, but not excluded One or more other features, integers, steps, operations, parts, components and/or groups thereof are present or additional. Note also that, as used herein, the terms "substantially," "approximately," and other similar terms are used as terms of approximation and not as terms of degree, as they are used to explain what one of ordinary skill in the art would recognize Inherent deviations from measured, calculated and/or provided values.
根据本公开的一个实施方式,提供了一种晶体管型光电探测器,其中该晶体管型光电探测器可以是红外探测器、可见光探测器、紫外探测器、太赫兹探测器等等。According to one embodiment of the present disclosure, a transistor-type photodetector is provided, wherein the transistor-type photodetector may be an infrared detector, a visible light detector, an ultraviolet detector, a terahertz detector, and the like.
图1示出了根据本公开的一个实施例的晶体管型光电探测器的示意图。FIG. 1 shows a schematic diagram of a transistor-type photodetector according to one embodiment of the present disclosure.
如图1所示,光电探测器10可以包括第一电极110和第二电极120。第一电极110和第二电极120可以彼此间隔开,其中第一电极110可以为源极或漏极,而第二电极120可以为漏极或源极。在第一电极110与第二电极120之间可以设置有沟道层130。As shown in FIG. 1 , the
第一电极110和第二电极120可以由任何合适的材料或材料组合形成。可用于第一电极110和第二电极120的材料的示例包括但不限于:金属、导电或半导体金属氧化物、导电或半导体聚合物、掺杂半导体、石墨烯、以及二维(2D)半导体等。作为一个优选示例,第一电极110和第二电极120的材料可以为Ti(钛)、Pd(钯)或Au(金)等金属材料中的一种或多种。The
光电探测器10可以包括沟道层130。沟道层130至少设置在第一电极110和第二电极120之间的区域。可用于沟道层130的材料的示例包括但不限于:晶体或非晶硅、半导体金属氧化物、过渡金属硫族化合物、石墨烯、碳纳米管、半导体纳米线、有机半导体等二维材料。The
在本公开中,沟道层130的材料优选为碳纳米管。例如可以在晶圆上沉积网络状或者顺排的高纯度碳纳米管薄膜,此外,也可以根据实际的需要对碳纳米管的密度来进行控制。In the present disclosure, the material of the
此外在二维材料沉积完成后可以对沟道区域之外的二维材料进行刻蚀以避免器件间的电串扰。In addition, after the deposition of the two-dimensional material is completed, the two-dimensional material outside the channel region can be etched to avoid electrical crosstalk between devices.
光电探测器10可以包括介质层140。介质层140可以设置在沟道层130与下面描述的光敏层150之间。介质层140可以为绝缘介质。可用于介质层140的材料的示例包括但不限于:SiO2、HfO2、ZrO2、Ta2O5、Y2O3、Nb2O5、Al2O3、TiO2、CeO2、In2O3、RuO2、MgO、SrO、B2O3、SnO2、PbO、PbO2、Pb3O4、V2O3、La2O3、Pr2O3、Sb2O3、Sb2O5、CaO等中的任一种。在本公开中,介质层140可以为上述所列材料形成的单层结构。但是介质层140也可以是两层以上的结构,例如通过上述所列的不同材料所形成的多层结构。可以通过曝光、热氧化或ALD等工艺来制备介质层140。The
在本公开中,介质层140优选为高介电常数介质层。通过该介质层140的设计可以实现将光敏层150的内建电场的电场信号变化以电容耦合方式放大并作用至沟道层130。根据本公开的独特器件结构,能够以电容耦合方式实现对光信号(光电压)的有效放大,从而可以获得较高的响应度/外量子效率。在本公开的结构中,光生激子不需要完全分离,只需要产生电偶极子电势,也就是产生电势分布即可。因此可以使得本公开的光电探测器具有极快的响应速度。因此,根据本公开的器件结构,可以解决传统的Photogating型光电探测器中所存在的高响应度与速度难以兼得的弊端,也能够很好地解决光敏层材料与沟道层材料接触,光敏层材料影响沟道层材料的输送特性以及传感机制变得复杂等问题。In the present disclosure, the
光电探测器10可以包括光敏层150。光敏层150与介质层140相邻设置。光敏层150的材料由所需探测的波段所决定。光敏层150可以设计成p-i-n异质结、p-n反型异质结、n-n同型异质结、p-p同型异质结、n-p-n双异质结、p-n-p双异质结、肖特基结等结结构。在本公开中,优选地光敏层150可以设计成p-i-n异质结,在该p-i-n异质结的结结构中,p区和n区可以设置地较薄,并且i区可以设置地较厚,也就是说i区的设置厚度大于p区和n区的设置厚度。通过这种设置可以有效地抑制多数载流子的隧穿效应,且灵敏度高,结电容小且电路常数小,耗尽层宽,扩散和渡越时间短,响应速度快。The
在本公开中,可以通过以下方式来形成光敏层150。作为一个示例,可以通过热蒸发、磁控溅射、电子束蒸镀、原子层沉积、化学气相沉积等方法制备的非晶或多晶薄膜,例如ZnO、TiO2、Si、PbS、PbSe等薄膜来形成光敏层150。作为另一示例,可以通过多晶或单晶的胶体量子点薄膜来形成光敏层150,例如包括Pb系、Hg系、Cd系、Si、氧化物、钙钛矿等量子点体系,如PbS、PbSe、HgTe、Si、CdTe、CdS、ZnO及其核壳结构的量子点。作为再一示例,可以通过单晶或多晶的纳米线、纳米片等组成的薄膜来形成光敏层150,如GaAs、Te等纳米线以及ZnO、HgTe等纳米片。In the present disclosure, the
作为示例,当晶体管型光电探测器为中波红外探测器的情况下,光敏层150的p-i-n结可以为Ag2Te-HgTe-Bi2Se3。当晶体管型光电探测器为短波红外探测器的情况下,光敏层150的p-i-n结可以为p-i-nGeSn、p-Si/i-Ge/n-Ge、PbS-EDT量子点/i-卤素骨架的PbS量子点/n-ZnO或n-TiO2。当晶体管型光电探测器为近红外波探测器的情况下,光敏层150的p-i-n结可以为p-NiOx/i-卤素骨架的PbS量子点/n-ZnO,当晶体管型光电探测器为可见光探测器的情况下,光敏层150的p-i-n结可以为p-i-n硅异质结。当晶体管型光电探测器为紫外光探测器的情况下,光敏层150的p-i-n结可以为ZnO薄膜、p-Si/i-ZnO/n-ZnO的p-i-n异质结。As an example, when the transistor-type photodetector is a mid-wave infrared detector, the pin junction of the
此外,对于p-i-n结结构,可以在p-i或i-n之间设计功能层,以便更好地实现能带匹配、或提高机械和/或电学稳定性等。例如,可以设计p-NiOx/i-PbS量子点/C60/n-ZnO结构作为光敏层,进行近红外探测,其中C60作为功能层;设计p-Si/SiOx/i-ZnO/n-ZnO作为光敏层,进行紫外光电探测,其中SiOx作为功能层。In addition, for the p-i-n junction structure, functional layers can be designed between p-i or i-n to achieve better band matching, or improve mechanical and/or electrical stability, etc. For example, p-NiOx/i-PbS quantum dots/C60/n-ZnO structure can be designed as a photosensitive layer for near-infrared detection, in which C60 is used as a functional layer; p-Si/SiOx/i-ZnO/n-ZnO can be designed as a The photosensitive layer is used for ultraviolet photodetection, and SiOx is used as the functional layer.
在本公开的结构中,内建电场的作用范围可以形成在整个结结构的区域,因此可以很好地解决BFBD器件的内建电场作用范围有限的问题,在BFBD器件中,内建电场的作用范围仅在源漏接触附近约50nm的区域,因此BFBD器件很难获得较高的信噪比。In the structure of the present disclosure, the action range of the built-in electric field can be formed in the region of the entire junction structure, so the problem of the limited action range of the built-in electric field in the BFBD device can be well solved. In the BFBD device, the action of the built-in electric field The range is only about 50 nm near the source-drain contact, so it is difficult to obtain a high signal-to-noise ratio for BFBD devices.
光电探测器10可以包括栅绝缘层160。栅绝缘层160可以为任意的绝缘介质,例如可以为SiO2。在图1中示出了全局底栅结构。在该全局底栅结构中,掺杂的基底170可以作为栅极,并且栅绝缘层160可以设置在基底170和沟道层130之间。The
图2示出了根据本公开的另一实施例,该实施例与参照图1所描述的内容的区别在于,可以在光敏层150的外侧设置功能层180,其中该功能层180可以为一层结构也可以为多层结构,例如可以为滤光层、减反膜、封装层等的至少一种。对于与图1的相关描述相同的内容,在此不再赘述。FIG. 2 shows another embodiment according to the present disclosure. The difference between this embodiment and the content described with reference to FIG. 1 is that a
图3示出了根据本公开的另一实施例的晶体管型光电探测器20的示意图。在该实施例中,光电探测器20可以包括第一电极210、第二电极220、沟道层230、介质层240、光敏层250、栅绝缘层260、基底270和栅极280。FIG. 3 shows a schematic diagram of a transistor-
其中,第一电极210、第二电极220、沟道层230、介质层240、光敏层250和栅绝缘层260的具体描述可以参照第一电极110、第二电极120、沟道层130、介质层140、光敏层150和栅绝缘层160的详细描述。这里为了简洁起见,不再赘述。The specific description of the
图3的实施例与图1的实施例的主要区别在于,在图3中采用了局部底栅结构,而图1采用的是全局底栅结构。The main difference between the embodiment of FIG. 3 and the embodiment of FIG. 1 is that a local bottom gate structure is used in FIG. 3 , while a global bottom gate structure is used in FIG. 1 .
在图3的实施例中,栅极280可以由Ti、Al、Sc、Ni、Pd、Au、Pt等金属材料制成,也可以为金属材料的叠层结构。在本公开中,可以为了实现调控晶体管的阈值来选择栅极金属。可以通过调控施加在底栅金属的电压,可以将晶体管偏置在最佳工作点,实现最佳信噪比。In the embodiment of FIG. 3 , the
在本公开中,基底材料可以为硅、玻璃、石英、ITO等;或者柔性的PI、PET等柔性基底。In the present disclosure, the substrate material may be silicon, glass, quartz, ITO, etc.; or flexible substrates such as flexible PI, PET, and the like.
在图3的实施例中,也可以在光敏层250上设置功能层(如图2的描述),其中该功能层可以为一层结构也可以为多层结构,例如可以为滤光层、减反膜、封装层等的至少一种。In the embodiment of FIG. 3, a functional layer (as described in FIG. 2) can also be provided on the
图4示出了根据本公开的又一实施例的晶体管型光电探测器30的示意图。图4所示的晶体管型光电探测器30可以为顶栅结构的背入射的光电探测器。在该实施例的光电探测器中,可以包括第一电极310、第二电极320、沟道层330、介质层340、光敏层350、栅绝缘层360、基底370和栅极380。其中这些部分的具体描述可以引用上面描述的内容,在此不再赘述。FIG. 4 shows a schematic diagram of a transistor-
在本公开中,光敏层350可以设置在基底370之上。基底370可以设置成透明形式(例如由玻璃、石英、ITO等制成),这样光线可以从如图4所示的基底370的下部进入并且照射至光敏层350。在光敏层350之上可以设置介质层340。沟道层330形成在第一电极310和第二电极320之间,并且位于栅绝缘层360与沟道层330之间。In the present disclosure, the
根据本公开的进一步实施例,如图5所示,晶体管型光电探测器30还可以包括第一功能层391,其中第一功能层391可以为滤光层、减反膜、钝化层等中的至少一种。其中该第一功能层391可以设置在光敏层350与透明的基底370之间。此外,晶体管型光电探测器30还可以包括第二功能层392。该第二功能层392可以设置在光敏层350和介质层340之间,该第二功能层392可以用于调整晶体管型光电探测器的阈值电压,例如该第二功能层392可以为金属层,此外可以为增反膜等。According to further embodiments of the present disclosure, as shown in FIG. 5 , the transistor-
根据本公开的器件结构,可以通过调节晶体管光电探测器的栅压来将其沟道层偏置到最佳工作点,实现最佳信噪比。例如可以采用如图6所示进行电路连接之后,可以调控施加栅压VGS,以使得沟道层偏置至最佳工作点,从而实现最佳信噪比。According to the device structure of the present disclosure, the channel layer of the transistor photodetector can be biased to the optimum operating point by adjusting the gate voltage of the transistor photodetector to achieve the optimum signal-to-noise ratio. For example, after the circuit connection as shown in FIG. 6 can be used, the applied gate voltage V GS can be regulated so that the channel layer is biased to the optimum operating point, thereby achieving the optimum signal-to-noise ratio.
根据本公开的技术方案,可以有效地解决BFBD器件的内建电场的作用范围有限很难得获得较高的信噪比的问题,也可以很好解决Photogating型器件所存在响应度/外量子效率和速度的矛盾问题。According to the technical solution of the present disclosure, the problem that the action range of the built-in electric field of the BFBD device is limited and it is difficult to obtain a high signal-to-noise ratio can be effectively solved, and the responsivity/external quantum efficiency and The paradox of speed.
尤其是对于沟道层为碳纳米管材料的情况下,本公开的技术方案可以同时获得较快的响应速度、较高的响应度/外量子效率和较大的信噪比。具体而言:在晶圆片上沉积网络状或阵列碳纳米管,实现高质量底栅晶体管的批量制作,由于碳纳米管具有优异的电荷输运性能,可以实现载流子的快速传输。采用ALD、热氧化等方式在碳纳米管上沉积高k介质作为介质层,这一介质层的设计能够实现将电场信号变化以电容耦合的方式放大并作用到碳纳米管;在介质层上采用旋涂、溅射等方式沉积量子薄膜等作为光敏层,具有高外量子效率,能够实现有效光吸收;在光敏层中设计p-i-n异质结、p-n反型异质结、n-n同型异质结、p-p同型异质结、n-p-n双异质结、p-n-p双异质结、肖特基结,实现光生载流子的有效快速分离,形成光电压;通过调控施加在碳纳米管底栅晶体管上的栅压,将碳纳米管偏置在最佳工作点,实现最佳信噪比。Especially in the case where the channel layer is made of carbon nanotube material, the technical solution of the present disclosure can simultaneously obtain faster response speed, higher responsivity/external quantum efficiency and larger signal-to-noise ratio. Specifically, network or array carbon nanotubes are deposited on wafers to achieve mass production of high-quality bottom-gate transistors. Due to the excellent charge transport properties of carbon nanotubes, rapid carrier transport can be achieved. ALD, thermal oxidation, etc. are used to deposit a high-k dielectric on the carbon nanotubes as a dielectric layer. The design of this dielectric layer can amplify the electric field signal change in a capacitive coupling way and act on the carbon nanotubes; Quantum thin films deposited by spin coating, sputtering, etc. are used as photosensitive layers, which have high external quantum efficiency and can achieve effective light absorption; p-p homo-heterojunction, n-p-n double heterojunction, p-n-p double heterojunction, Schottky junction, to achieve effective and rapid separation of photogenerated carriers to form photovoltage; by regulating the gate applied on the carbon nanotube bottom gate transistor pressure to bias the carbon nanotubes at the optimal working point to achieve the best signal-to-noise ratio.
根据本公开的再一实施例,提供了一种晶体管型光电探测器的制备方法。图7示出了根据本公开的一个实施例的制备方法M700的流程图,并且可以包括以下内容。According to yet another embodiment of the present disclosure, a method for fabricating a transistor-type photodetector is provided. FIG. 7 shows a flowchart of a preparation method M700 according to an embodiment of the present disclosure, and may include the following contents.
在步骤S702中,制备光敏层或者沟道层;在步骤S704中,制备介质层,在步骤S706中,制备沟道层或光敏层。如果在步骤S702中制备光敏层则在步骤S706中制备沟道层,如果在步骤S702中制备沟道层则在步骤S706中制备光敏层。其中光敏层为p-i-n异质结结构,并且光敏层的材料由需要探测的波段所决定。或者,沟道层为碳纳米管沟道层。In step S702, a photosensitive layer or a channel layer is prepared; in step S704, a dielectric layer is prepared, and in step S706, a channel layer or a photosensitive layer is prepared. If the photosensitive layer is prepared in step S702, the channel layer is prepared in step S706, and if the channel layer is prepared in step S702, the photosensitive layer is prepared in step S706. The photosensitive layer is a p-i-n heterojunction structure, and the material of the photosensitive layer is determined by the wavelength band to be detected. Alternatively, the channel layer is a carbon nanotube channel layer.
根据本公开的具体实施例,提供了下面的晶体管型光电探测器的制备方法,其中在下面的描述中,以碳纳米管作为沟道层来进行描述。According to specific embodiments of the present disclosure, the following method for fabricating a transistor-type photodetector is provided, wherein in the following description, carbon nanotubes are used as the channel layer for description.
图8示出了一种具体制备方法M800的流程图。方法M800可以对应于如图1的实施例的全局底栅结构,该方法的具体内容可以参照关于图1的描述。FIG. 8 shows a flow chart of a specific preparation method M800. The method M800 may correspond to the global bottom gate structure in the embodiment of FIG. 1 , and the specific content of the method may refer to the description related to FIG. 1 .
在步骤S802中,可以在晶圆上沉积栅绝缘层。栅绝缘层可以为任意的绝缘介质,该晶圆可以为掺杂的基底并且可以作为晶体管型光电探测器的栅极来使用。In step S802, a gate insulating layer may be deposited on the wafer. The gate insulating layer can be any insulating medium, and the wafer can be a doped substrate and can be used as a gate of a transistor-type photodetector.
在步骤S804中,在栅绝缘层上可以沉积沟道层,例如可以沉积网络状或顺排的高纯度碳纳米管薄膜。如上面说明的,也可以采用晶体或非晶硅、半导体金属氧化物、过渡金属硫族化合物、石墨烯、半导体纳米线、有机半导体等其他二维材料来进行沉积形成沟道层。在本公开中,可以对沉积的碳纳米管的密度进行相应的控制。此外,在碳纳米管沉积完成之后,可以进行高温退火,并且采用例如氧化钇清洗技术来去除碳纳米管表面的有机聚合物。In step S804, a channel layer may be deposited on the gate insulating layer, for example, a network-like or aligned high-purity carbon nanotube thin film may be deposited. As explained above, other two-dimensional materials such as crystalline or amorphous silicon, semiconductor metal oxides, transition metal chalcogenides, graphene, semiconductor nanowires, organic semiconductors, etc. can also be used for deposition to form the channel layer. In the present disclosure, the density of the deposited carbon nanotubes can be controlled accordingly. In addition, after the carbon nanotube deposition is completed, high temperature annealing may be performed, and a cleaning technique such as yttrium oxide may be used to remove organic polymers on the surface of the carbon nanotubes.
在步骤S806中,可以制备第一电极和第二电极。其中具体地,可以采用曝光、电子束镀膜等微加工工艺来沉积金属材料从而制备第一电极和第二电极。第一电极和第二电极的材料可以为Ti、Pd或Au等金属材料中的一种或多种。In step S806, the first electrode and the second electrode may be prepared. Specifically, the first electrode and the second electrode can be prepared by depositing a metal material by using a micro-machining process such as exposure and electron beam coating. The material of the first electrode and the second electrode may be one or more of metal materials such as Ti, Pd or Au.
在步骤S808中,可以诸如曝光、干法刻蚀等工艺对碳纳米管薄膜进行图形化,并且刻蚀沟道区域之外的碳纳米管,从而避免器件之间的电串扰。In step S808, the carbon nanotube film may be patterned by processes such as exposure, dry etching, etc., and the carbon nanotubes outside the channel region are etched, so as to avoid electrical crosstalk between devices.
在步骤S810中,可以在碳纳米管薄膜上形成介质层,其中介质层的材料可以如上所述。例如可以采用电子束蒸镀金属钇,然后进行热氧化,从而在碳纳米管薄膜上形成氧化钇来作为高介电常数介质层。此外,也可以形成多层结构的氧化物来形成高介电常数介质层。In step S810, a dielectric layer may be formed on the carbon nanotube thin film, wherein the material of the dielectric layer may be as described above. For example, metal yttrium can be deposited by electron beam evaporation and then thermally oxidized to form yttrium oxide on the carbon nanotube film as a high dielectric constant dielectric layer. In addition, an oxide of a multilayer structure can also be formed to form a high dielectric constant dielectric layer.
在步骤S812中,可以在介质层之上制备光敏层。光敏层可以制备成二层至三层结构,光敏层的材料根据所需探测波段所确定。并且光敏层制备成可以促进光生载流子的有效分离。光敏层可以制备成p-i-n异质结、p-n反型异质结、n-n同型异质结、p-p同型异质结、n-p-n双异质结、p-n-p双异质结、肖特基结等结结构。In step S812, a photosensitive layer may be prepared on the dielectric layer. The photosensitive layer can be prepared into a two-layer to three-layer structure, and the material of the photosensitive layer is determined according to the required detection band. And the photoactive layer is prepared to promote the effective separation of photogenerated carriers. The photosensitive layer can be prepared into p-i-n heterojunction, p-n inverse heterojunction, n-n homoheterojunction, p-p homoheterojunction, n-p-n double heterojunction, p-n-p double heterojunction, Schottky junction and other junction structures.
在本公开中,光敏层优选为p-i-n异质结。例如在进行中波红外探测的情况下,光敏层的p-i-n结可以为Ag2Te-HgTe-Bi2Se3。当晶体管型光电探测器为短波红外探测器的情况下,光敏层的p-i-n结可以为p-i-n GeSn、p-Si/i-Ge/n-Ge、p-PbS-EDT量子点/i-卤素骨架的PbS量子点/n-ZnO或n-TiO2。当晶体管型光电探测器为近红外波探测器的情况下,光敏层的p-i-n结可以为p-NiOx/i-卤素骨架的PbS量子点/n-ZnO,当晶体管型光电探测器为可见光探测器的情况下,光敏层的p-i-n结可以为p-i-n硅异质结。当晶体管型光电探测器为紫外光探测器的情况下,光敏层的p-i-n结可以为ZnO薄膜、p-Si/i-ZnO/n-ZnO的p-i-n异质结。In the present disclosure, the photoactive layer is preferably a pin heterojunction. For example, in the case of medium-wave infrared detection, the pin junction of the photosensitive layer can be Ag 2 Te-HgTe-Bi 2 Se 3 . When the transistor-type photodetector is a short-wave infrared detector, the pin junction of the photosensitive layer can be pin GeSn, p-Si/i-Ge/n-Ge, p-PbS-EDT quantum dots/i-halogen skeleton PbS quantum dots/n-ZnO or n- TiO2 . When the transistor-type photodetector is a near-infrared wave detector, the pin junction of the photosensitive layer can be p-NiOx/i-halogen skeleton PbS quantum dots/n-ZnO, and when the transistor-type photodetector is a visible light detector In the case of , the pin junction of the photosensitive layer may be a pin silicon heterojunction. When the transistor-type photodetector is an ultraviolet photodetector, the pin junction of the photosensitive layer can be a ZnO thin film or a pin heterojunction of p-Si/i-ZnO/n-ZnO.
在该实施例中,还可以包括在光敏层上制备一层或多层功能层,例如可以为滤光层、减反膜、封装层等的至少一种。进一步地还可以包括进行如图6所示的电路连接,进行相应的光电性能测试,通过调控底栅工作电压获得最佳信噪比。In this embodiment, one or more functional layers may also be prepared on the photosensitive layer, such as at least one of a filter layer, an antireflection film, an encapsulation layer, and the like. Further, the circuit connection as shown in FIG. 6 may be performed, corresponding photoelectric performance tests are performed, and the optimal signal-to-noise ratio can be obtained by adjusting the operating voltage of the bottom gate.
图9示出了一种具体制备方法M900的流程图。方法M900可以对应于如图3的实施例的局部底栅结构,该方法的具体内容可以参照关于图3的描述。FIG. 9 shows a flow chart of a specific preparation method M900. The method M900 may correspond to the local bottom gate structure of the embodiment of FIG. 3 , and the specific content of the method may refer to the description related to FIG. 3 .
在步骤S902中,在晶圆上加工栅极结构,并且沉积栅极金属来制备栅极。In step S902, the gate structure is processed on the wafer, and gate metal is deposited to prepare the gate.
在步骤S904中,可以在晶圆及栅极结构之上沉积栅绝缘层。栅绝缘层可以为任意的绝缘介质。In step S904, a gate insulating layer may be deposited over the wafer and the gate structure. The gate insulating layer can be any insulating medium.
在步骤S906中,在栅绝缘层上可以沉积沟道层,例如可以沉积网络状或顺排的高纯度碳纳米管薄膜。如上面说明的,也可以采用晶体或非晶硅、半导体金属氧化物、过渡金属硫族化合物、石墨烯、半导体纳米线、有机半导体等其他二维材料来进行沉积形成沟道层。在本公开中,可以对沉积的碳纳米管的密度进行相应的控制。此外,在碳纳米管沉积完成之后,可以进行高温退火,并且采用例如氧化钇清洗技术来去除碳纳米管表面的有机聚合物。In step S906, a channel layer may be deposited on the gate insulating layer, for example, a network-like or aligned high-purity carbon nanotube thin film may be deposited. As explained above, other two-dimensional materials such as crystalline or amorphous silicon, semiconductor metal oxides, transition metal chalcogenides, graphene, semiconductor nanowires, organic semiconductors, etc. can also be used for deposition to form the channel layer. In the present disclosure, the density of the deposited carbon nanotubes can be controlled accordingly. In addition, after the carbon nanotube deposition is completed, high temperature annealing may be performed, and a cleaning technique such as yttrium oxide may be used to remove organic polymers on the surface of the carbon nanotubes.
在步骤S908中,可以制备第一电极和第二电极。可以采用曝光、电子束镀膜等微加工工艺来沉积金属材料从而制备第一电极和第二电极。第一电极和第二电极的材料可以为Ti、Pd或Au等金属材料中的一种或多种。In step S908, a first electrode and a second electrode may be prepared. The first electrode and the second electrode can be prepared by depositing the metal material by using microfabrication processes such as exposure and electron beam coating. The material of the first electrode and the second electrode may be one or more of metal materials such as Ti, Pd or Au.
在步骤S910中,可以诸如曝光、干法刻蚀等工艺对碳纳米管薄膜进行图形化,并且刻蚀沟道区域之外的碳纳米管,从而避免器件之间的电串扰。In step S910, the carbon nanotube thin film may be patterned by processes such as exposure, dry etching, etc., and the carbon nanotubes outside the channel region are etched, so as to avoid electrical crosstalk between devices.
在步骤S912中,可以在碳纳米管薄膜上形成介质层,其中介质层的材料可以如上所述。例如可以采用电子束蒸镀金属钇,然后进行热氧化,从而在碳纳米管薄膜上形成氧化钇来作为高介电常数介质层。此外,也可以形成多层结构的氧化物来形成高介电常数介质层。In step S912, a dielectric layer may be formed on the carbon nanotube thin film, wherein the material of the dielectric layer may be as described above. For example, metal yttrium can be deposited by electron beam evaporation and then thermally oxidized to form yttrium oxide on the carbon nanotube film as a high dielectric constant dielectric layer. In addition, an oxide of a multilayer structure can also be formed to form a high dielectric constant dielectric layer.
在步骤S914中,可以在介质层之上制备光敏层。光敏层可以制备成二层至三层结构,光敏层的材料根据所需探测波段所确定。并且光敏层制备成可以促进光生载流子的有效分离。光敏层可以制备成p-i-n异质结、p-n反型异质结、n-n同型异质结、p-p同型异质结、n-p-n双异质结、p-n-p双异质结、肖特基结等结结构。In step S914, a photosensitive layer may be prepared on the dielectric layer. The photosensitive layer can be prepared into a two-layer to three-layer structure, and the material of the photosensitive layer is determined according to the desired detection band. And the photoactive layer is prepared to promote the effective separation of photogenerated carriers. The photosensitive layer can be prepared into p-i-n heterojunction, p-n inverse heterojunction, n-n homoheterojunction, p-p homoheterojunction, n-p-n double heterojunction, p-n-p double heterojunction, Schottky junction and other junction structures.
在本公开中,光敏层优选为p-i-n异质结。例如在进行中波红外探测的情况下,光敏层的p-i-n结可以为Ag2Te-HgTe-Bi2Se3。当晶体管型光电探测器为短波红外探测器的情况下,光敏层的p-i-n结可以为p-i-n GeSn、p-Si/i-Ge/n-Ge、p-PbS-EDT量子点/i-卤素骨架的PbS量子点/n-ZnO或n-TiO2。当晶体管型光电探测器为近红外波探测器的情况下,光敏层的p-i-n结可以为p-NiOx/i-卤素骨架的PbS量子点/n-ZnO,当晶体管型光电探测器为可见光探测器的情况下,光敏层的p-i-n结可以为p-i-n硅异质结。当晶体管型光电探测器为紫外光探测器的情况下,光敏层的p-i-n结可以为ZnO薄膜、p-Si/i-ZnO/n-ZnO的p-i-n异质结。In the present disclosure, the photoactive layer is preferably a pin heterojunction. For example, in the case of medium-wave infrared detection, the pin junction of the photosensitive layer can be Ag 2 Te-HgTe-Bi 2 Se 3 . When the transistor-type photodetector is a short-wave infrared detector, the pin junction of the photosensitive layer can be pin GeSn, p-Si/i-Ge/n-Ge, p-PbS-EDT quantum dots/i-halogen skeleton PbS quantum dots/n-ZnO or n- TiO2 . When the transistor-type photodetector is a near-infrared wave detector, the pin junction of the photosensitive layer can be p-NiOx/i-halogen skeleton PbS quantum dots/n-ZnO, and when the transistor-type photodetector is a visible light detector In the case of , the pin junction of the photosensitive layer may be a pin silicon heterojunction. When the transistor-type photodetector is an ultraviolet photodetector, the pin junction of the photosensitive layer can be a ZnO thin film or a pin heterojunction of p-Si/i-ZnO/n-ZnO.
在该实施例中,还可以包括在光敏层上制备一层或多层功能层,例如可以为滤光层、减反膜、封装层等的至少一种。进一步地还可以包括进行如图6所示的电路连接,进行相应的光电性能测试,通过调控底栅工作电压获得最佳信噪比。In this embodiment, one or more functional layers may also be prepared on the photosensitive layer, such as at least one of a filter layer, an antireflection film, an encapsulation layer, and the like. Further, the circuit connection as shown in FIG. 6 may be performed, corresponding photoelectric performance tests are performed, and the optimal signal-to-noise ratio can be obtained by adjusting the operating voltage of the bottom gate.
图10示出了一种具体制备方法M1000的流程图。方法M1000可以对应于如图4的实施例的全局底栅结构,该方法的具体内容可以参照关于图4的描述。FIG. 10 shows a flow chart of a specific preparation method M1000. The method M1000 may correspond to the global bottom gate structure in the embodiment of FIG. 4 , and the specific content of the method may refer to the description about FIG. 4 .
在步骤S1002中,可以在晶圆上制备光敏层。光敏层可以制备成二层至三层结构,光敏层的材料根据所需探测波段所确定。并且光敏层制备成可以促进光生载流子的有效分离。光敏层可以制备成p-i-n异质结、p-n反型异质结、n-n同型异质结、p-p同型异质结、n-p-n双异质结、p-n-p双异质结、肖特基结等结结构。在本公开中,光敏层优选为p-i-n异质结。例如在进行中波红外探测的情况下,光敏层的p-i-n结可以为Ag2Te-HgTe-Bi2Se3。当晶体管型光电探测器为短波红外探测器的情况下,光敏层的p-i-n结可以为p-i-n GeSn、p-Si/i-Ge/n-Ge、p-PbS-EDT量子点/i-卤素骨架的PbS量子点/n-ZnO或n-TiO2。当晶体管型光电探测器为近红外波探测器的情况下,光敏层的p-i-n结可以为p-NiOx/i-卤素骨架的PbS量子点/n-ZnO,当晶体管型光电探测器为可见光探测器的情况下,光敏层的p-i-n结可以为p-i-n硅异质结。当晶体管型光电探测器为紫外光探测器的情况下,光敏层的p-i-n结可以为ZnO薄膜、p-Si/i-ZnO/n-ZnO的p-i-n异质结。In step S1002, a photosensitive layer may be prepared on the wafer. The photosensitive layer can be prepared into a two-layer to three-layer structure, and the material of the photosensitive layer is determined according to the required detection band. And the photoactive layer is prepared to promote the effective separation of photogenerated carriers. The photosensitive layer can be prepared into pin heterojunction, pn inversion heterojunction, nn homoheterojunction, pp homoheterojunction, npn double heterojunction, pnp double heterojunction, Schottky junction and other junction structures. In the present disclosure, the photoactive layer is preferably a pin heterojunction. For example, in the case of medium-wave infrared detection, the pin junction of the photosensitive layer can be Ag 2 Te-HgTe-Bi 2 Se 3 . When the transistor-type photodetector is a short-wave infrared detector, the pin junction of the photosensitive layer can be pin GeSn, p-Si/i-Ge/n-Ge, p-PbS-EDT quantum dots/i-halogen skeleton PbS quantum dots/n-ZnO or n- TiO2 . When the transistor-type photodetector is a near-infrared wave detector, the pin junction of the photosensitive layer can be p-NiOx/i-halogen skeleton PbS quantum dots/n-ZnO, and when the transistor-type photodetector is a visible light detector In the case of , the pin junction of the photosensitive layer may be a pin silicon heterojunction. When the transistor-type photodetector is an ultraviolet photodetector, the pin junction of the photosensitive layer can be a ZnO thin film or a pin heterojunction of p-Si/i-ZnO/n-ZnO.
在步骤S1004中,可以在光敏层上制备介质层,其中介质层的材料可以如上所述。例如可以采用电子束蒸镀金属钇,然后进行热氧化,从而在碳纳米管薄膜上形成氧化钇来作为高介电常数介质层。此外,也可以形成多层结构的氧化物来形成高介电常数介质层。In step S1004, a dielectric layer may be prepared on the photosensitive layer, wherein the material of the dielectric layer may be as described above. For example, metal yttrium can be deposited by electron beam evaporation and then thermally oxidized to form yttrium oxide on the carbon nanotube film as a high dielectric constant dielectric layer. In addition, an oxide of a multilayer structure can also be formed to form a high dielectric constant dielectric layer.
在步骤S1006中,在介质层上可以沉积沟道层,例如可以沉积网络状或顺排的高纯度碳纳米管薄膜。如上面说明的,也可以采用晶体或非晶硅、半导体金属氧化物、过渡金属硫族化合物、石墨烯、半导体纳米线、有机半导体等其他二维材料来进行沉积形成沟道层。在本公开中,可以对沉积的碳纳米管的密度进行相应的控制。此外,在碳纳米管沉积完成之后,可以进行高温退火,并且采用例如氧化钇清洗技术来去除碳纳米管表面的有机聚合物。In step S1006, a channel layer may be deposited on the dielectric layer, for example, a network-like or aligned high-purity carbon nanotube thin film may be deposited. As explained above, other two-dimensional materials such as crystalline or amorphous silicon, semiconductor metal oxides, transition metal chalcogenides, graphene, semiconductor nanowires, organic semiconductors, etc. can also be used for deposition to form the channel layer. In the present disclosure, the density of the deposited carbon nanotubes can be controlled accordingly. In addition, after the carbon nanotube deposition is completed, high temperature annealing may be performed, and a cleaning technique such as yttrium oxide may be used to remove organic polymers on the surface of the carbon nanotubes.
在步骤S1008中,可以制备第一电极和第二电极。其中具体地,可以采用曝光、电子束镀膜等微加工工艺来沉积金属材料从而制备第一电极和第二电极。第一电极和第二电极的材料可以为Ti、Pd或Au等金属材料中的一种或多种。In step S1008, a first electrode and a second electrode may be prepared. Specifically, the first electrode and the second electrode can be prepared by depositing a metal material by using a micro-machining process such as exposure and electron beam coating. The material of the first electrode and the second electrode may be one or more of metal materials such as Ti, Pd or Au.
在步骤S1010中,可以诸如曝光、干法刻蚀等工艺对碳纳米管薄膜进行图形化,并且刻蚀沟道区域之外的碳纳米管,从而避免器件之间的电串扰。In step S1010, the carbon nanotube thin film may be patterned by a process such as exposure, dry etching, etc., and the carbon nanotubes outside the channel region are etched, so as to avoid electrical crosstalk between devices.
在步骤S1012中,可以在沟道层上沉积栅绝缘层。栅绝缘层可以为任意的绝缘介质。In step S1012, a gate insulating layer may be deposited on the channel layer. The gate insulating layer can be any insulating medium.
在步骤S1014中,可以在栅绝缘层上制备栅极,采用曝光、电子束镀膜等微加工工艺来沉积金属材料来形成栅极。In step S1014, a gate electrode may be prepared on the gate insulating layer, and a metal material is deposited by micro-processing techniques such as exposure and electron beam coating to form the gate electrode.
还可以包括进行如图6所示的电路连接,进行相应的光电性能测试,通过调控底栅工作电压获得最佳信噪比等。此外,如上面所描述的,也可以包括制备第一功能层和/或第二功能层的步骤。第一功能层可以为滤光层、减反膜、钝化层等中的至少一种,可以设置在光敏层与透明的基底之间。第二功能层可以设置在光敏层和介质层之间,该第二功能层可以用于调整晶体管的阈值电压,例如该第二功能层可以为金属层,此外可以为增反膜等。It may also include making circuit connections as shown in FIG. 6 , conducting corresponding optoelectronic performance tests, and obtaining the best signal-to-noise ratio by adjusting the operating voltage of the bottom gate. Furthermore, as described above, a step of preparing the first functional layer and/or the second functional layer may also be included. The first functional layer may be at least one of a filter layer, an antireflection film, a passivation layer, etc., and may be disposed between the photosensitive layer and the transparent substrate. The second functional layer can be disposed between the photosensitive layer and the dielectric layer, and the second functional layer can be used to adjust the threshold voltage of the transistor. For example, the second functional layer can be a metal layer, and can also be a reflection enhancement film.
图11示出了根据本公开所描述的全局底栅结构的器件示意图。其中介质层140为高介电常数介质层。通过该介质层140的设计可以实现将光敏层150的内建电场的电场信号变化以电容耦合方式作用至沟道层130。根据本公开的独特的器件结构,能够以电容耦合方式实现对光信号(光电压)的有效放大,从而可以获得较高的响应度/外量子效率。而且在这种结构中,光生激子不需要完全分离,只需要产生电偶极子电势,也就是产生电势分布即可,因此可以使得本公开的光电探测器具有极快的响应速度。因此,根据本公开的器件结构,可以解决传统的Photogating型光电探测器中所存在的高响应度与速度难以兼得的弊端,也能够很好地解决光敏层材料与沟道层材料接触,使得光敏层材料影响沟道层材料的输送特性以及传感机制变得复杂等问题。FIG. 11 shows a device schematic diagram of the global bottom gate structure described in accordance with the present disclosure. The
在本公开中,光敏层150设计为通过内建电场实现光生载流子的分离来形成光电压信号,介质层10设计为将光电压信号通过电容耦合方式放大并作用至沟道层130。In the present disclosure, the
在本公开的结构中,内建电场154(图中虚线示出)的作用范围可以形成在整个结的区域,因此可以很好地解决BFBD器件的内建电场作用范围有限的问题,因为在BFBD器件中内建电场的作用范围仅在源漏接触附近约50nm的区域,因此BFBD器件很难获得较高的信噪比。In the structure of the present disclosure, the action range of the built-in electric field 154 (shown by the dotted line in the figure) can be formed in the entire junction area, so the problem of the limited action range of the built-in electric field of the BFBD device can be well solved, because in the BFBD The range of the built-in electric field in the device is only about 50 nm near the source-drain contact, so it is difficult to obtain a high signal-to-noise ratio for BFBD devices.
在此以短波红外探测器为例进行说明,光敏层150可以为光敏层为由PbS量子点和ZnO组成的两层或三层的结结构。例如优选地可以为EDT配体的PbS量子点层和ZnO层构成的p-n结,其中,在介质层140上组装ZnO层,然后在ZnO层上旋涂EDT配体的PbS量子点薄膜。更优选地光敏层150可以为p-i-n结的结结构。可以在介质层140上组装ZnO层,在ZnO层上形成卤素骨架的PbS量子点薄膜,以及再形成EDT配体的PbS量子点薄膜,来形成光敏层。Herein, a short-wave infrared detector is used as an example for description. The
图12至图16示出了沟道层采用网络状碳纳米管,介质层采用氧化钇、光敏层采用p-PbS-EDT量子点/i-卤素骨架的PbS量子点/n-ZnO的p-i-n结的所制成的短波红外探测器件的性能指标的示意图。Figures 12 to 16 show the p-i-n junction where the channel layer adopts network carbon nanotubes, the dielectric layer adopts yttrium oxide, and the photosensitive layer adopts p-PbS-EDT quantum dots/i-halogen skeleton PbS quantum dots/n-ZnO p-i-n junction Schematic diagram of the performance indicators of the fabricated SWIR detection device.
图12示出了器件在1300nm光照条件下,不同光功率下实时的光电响应(其中VGS=0V,VDS=-0.1V),根据测试结果可以清楚地看出,根据本公开的技术方案所制成的器件能够实现光功率密度低于130nW/cm2的极弱光的探测。Figure 12 shows the real-time photoelectric response of the device under 1300nm illumination conditions and different optical powers (wherein V GS =0V, V DS =-0.1V), according to the test results, it can be clearly seen that according to the technical solution of the present disclosure The fabricated device can realize the detection of very weak light with an optical power density below 130 nW/cm 2 .
图13示出了器件在1300nm光照条件下,提取的响应度和光电流,根据测试结构可以清楚地看出,对1300nm弱光的响应度高达104A/WFigure 13 shows the extracted responsivity and photocurrent of the device under 1300nm illumination. According to the test structure, it can be clearly seen that the responsivity to 1300nm weak light is as high as 10 4 A/W
图14示出了器件在1300nm光照条件下的响应速度(左)和恢复速度(右)(VGS=0V,VDS=-0.1V),可以清楚地看出,响应速度及恢复速度可以达到亚ms水平。Figure 14 shows the response speed (left) and recovery speed (right) of the device under 1300nm illumination (V GS =0V, V DS =-0.1V), it can be clearly seen that the response speed and recovery speed can reach sub-ms level.
图15示出了器件在1300nm光照条件下的噪声谱和比探测率,其中可以清楚地看出对弱光的比探测率D*,在1Hz情况下可以高达6×1013;在400Hz情况下,可以高达3×1014;并且在1000Hz的情况下可以高达6×1014。Figure 15 shows the noise spectrum and specific detectivity of the device under 1300nm illumination, where it can be clearly seen that the specific detectivity D* for weak light can be as high as 6×10 13 at 1Hz; at 400Hz , up to 3×10 14 ; and up to 6×10 14 at 1000 Hz.
在图16中示出了根据本公开的技术方案制备的器件与现有的器件之间的性能比较示意图。从比较结果可以看出,根据本公开的器件无论在响应速度还是比探测率方面均明显由于现有的器件。FIG. 16 shows a schematic diagram of the performance comparison between the device prepared according to the technical solution of the present disclosure and the existing device. From the comparison results, it can be seen that the device according to the present disclosure is significantly better than the existing device in terms of response speed and specific detection rate.
在本说明书的描述中,参考术语“一个实施例/方式”、“一些实施例/方式”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例/方式或示例描述的具体特征、结构、材料或者特点包含于本申请的至少一个实施例/方式或示例中。在本说明书中,对上述术语的示意性表述不必须针对的是相同的实施例/方式或示例。而且,描述的具体特征、结构、材料或者特点可以在任一个或多个实施例/方式或示例中以合适的方式结合。此外,在不相互矛盾的情况下,本领域的技术人员可以将本说明书中描述的不同实施例/方式或示例以及不同实施例/方式或示例的特征进行结合和组合。In the description of this specification, references to the terms "one embodiment/mode", "some embodiments/modes", "example", "specific example", or "some examples", etc. are intended to be combined with the description of the embodiment/mode A particular feature, structure, material, or characteristic described by way of example or example is included in at least one embodiment/mode or example of the present application. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment/mode or example. Furthermore, the particular features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments/means or examples. Furthermore, those skilled in the art may combine and combine the different embodiments/modes or examples described in this specification and the features of the different embodiments/modes or examples without conflicting each other.
此外,术语“第一”、“第二”仅用于描述目的,而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此,限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。在本申请的描述中,“多个”的含义是至少两个,例如两个,三个等,除非另有明确具体的限定。In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, a feature delimited with "first", "second" may expressly or implicitly include at least one of that feature. In the description of the present application, "plurality" means at least two, such as two, three, etc., unless expressly and specifically defined otherwise.
本领域的技术人员应当理解,上述实施方式仅仅是为了清楚地说明本公开,而并非是对本公开的范围进行限定。对于所属领域的技术人员而言,在上述公开的基础上还可以做出其它变化或变型,并且这些变化或变型仍处于本公开的范围内。Those skilled in the art should understand that the above-mentioned embodiments are only for clearly illustrating the present disclosure, rather than limiting the scope of the present disclosure. For those skilled in the art, other changes or modifications may also be made on the basis of the above disclosure, and these changes or modifications are still within the scope of the present disclosure.
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