CN114598138A

CN114598138A - Power tube grid end driving circuit

Info

Publication number: CN114598138A
Application number: CN202210236073.5A
Authority: CN
Inventors: 罗寅; 涂才根; 谭在超; 张胜; 丁国华
Original assignee: Suzhou Covette Semiconductor Co ltd
Current assignee: Suzhou Covette Semiconductor Co ltd
Priority date: 2022-03-11
Filing date: 2022-03-11
Publication date: 2022-06-07

Abstract

The invention discloses a gate end driving circuit of a power tube, which comprises: the driving circuit comprises PMOS (P1, P2, P3, P4, P5, P6, P7, P8 and P9), NMOS (N1, N2, N3, N4, N5, N6, N7 and N8), resistors (R1, R2 and R3), Zener diodes (D1 and D2) and a current source Ibias; the technical scheme reduces the limitation of the driving circuit on the process requirement through ingenious design, and the controllable driving current and driving voltage are beneficial to the application of the switch power supply module.

Description

Power tube grid end driving circuit

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to a gate terminal driving circuit of a power tube.

Background

With the development of integrated circuit technology, MOS power transistors have been widely used in various switching power supply management circuits due to their characteristics of high cost performance and high reliability. In order to control the on and off of the MOS power transistor, a special driving circuit is usually required to be designed in the control IC, and the on and off of the MOS power transistor are realized by controlling the voltage of the gate of the power transistor. In order to reduce the conduction loss of the MOS power transistor, the area of the MOS power transistor is generally large, and the parasitic input capacitance of the MOS power transistor is large, so that a certain driving capability is required for driving.

As shown in FIG. 1, the power supplies of all digital gates are VCC (usually 10-30V), and INV 1-INV 7 are inverters; NOR1 is a NOR gate; NAND1 is a NAND gate; the P0 and N0 are two driving tubes and generally have strong driving capability; DRV is an internal driving signal, and the driving capability is weak; the GATE is an output signal and is directly connected with the GATE end of the external MOS power tube. INV2~ INV7, NOR1, NAND1 are for designing dead time, in order to prevent P0, N0 from going through, if DRV goes high, pull down the GATE terminal of N0 first, turn off N0, pull down the GATE terminal of P0 after a certain delay, turn on P0, pull up the output GATE; if DRV becomes low, the GATE terminal of P0 is pulled high quickly, P0 is turned off, the GATE terminal of N0 is pulled high after a certain delay, N0 is turned on, and the output GATE is pulled low.

However, in the existing driving technology, the high level voltage of the driving output GATE is the control chip power supply VCC, so the control chip power supply voltage VCC is not too high, and the GATE oxide breakdown of the external power tube is prevented; the current of the driving transistors P0 and N0 is controlled by the gate-oxide voltage VGS (i.e. VCC), and the driving capability under different power supply voltages is very different. Also, as semiconductor manufacturing technology advances, in more advanced processes of 0.18um and below, the gate oxide thickness is generally thin, the gate oxide operating voltage of the medium voltage tube is generally not allowed to exceed 5V, and the existing driving technology is obviously not suitable for use in the advanced processes.

Aiming at the defects in the prior art, the invention provides a novel power tube gate driving circuit which can solve the driving application problem under the thin gate oxide process and can effectively control the driving voltage and the driving current.

Disclosure of Invention

In order to achieve the purpose, the technical scheme of the invention is as follows: a power tube gate drive circuit, the circuit comprising:

the driving circuit comprises PMOS (P1, P2, P3, P4, P5, P6, P7, P8 and P9), NMOS (N1, N2, N3, N4, N5, N6, N7 and N8), resistors (R1, R2 and R3), Zener diodes (D1 and D2) and a current source Ibias;

the logic control circuit comprises inverters (INV 1, INV2, INV3, INV4, INV5 and INV 6).

As an improvement of the present invention, in the driving circuit, a gate terminal of a PMOS transistor P1 is connected to a gate terminal of a PMOS transistor P2, a source terminal of a PMOS transistor P1 and a source terminal of a PMOS transistor P2 are connected to VDD, a drain terminal of a PMOS transistor P1 is connected to an input terminal of a current source Ibias, a gate terminal of a PMOS transistor P1 is connected to a drain terminal, a drain terminal of the PMOS transistor P2 is connected to a source terminal of a PMOS transistor P3, a drain terminal of the PMOS transistor P3 is connected to a source terminal of a PMOS transistor P4, and a drain terminal of a PMOS transistor P4 is connected to a drain terminal of an NMOS transistor N1.

Based on the technical scheme, the PMOS tube P1 and the PMOS tube P2 form a current mirror.

As an improvement of the present invention, in the driving circuit, a source terminal of an NMOS transistor N1 is grounded, a gate terminal of an NMOS transistor N1 is connected to a gate terminal of an NMOS transistor N2, a gate terminal of an NMOS transistor N1 is connected to a drain terminal, a source terminal of an NMOS transistor N2 is connected to a source terminal of an NMOS transistor N1, and a drain terminal of an NMOS transistor N2 is connected to a source terminal of an NMOS transistor N3.

Based on the technical scheme, the NMOS tube N1 and the NMOS tube N2 form a current mirror.

As an improvement of the invention, in the driving circuit, the drain terminal of an NMOS tube N3 is connected with the drain terminal of a PMOS tube P5, the drain terminal of the PMOS tube P5 is connected with the gate terminal, the source terminal of the PMOS tube P5 is connected with VCC, and the gate terminal of the PMOS tube P5 is connected with the gate terminal of the PMOS tube P6.

Based on the technical scheme, the PMOS tube P5 and the PMOS tube P6 form a current mirror, and the proportion is 1: n, the PMOS pipe P6 is a pull-up driving pipe.

In the driving circuit, a drain terminal of an NMOS tube N4 is connected to a source terminal of an NMOS tube N6, a source terminal of an NMOS tube N4 is connected to a source terminal of an NMOS tube N2, a drain terminal of an NMOS tube N6 is connected to a gate terminal of a PMOS tube P8, a drain terminal of a PMOS tube P7 and an anode of a zener diode D1, a cathode of the zener diode D1 is connected to a source terminal of a PMOS tube P5, a source terminal of the PMOS tube P7 is connected to a cathode of the zener diode D1, a source terminal of an NMOS tube N5 is connected to a source terminal of an NMOS tube N4, a source terminal of an NMOS tube N4 is connected to a source terminal of an NMOS tube N7, a drain terminal of an NMOS tube N7 is connected to a gate terminal of a PMOS tube P7, a gate terminal of a PMOS tube P9, an anode of a source terminal diode D2 and a drain terminal of a PMOS tube P8, and a drain terminal of a PMOS tube P8 is connected to a PMOS tube P7.

Based on the technical scheme, a PMOS tube P7, a PMOS tube P8, an NMOS tube N6, an NMOS tube N7, an NMOS tube N4 and an NMOS tube N5 form a level shift circuit, the gate end of the PMOS tube P9 is connected with the output of the level shift circuit, and the drain end of the PMOS tube P6 is connected with the gate end of the PMOS tube P6; the resistor R1 is connected between the gate terminal of the PMOS transistor P9 and the ground, and starts to act, and the P9 is firstly ensured to be conducted in the initial power-on period, so that the pull-up driving transistor P6 is closed.

As an improvement of the invention, the source end of a PMOS tube P6 is connected with the source end of a PMOS tube P9, the drain end of the PMOS tube P6 is connected with the drain end of an NMOS tube N8, the source end of an NMOS tube N8 is connected with the source end of an NMOS tube N5, a resistor R1 is connected between the source end of the NMOS tube N8 and the GATE end of the PMOS tube P9, the joint of the PMOS tube P6 and the NMOS tube N8 is connected with a GATE end and one end of a divider resistor R2, the other end of the divider resistor R2 is connected with the divider resistor R3, the other end of the divider resistor R3 is connected with the source end of the NMOS tube N8, and the joint of the divider resistor R2 and the divider resistor R3 is connected with the GATE end of the PMOS tube.

Based on the technical scheme, N8 is a pull-down driving tube, and a Gate end is a control signal S2; the driving output GATE has a resistor divider network of R2/R3 to ground.

In the logic control circuit, an input end of an inverter INV1 is connected to a DRV signal, an output end of an inverter INV1 is connected to an input end of an inverter INV2 and an input end of an inverter INV4, an output end of an inverter INV2 outputs an S1 signal, an output end of an inverter INV2 is connected to an input end of an inverter INV3, an output end of an inverter INV3 outputs an S2 signal, an output end of an inverter INV4 is connected to an input end of an inverter INV5, an output end of an inverter INV5 outputs an S3 signal, an output end of an inverter INV5 is connected to an input end of an inverter INV6, and an output end of an inverter INV6 outputs an S4 signal.

As an improvement of the invention, the gate of the PMOS transistor P4 is connected with the S3 signal, the gate of the NMOS transistor N3 is connected with the S4 signal, the gate of the NMOS transistor N4 is connected with the S1 signal, the gate of the NMOS transistor N5 is connected with the S5 signal, and the gate of the NMOS transistor N8 is connected with the S2 signal.

Compared with the prior art, the invention has the beneficial effects that: the invention can solve the driving problem in the design of the thin gate oxide process, can also effectively control the driving voltage and the driving current, and is beneficial to debugging of a system level scheme.

Drawings

Fig. 1 is a schematic diagram of a driving circuit in the prior art.

Fig. 2 is a schematic diagram of a gate driving circuit of a power transistor according to the present invention.

FIG. 3 is a schematic diagram of a gate-side logic control circuit of a power transistor according to the present invention.

Detailed Description

The present invention will be further illustrated with reference to the accompanying drawings and specific embodiments, which are to be understood as merely illustrative of the invention and not as limiting the scope of the invention.

Example (b): referring to fig. 2 and 3, a gate terminal driving circuit of a power transistor includes:

In the drive circuit, the gate end of a PMOS tube P1 is connected with the gate end of a PMOS tube P2, the source ends of the PMOS tubes P1 and P2 are connected with VDD, the drain end of the PMOS tube P1 is connected with the input end of a current source Ibias, the gate end of a PMOS tube P1 is connected with the drain end, the drain end of the PMOS tube P2 is connected with the source end of a PMOS tube P3, the drain end of the PMOS tube P3 is connected with the source end of a PMOS tube P4, and the drain end of the PMOS tube P4 is connected with the drain end of an NMOS tube N1. The PMOS transistor P1 and the PMOS transistor P2 constitute a current mirror.

Further, in the driving circuit, a source end of the NMOS transistor N1 is grounded, a gate end of the NMOS transistor N1 is connected to a gate end of the NMOS transistor N2, a gate end of the NMOS transistor N1 is connected to a drain end, a source end of the NMOS transistor N2 is connected to a source end of the NMOS transistor N1, and a drain end of the NMOS transistor N2 is connected to a source end of the NMOS transistor N3. The NMOS transistor N1 and the NMOS transistor N2 constitute a current mirror.

Furthermore, in the driving circuit, the drain terminal of the NMOS transistor N3 is connected to the drain terminal of the PMOS transistor P5, the drain terminal of the PMOS transistor P5 is connected to the gate terminal, the source terminal of the PMOS transistor P5 is connected to VCC, and the gate terminal of the PMOS transistor P5 is connected to the gate terminal of the PMOS transistor P6. The PMOS tube P5 and the PMOS tube P6 form a current mirror, and the proportion is 1: n, the PMOS pipe P6 is a pull-up driving pipe.

Further, in the driving circuit, a drain terminal of an NMOS transistor N4 is connected to a source terminal of an NMOS transistor N6, a source terminal of an NMOS transistor N4 is connected to a source terminal of an NMOS transistor N2, a drain terminal of an NMOS transistor N6 is connected to a gate terminal of a PMOS transistor P8, a drain terminal of a PMOS transistor P7 and an anode of a zener diode D1, a cathode of the zener diode D1 is connected to a source terminal of a PMOS transistor P5, a source terminal of the PMOS transistor P7 is connected to a cathode of a zener diode D1, a source terminal of an NMOS transistor N5 is connected to a source terminal of an NMOS transistor N4, a source terminal of an NMOS transistor N4 is connected to a source terminal of an NMOS transistor N7, a drain terminal of an NMOS transistor N7 is connected to a gate terminal of a PMOS transistor P7, a gate terminal of a PMOS transistor P9, an anode of a zener diode D2 and a drain terminal of a PMOS transistor P8, and a PMOS transistor P8 is connected to a drain terminal of a PMOS transistor P7. The PMOS tube P7, the PMOS tube P8, the NMOS tube N6, the NMOS tube N7, the NMOS tube N4 and the NMOS tube N5 form a level shift circuit, the gate end of the PMOS tube P9 is connected with the output of the level shift circuit, and the drain end of the PMOS tube P6 is connected with the gate end of the PMOS tube P6; the resistor R1 is connected between the gate terminal of the PMOS transistor P9 and the ground, and starts to act, and the P9 is firstly ensured to be conducted in the initial power-on period, so that the pull-up driving transistor P6 is closed.

Furthermore, the source end of the PMOS transistor P6 is connected to the source end of the PMOS transistor P9, the drain end of the PMOS transistor P6 is connected to the drain end of the NMOS transistor N8, the source end of the NMOS transistor N8 is connected to the source end of the NMOS transistor N5, the resistor R1 is connected between the source end of the NMOS transistor N8 and the GATE end of the PMOS transistor P9, the joint between the PMOS transistor P6 and the NMOS transistor N8 is connected to a GATE end and one end of the resistor R2, the other end of the resistor R2 is connected to the resistor R3, the other end of the resistor R3 is connected to the source end of the NMOS transistor N8, and the joint between the resistor R2 and the resistor R3 is connected to the GATE end of the PMOS transistor. N8 is a pull-down driving tube, and a Gate end is a control signal S2; the driving output GATE has a resistor divider network of R2/R3 to ground.

Further, in the logic control circuit, an input end of an inverter INV1 is connected to the DRV signal, an output end of an inverter INV1 is connected to an input end of an inverter INV2 and an input end of an inverter INV4, an output end of an inverter INV2 outputs an S1 signal, an output end of an inverter INV2 is connected to an input end of an inverter INV3, an output end of an inverter INV3 outputs an S2 signal, an output end of an inverter INV4 is connected to an input end of an inverter INV5, an output end of an inverter INV5 outputs an S3 signal, an output end of an inverter INV5 is connected to an input end of an inverter INV6, and an output end of an inverter INV6 outputs an S4 signal.

Furthermore, the gate of the PMOS transistor P4 is connected to the S3 signal, the gate of the NMOS transistor N3 is connected to the S4 signal, the gate of the NMOS transistor N4 is connected to the S1 signal, the gate of the NMOS transistor N5 is connected to the S5 signal, and the gate of the NMOS transistor N8 is connected to the S2 signal.

The working principle is as follows: the input signal DRV of the driving circuit is changed from low to high, the signal S1 is changed to high, the signal S2 is changed to low, the lower driving tube N8 is turned off, the level shift circuit outputs high level VCC, P9 is turned off, and the current mirrors P5 and P6 can work; meanwhile, the signal S3 goes low, the signal S4 goes high, both P4 and N3 are turned on, the current source Ibias can go through several stages of current mirror switching to generate a driving current in the pull-up driving transistor P6, and the current is determined by the current mirror ratio, such as: P1/P2 and N1/N2 are both 1: 1 current mirror, P5/P6 is 1: n current mirror, the driving current generated by P6 is n × Ibias. After the voltage of the GATE is gradually increased, the voltage of the voltage dividing nodes of R2 and R3 is gradually increased after the voltage is divided by R2 and R3, and when the voltage is increased to a certain degree, P3 is turned off, the current of P6 is finally turned off, the voltage of the voltage dividing nodes of R2 and R3 is reduced, P3 is turned on, the voltage of the output GATE is controlled to be increased again, and finally, the voltage reaches a steady state, and the voltage of the output GATE is finally stabilized at a certain voltage value which is determined by the voltage dividing ratio of R2 and R3. If the low voltage power supply VDD is 5V, the off-state voltage of P3 is about 4V, and the output GATE voltage is (R2 + R3) × 4/R3, but cannot exceed VCC at most.

The input signal DRV of the driving circuit changes from high to low, the signal S3 goes high, the signal S4 goes low, the P4 and the N3 are turned off, and the P5 has no current, so that the pull-up driving tube P6 has no current; meanwhile, the signal S1 becomes low, the signal S2 becomes high, the output voltage of the level shift circuit is VCC-Vdz, Vdz is the breakdown voltage of Zener tubes D1 and D2, P9 is conducted, the Gate end of P6 is pulled high, the current of P6 is completely stopped, and the pull-down driving tube N8 is conducted due to the fact that the signal S2 becomes high, and the output Gate becomes low. The driving current of N8 is completely determined by the low voltage power VDD, which is a fixed voltage, so the current value is controllable.

In the driving circuit provided by the invention, the logic control circuit at the lower half part only gives a logic relation schematically, and the sequence of the control signals S1-S4 can be changed through specific design, such as adjusting the size of a transistor in each logic gate, so that dead time is designed between the pull-up driving tube P6 and the pull-down driving tube N8. Such as: when the input signal DRV is high, after the logic gate delays of INV 8-INV 13, the signal S1 is ensured to be high and the signal S2 is ensured to be low, then the signal S3 is ensured to be low and the signal S4 is ensured to be high, for two driving tubes P6 and N8, N8 is firstly turned off, P6 is then turned on, and a dead time is directly generated between the two driving tubes. When the input signal DRV becomes low, after the logic gate delays of INV 8-INV 13, the signal S3 is ensured to be high and the signal S4 is ensured to be low, then the signal S1 becomes low and the signal S2 becomes high, for two driving tubes P6 and N8, P6 is firstly turned off, and N8 is then turned on, so that dead time is introduced.

The gate oxide voltage of all PMOS and NMOS in the driving circuit does not exceed 5V-5.5V, and the structure can be applied to more advanced thin gate process of 0.18um and below; the driving current of the driving circuit is determined by a specific current mirror proportion and is controllable; the output voltage of the driving circuit can be set through an output resistor network, the output GATE voltage value is constant, and the output GATE voltage value cannot change along with the change of a power supply of a control chip.

It should be noted that the above-mentioned contents only illustrate the technical idea of the present invention, and the protection scope of the present invention is not limited thereby, and it will be apparent to those skilled in the art that several modifications and embellishments can be made without departing from the principle of the present invention, and these modifications and embellishments fall within the protection scope of the claims of the present invention.

Claims

1. A power transistor gate driver circuit, comprising:

the driving circuit comprises PMOS (P1, P2, P3, P4, P5, P6, P7, P8 and P9), NMOS (N1, N2, N3, N4, N5, N6, N7 and N8), resistors (R1, R2 and R3), Zener diodes (D1 and D2) and a current source Ibias; the logic control circuit comprises inverters (INV 1, INV2, INV3, INV4, INV5 and INV 6).

2. The gate terminal driving circuit of claim 1, wherein in the driving circuit, the gate terminal of the PMOS transistor P1 is connected to the gate terminal of the PMOS transistor P2, the source terminals of the PMOS transistor P1 and the PMOS transistor P2 are connected to VDD, the drain terminal of the PMOS transistor P1 is connected to the input terminal of the current source Ibias, the gate terminal and the drain terminal of the PMOS transistor P1 are connected, the drain terminal of the PMOS transistor P2 is connected to the source terminal of the PMOS transistor P3, the drain terminal of the PMOS transistor P3 is connected to the source terminal of the PMOS transistor P4, and the drain terminal of the PMOS transistor P4 is connected to the drain terminal of the NMOS transistor N1.

3. The gate terminal driving circuit of claim 1, wherein in the driving circuit, a source terminal of an NMOS transistor N1 is grounded, a gate terminal of an NMOS transistor N1 is connected to a gate terminal of an NMOS transistor N2, a gate terminal of an NMOS transistor N1 is connected to a drain terminal, a source terminal of an NMOS transistor N2 is connected to a source terminal of an NMOS transistor N1, and a drain terminal of an NMOS transistor N2 is connected to a source terminal of an NMOS transistor N3.

4. The gate driver circuit of claim 1, wherein the drain terminal of the NMOS transistor N3 is connected to the drain terminal of the PMOS transistor P5, the drain terminal of the PMOS transistor P5 is connected to the gate terminal, the source terminal of the PMOS transistor P5 is connected to VCC, and the gate terminal of the PMOS transistor P5 is connected to the gate terminal of the PMOS transistor P6.

5. The gate terminal driving circuit of claim 1, wherein in the driving circuit, a drain terminal of an NMOS transistor N4 is connected to a source terminal of an NMOS transistor N6, a source terminal of an NMOS transistor N4 is connected to a source terminal of an NMOS transistor N2, a drain terminal of an NMOS transistor N6 is connected to a gate terminal of a PMOS transistor P8, a drain terminal of a PMOS transistor P7 and an anode of a zener diode D1, a cathode of the zener diode D1 is connected to a source terminal of a PMOS transistor P5, a source terminal of a PMOS transistor P7 is connected to a cathode of a diode D1, a source terminal of an NMOS transistor N5 is connected to a source terminal of an NMOS transistor N4, a source terminal of an NMOS transistor N4 is connected to a source terminal of an NMOS transistor N7, a drain terminal of an NMOS transistor N7 is connected to a gate terminal of a PMOS transistor P7, a gate terminal of a PMOS transistor P9, an anode of a zener diode D2 and a drain terminal of a PMOS transistor P8, and a drain terminal of a PMOS transistor P8 is connected to a source terminal of a PMOS transistor P7.

6. The GATE driving circuit of claim 1, wherein a source terminal of the PMOS transistor P6 is connected to a source terminal of the PMOS transistor P9, a drain terminal of the PMOS transistor P6 is connected to a drain terminal of the NMOS transistor N8, a source terminal of the NMOS transistor N8 is connected to a source terminal of the NMOS transistor N5, the resistor R1 is connected between the source terminal of the NMOS transistor N8 and the GATE terminal of the PMOS transistor P9, a GATE terminal and one terminal of a resistor R2 are connected to a connection between the PMOS transistor P6 and the NMOS transistor N8, the other terminal of the resistor R2 is connected to the resistor R3, the other terminal of the resistor R3 is connected to the source terminal of the NMOS transistor N8, and a connection point of the resistor R2 and the resistor R3 is connected to the GATE terminal of the PMOS transistor.

7. The gate driver circuit of claim 1, wherein in the logic control circuit, an input terminal of an inverter INV1 is connected to the DRV signal, an output terminal of an inverter INV1 is connected to the input terminals of the inverter INV2 and the input terminal of the inverter INV4, an output terminal of an inverter INV2 outputs the S1 signal, an output terminal of an inverter INV2 is connected to the input terminal of the inverter INV3, an output terminal of an inverter INV3 outputs the S2 signal, an output terminal of an inverter INV4 is connected to the input terminal of an inverter INV5, an output terminal of an inverter INV5 outputs the S3 signal, an output terminal of an inverter INV5 is connected to the input terminal of the inverter INV6, and an output terminal of an inverter INV6 outputs the S4 signal.

8. The gate driver circuit of claim 3, wherein the gate of the PMOS transistor P4 is connected to the S3 signal, the gate of the NMOS transistor N3 is connected to the S4 signal, the gate of the NMOS transistor N4 is connected to the S1 signal, the gate of the NMOS transistor N5 is connected to the S5 signal, and the gate of the NMOS transistor N8 is connected to the S2 signal.

9. The gate driver circuit of claim 1, wherein a dead time is set between the pull-up driving transistor P6 and the pull-down driving transistor N8 by changing the sequence of the control signals S1-S4.