CN114595073A - A pipeline data transmission method and data pipeline device - Google Patents

Abstract

The present invention provides a pipeline data transmission method and a data pipeline device. The data pipeline device includes a pre-stage module, a post-stage module, and a buffer area coupled between the pre-stage module and the post-stage module. The buffer contains complex storage units. The pipeline data transmission method includes: performing multiple write and read rounds; in each write and read round, the front-end module sequentially executes a write action to each storage unit according to a write sequence; and in each write and read round Among them, the post-stage module sequentially performs a read operation on each storage unit according to a read sequence; wherein, in two consecutive write and read rounds, the write sequence in the subsequent write and read rounds is the same as that of the previous one. The read order in the write and read rounds is the same.

Description

A pipeline data transmission method and data pipeline device

technical field

The present invention relates to a data transmission technology, in particular to a pipeline data transmission method and a data pipeline device.

Background technique

In order to avoid power consumption caused by frequent storage and reading to the memory, a buffer can be connected in series between the two electronic components for data transmission between the two for the data transmission end to store the data to be transmitted, and for the data reception end Read the data stored in the buffer. However, when the two electronic components store and read the same buffer at the same time, the problem of data loss will inevitably occur. For example, data is written to an area of the buffer, and new data is written before that area can be read. This problem is particularly prone to occur when the access sequence of the two electronic components to the buffer is different.

In order to overcome this problem, there is a method of using two buffers, and the data transmitting end alternately writes data to the two buffers for the data reading end to read. In this way, although the problem of data loss can be solved, it requires twice the buffer cost.

SUMMARY OF THE INVENTION

In view of the above problems, the present invention provides a pipeline data transmission method, which is applied to a data pipeline device. The data pipeline device includes a pre-stage module, a post-stage module, and a buffer area coupled between the pre-stage module and the post-stage module. The buffer contains complex storage units. The pipelined data transmission method includes: performing multiple write-read rounds; in each write-read round, the front-end module sequentially executes a write operation to each storage unit according to a write-in sequence; and in each write-read round Among them, the post-stage module sequentially performs a read operation on each storage unit according to a read sequence; wherein, in two consecutive write and read rounds, the write sequence in the subsequent write and read rounds is the same as the previous one. The read order in the write and read rounds is the same.

An embodiment of the present invention further provides a data pipeline device, which includes a pre-stage module, a post-stage module, and a buffer area. The buffer is coupled between the preceding module and the succeeding module, and includes a plurality of storage units. The front-level module and the rear-level module perform multiple write and read rounds. In each write-read round, the previous-level module sequentially performs a write operation on each storage unit according to a write sequence, and the subsequent-level module sequentially performs a read operation on each storage unit according to a read sequence action. In two consecutive write-read rounds, the write order in the latter write-read round is the same as the read order in the previous write-read round.

According to the data pipeline device and the pipelined data transmission method proposed in the embodiments of the present invention, in the case of using a single buffer, the previous-level module and the subsequent-level module can each use their write sequence and read sequence to store the data. It can also avoid the problem of data loss caused by overwriting of unread data.

Description of drawings

Below, the preferred embodiments of the present invention will be described in further detail in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic structural diagram of a data pipeline device according to an embodiment of the present invention;

2 is a flowchart of a pipeline data transmission method according to an embodiment of the present invention;

3 is a schematic diagram of performing a write operation to a buffer according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of performing a read operation on a buffer according to an embodiment of the present invention; and

FIG. 5 is a detailed flowchart of a pipeline data transmission method according to an embodiment of the present invention.

【Symbol Description】

100: Data pipeline device

110: Pre-Module

120: Power Module

130:buffer

131: Storage unit

S210, S220, S230: Steps

S510, S520, S530, S540, S550, S560: Steps

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the following detailed description, reference may be made to the accompanying drawings, which are considered a part of this application to illustrate specific embodiments of the application. In the figures, like reference numerals describe substantially similar components in the different figures. Various specific embodiments of the present application are described in sufficient detail below to enable those of ordinary skill with relevant knowledge and technology in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized or structural, logical or electrical changes may be made to the embodiments of the present application.

Referring to FIG. 1 , it is a schematic structural diagram of a data pipeline apparatus according to an embodiment of the present invention. The data pipeline device 100 includes a pre-stage module 110 , a post-stage module 120 , and a buffer area 130 coupled between the pre-stage module 110 and the post-stage module 120 . The pre-stage module 110 and the post-stage module 120 are respectively two independent electronic devices. In some embodiments, the pre-stage module 110 is an image sensor, the post-stage module 120 is an image encoder, and the transmitted data is image data. For convenience of description, the following application scenario will be used as an example for description, but the present invention is not limited to this application scenario. In some embodiments, the post-stage module 120 is an image encoder conforming to a High Efficiency Video Coding (HEVC) architecture.

Referring to FIG. 2 , it is a flowchart of a pipeline data transmission method according to an embodiment of the present invention. The pipeline data transmission method is applied to the aforementioned data pipeline device 100 , so that the front-end module 110 can transmit data to the latter-stage module 120 .

In step S210, a plurality of write and read rounds are performed. That is, after completing one write-read round, continue to execute the next write-read round. In other words, until one write-read round is completed, the next write-read round is not entered. One write-read round means that the front-end module 110 completely writes a piece of data into the buffer 130 , and the latter-stage module 120 completely reads the data from the buffer 130 . The piece of data, taking image data as an example, may be, for example, an image, a certain slice (Slice) of an image, or the like. In some embodiments, during the process of writing data by the previous-stage module 110 (the data has not been completely written), the subsequent-stage module 120 starts to read the data. In some embodiments, within a write/read round, a read operation begins after a write operation completes. Between two consecutive write/read rounds, the next round of write operations can begin before the previous round of read operations has completed.

Referring to FIG. 3 , it is a schematic diagram of performing a write operation to the buffer 130 according to an embodiment of the present invention. The buffer 130 includes a plurality of storage units 131 . The storage unit 131 is the smallest unit for performing one write operation or read operation. The storage unit 131 includes one or more storage units (not shown). The storage unit is the smallest memory unit in the buffer 130 . For example, the storage capacity of one storage unit is one byte, and the storage capacity of one storage unit 131 is four bytes (ie, one storage unit 131 has four storage units). For the convenience of description, only the buffer 130 has 20 storage units 131 as an example here, but the present invention is not limited to this number, and may include fewer or more storage units 131 . Here, the storage units 131 are two-dimensionally arranged in four rows and five columns. In some embodiments, the number of the storage units 131 in a row (here, five) is positively correlated with the stride of the image data. Specifically, the storage units 131 in a row can store a plurality of rows of pixel data of an image. In some embodiments, the number of one row of storage units 131 (here, four) is positively correlated with the height of the image data, that is, one row of storage units 131 can store multiple rows of pixel data of the image. In some embodiments, one storage unit 131 may store one Coding Tree Unit (CTU).

In step S220 , in each write and read round, the preceding module 110 performs a write operation to each storage unit 131 in sequence according to a write sequence. As shown in FIG. 3 , the numbers marked in the storage units 131 are ordinal numbers of the write operations performed for each storage unit 131 . The number "1" represents the first storage unit 131 that performs the writing operation, the number "2" represents the second storage unit 131 that performs the writing operation, and so on. In the embodiment shown in FIG. 3 , after the storage units 131 in the first row are sequentially written from left to right, then the storage units 131 in the second row are written from left to right, and then written from left to right. The storage unit 131 in the third row is finally written to the storage unit 131 in the fourth row from left to right, and this order is generally referred to as a raster order.

In step S230 , in each write and read round, the subsequent module 120 performs a read operation for each storage unit 131 in sequence according to a read sequence. Referring to FIG. 4 , it is a schematic diagram of performing a read operation on the buffer 130 according to an embodiment of the present invention. The numbers marked in the storage units 131 are the ordinal numbers of the read operations performed for each storage unit 131 . The number "1" represents the first storage unit 131 that performs the reading operation, the number "2" represents the second storage unit 131 that performs the reading operation, and so on. In the example shown in FIG. 4 , the storage cells 131 in the first row from the left are read sequentially from top to bottom, then the storage cells 131 in the second row from the left are read from top to bottom, and then the storage cells 131 in the second row from the left are read from top to bottom. The storage unit 131 in the third row from the left is read from the bottom, then the storage unit 131 in the fourth row from the left is read from the top to the bottom, and finally the storage unit 131 in the fifth row from the left is read from the top to the bottom. This order is the Tile order.

For the convenience of description, the following embodiments define the address of the storage unit 131 as an ordinal number as shown in FIG. 3 . That is to say, the address of the storage unit 131 in the first column and the first row is "1", the address of the storage unit 131 in the first column and the second row is "2", and so on. The aforementioned writing sequence refers to a sequence formed by arranging the addresses corresponding to each storage unit 131 in the order in which the writing operations are performed. The aforementioned reading sequence refers to a sequence formed by arranging the addresses corresponding to the respective storage units 131 according to the sequence in which the reading operations are performed.

Referring to Table 1, the writing sequence and the reading sequence of the multiple write-read rounds according to an embodiment of the present invention are shown. It can be seen that in two consecutive write and read rounds, the write order in the latter write and read rounds is the same as the read order in the previous write and read rounds. For example, the write order of the second write-read round is the same as the read order of the first write-read round, and the write order of the third write-read round is the same as the read order of the second write-read round. In this way, in two consecutive write-read rounds, if the execution ordinal number of the write sequence in the subsequent write-read round is smaller than the execution ordinal number of the read sequence in the previous write-read round, it will not make the The read storage unit 131 is written with new data, resulting in data loss. For example, when the execution ordinal number of the read order is "5", the execution ordinal number of the write order can be "1", "2", "3", "4", but not "5" or the following ordinal number . The execution ordinal number refers to the ordinal number of the address of the storage unit 131 to which the writing operation is to be performed currently in the writing sequence. For example, in the write sequence in the second write-read round, if the current write operation is to be performed on the storage unit 131 whose address is "16", the execution sequence number is "4".

Table 1

Referring to Table 1, the writing order and the reading order in the same write-read round are different. Therefore, the pre-stage module 110 and the post-stage module 120 can be respectively written and read according to their requirements. For example, the front-end module 110 as an image sensor writes image data into the buffer 130 column by column, while the post-module 120 as an image encoder needs to read the image data from the buffer 130 block by block. to encode.

Referring to Table 1, there is a mapping relationship between the writing sequence and the reading sequence in the same write-read round, and the mapping relationship of each write-read round is the same. That is to say, in the same write-read round, there is a mapping relationship between the two addresses of the same ordinal number in the write sequence and the read sequence; in each write-read round, the address in the write sequence is mapped to the read sequence The addresses in the fetch order are the same. For example, in the first write and read round, the address with the ordinal "2" in the write order is "2", the address with the same ordinal "2" in the read order is "6", and in the other In the write and read rounds, the address "2" in the write order is mapped to the address "6" in the read order (for example, the ordinal number "5" in the second write and read round). Table 2 shows the mapping relationship between addresses in the writing sequence and addresses in the reading sequence according to an embodiment of the present invention.

Table 2

Referring to FIG. 5 , it is a detailed flowchart of a pipeline data transmission method according to an embodiment of the present invention. First, in step S510, the initial value of the parameter is set. The parameters are parameters used in the following calculation formula, which will be described later.

In step S520, the previous-level module 110 performs a write operation on the storage unit 131 at the current address; the subsequent-level module 120 performs an operation on the storage unit 131 at the current address. For the preceding module 110, the current address is the address corresponding to the current execution ordinal in the writing sequence; for the latter module 120, the current address is the address corresponding to the current execution ordinal in the reading sequence. The current execution ordinal number of the preceding-stage module 110 may be different from the current execution ordinal number of the subsequent-stage module 120 .

After step S520 is completed, step S530 is entered, and the address of the next execution ordinal number is obtained as the current address of the next write or read operation. The calculation formula is shown in formula (1). Add(n) is the write address or read address of the current ordinal number, and Add(n+1) is the write address or read address of the next ordinal number. n is the current ordinal number. p is the displacement between the current address and the next address. If Add(n+1) obtained by Equation (1) is greater than z, then Add(n+1) is updated according to Equation (2). z is the number of storage units 131 . In this example, z is 20. n, p, and z are positive integers. In this supplementary description, in the aforementioned step S510, the initial values of the parameters set: n is 1, Add(1) is 1, the initial value of p of the previous module 110 is 1, and the initial value of p of the rear module 120 is 1. is 5.

Add(n+1)=Add(n)+p Formula (1)

Add(n+1)=Add(n+1)-z+1 Equation (2)

In step S540, it is determined whether the writing or reading of the image data is completed. If yes, go to step S550; if no, go back to step S520 and continue to execute the next write or read action.

In step S550, it is determined whether to execute the next write-read round (ie, it is determined whether the write sequence or the read sequence of the current write-read round is completed). If yes, go to step S560 to update the parameter value, and the calculation formula is as shown in formula (3); if not, end the process. Formula (3) is the result of dividing the product of p and s by z and then taking the largest integer less than or equal to (or called "round down"), plus the result of dividing the product of p and s and the remainder of z, as p-value for the next read and write round. s is a positive integer. In this example, s is positively correlated with the span of image data. Specifically, s is the number of storage units 131 in a row (here, 5), but the embodiment of the present invention is not limited to this, and s can also be set as other values. The p-values corresponding to the write order and the read order in each write and read round are shown in Table 1.

In another embodiment, instead of using Equation (3), the parameter values are updated through Equation (3-1) to Equation (3-3), which can eliminate the need for multiplication and division calculations, which can improve computing performance or reduce hardware body cost. Before executing the formula (3-1), execute the p-order formula (3-2) to obtain the q value. In the process of executing the p-order formula (3-2), check the results after each execution of the formula (3-2), if the calculated q value is greater than z, update the q value according to the formula (3-3), and then Continue the calculation of the next formula (3-2). Finally, use the calculated final q value as the new p value (ie, equation (3-1)), and reset the q value to 0. In this supplementary description, in the aforementioned step S510, the initial value of the parameter set further includes: the initial value of q is 0.

p=q Formula (3-1)

q=q+s Formula (3-2)

q=q-z+1 Formula (3-3)

To sum up, according to the data pipeline device 100 and the pipeline data transmission method proposed in the embodiments of the present invention, in the case of using a single buffer 130 , the front-end module 110 and the latter-stage module 120 can each use its buffer 130 . The buffer 130 is accessed in the order of writing and reading, and at the same time, the problem of data loss caused by overwriting of unread data can be avoided.

The above-mentioned embodiments are only for the purpose of illustrating the present invention, rather than limiting the present invention. Those of ordinary skill in the relevant technical field can also make various changes and modifications without departing from the scope of the present invention. Therefore, all Equivalent technical solutions should also belong to the scope of the disclosure of the present invention.

Claims (16)

1. A pipeline data transmission method, applied to a data pipeline device, the data pipeline device comprises a front-stage module, a rear-stage module and is coupled between the front-stage module and the rear-stage module A buffer of the , the buffer includes a plurality of storage units, and the pipelined data transmission method includes: Execute multiple write and read rounds; In each of the write-read rounds, the front-end module sequentially executes a write operation to each of the storage units in sequence according to a write sequence; and In each of the write-read rounds, the latter-stage module sequentially performs a read operation on each of the storage units in sequence according to a read sequence; Wherein, in two consecutive writing and reading rounds, the writing sequence in the subsequent writing and reading round is the same as the reading order in the preceding writing and reading round. 2 . The pipelined data transmission method of claim 1 , wherein the write order and the read order in the same write-read round are different. 3 . 3. The pipeline data transmission method of claim 2, wherein there is a mapping relationship between the writing sequence and the reading sequence in the same write-read round, and the mapping relationship of each write-read round for the same. 4. The pipeline data transmission method of claim 1, wherein in two consecutive write-read rounds, the execution sequence number of the write-in sequence in the later write-read round is smaller than the previous write-read round The execution ordinal of this read order in . 5. The pipeline data transmission method as claimed in claim 1, wherein at least one of the write sequence and the read sequence is a sequence formed by arranging an address corresponding to each of the storage units according to the sequence in which the related actions are performed , which is expressed as formula (1), if Add(n+1) obtained by formula (1) is greater than z, then update Add(n+1) according to formula (2), where Add(n) is the writing of the current ordinal number Input address, Add(n+1) is the write address of the next ordinal number, z is the number of these storage units, n is the current ordinal number, and n, p, s, and z are positive integers; Add(n+1)=Add(n)+p Formula (1) Add(n+1)=Add(n+1)-z+1 Formula (2). 6. The pipeline data transmission method according to claim 1, wherein after the write and read rounds are completed, the p value is updated according to formula (3);

7. The pipeline data transmission method as claimed in claim 5, wherein when the write and read rounds are completed, the p value is updated according to formula (3-1); p=q Formula (3-1) q=q+s Formula (3-2) q=q-z+1 Formula (3-3) Among them, before executing the formula (3-1), execute the p-order formula (3-2) to obtain the q value, and if the q value after each execution of the formula (3-2) is greater than z, then according to the formula (3- 3) Update the q value, where q is a positive integer. 8. The pipelined data transmission method of claims 5-7, wherein each of the write and read rounds writes an image data to the buffer and reads the image data from the buffer, wherein s and the image The span of the data is positively correlated. 9. A data pipeline device, comprising: A front-end module; a post module; and a buffer, coupled between the front-end module and the back-end module, and including a plurality of storage units; Wherein, the previous-level module and the subsequent-level module perform multiple write-read rounds, and in each write-read round, the previous-level module sequentially executes a write to each of the storage units according to a write sequence an operation, the post-stage module sequentially performs a reading operation on each of the storage units in sequence according to a reading sequence; Wherein, in two consecutive writing and reading rounds, the writing sequence in the subsequent writing and reading round is the same as the reading order in the preceding writing and reading round. 10. The data pipeline apparatus of claim 9, wherein the write order and the read order in the same write-read round are different. 11. The data pipeline device of claim 10, wherein there is a mapping relationship between the writing sequence and the reading sequence in the same write-read round, and the mapping relationship of each write-read round is the same . 12 . The data pipeline device of claim 9 , wherein in two consecutive write-read rounds, the execution ordinal number of the write sequence in the later write-read round is smaller than that in the previous write-read round. 13 . The execution ordinal of this read order. 13. The data pipeline device of claim 9, wherein at least one of the write sequence and the read sequence is a sequence formed by arranging an address corresponding to each of the storage units according to the sequence in which the related actions are performed, wherein Expressed as formula (1), if Add(n+1) obtained by formula (1) is greater than z, then update Add(n+1) according to formula (2), where Add(n) is the write bit of the current ordinal number address, Add(n+1) is the write address of the next ordinal number, z is the number of these storage units, n is the current ordinal number, and n, p, s, and z are positive integers; Add(n+1)=Add(n)+p Formula (1) Add(n+1)=Add(n+1)-z+1 Formula (2). 14. The data pipeline device of claim 13, wherein after the write and read rounds are completed, the p value is updated according to equation (3);

15. The data pipeline device of claim 13, wherein when the write and read rounds are completed, the p value is updated according to equation (3-1); p=q Formula (3-1) q=q+s Formula (3-2) q=q-z+1 Formula (3-3) Among them, before executing the formula (3-1), execute the p-order formula (3-2) to obtain the q value, and if the q value after each execution of the formula (3-2) is greater than z, then according to the formula (3- 3) Update the value of q, where q is a positive integer. 16. A data pipeline arrangement as claimed in any one of claims 13 to 15, wherein s is positively related to the stride of the data.

Images