CN101930713A - Memory architecture of display device and reading method thereof - Google Patents

Abstract

The invention relates to a memory architecture of a display device and a reading method thereof. The display data memory block is provided with N sub memories and N arbiters, wherein the N arbiters are respectively coupled to the N sub memories, and N is a positive integer greater than 1. The processor is used for respectively and continuously outputting the corresponding N control signals and N address signals to the N arbiters. After receiving the corresponding control signals, the N arbiters respectively output corresponding address signals to the corresponding sub-memories, so that the N sub-memories respectively access data simultaneously according to the N address signals.

Description

Memory architecture of display device and reading method thereof

technical field

The present invention relates to a memory architecture of a display device and a reading method thereof, and in particular to a memory architecture of a display device capable of high-speed reading and a reading method thereof.

Background technique

Please refer to FIG. 1 and FIG. 2 , FIG. 1 is a block diagram of a conventional display device, and FIG. 2 is a timing diagram of signals of a conventional display device. As shown in FIG. 1 , the display device 100 includes a processor 120 , a display data memory 140 and a source driving unit 160 . The display data memory 140 includes an arbiter 142 and a memory 144 . If data access to the memory 144 is desired, the processor 120 outputs a write/read signal CPU_write/read and a corresponding address signal CPU_add to the arbiter 142 . The arbiter 142 controls the memory 144 to write or read pixel data according to the write/read signal arb_write/read and the address signal CPU_add_arb.

To display images on the display device 100 , the processor 120 outputs a display read signal LCD_read and a corresponding display address signal LCD_add to the arbiter 142 . The arbiter 142 controls the memory 144 to read display data according to the display read signal LCD_read_arb and the display address signal LCD_add_arb. The memory 144 accesses the pixel data or reads the display data according to the write/read enable signal write/read_en, the display read enable signal LCD_read_en and the enable address signal add_en and outputs it to the processor 120 . The processor 120 outputs the display data to the source driving unit 160 to display images on the display device 100 .

It can be known from FIG. 1 and FIG. 2 that the display data memory 140 accesses data in units of a single pixel. However, in the state of high-speed writing, if the processor 120 intends to read the display data from the memory 144, the speed of data writing may be limited due to the relationship of the reading time. In addition, as the size of the display 100 becomes larger and larger, the capacity requirement of the display data memory 140 is also higher and higher, so that the length of the data wires increases, resulting in consumption due to the high wire load when reading the display data. higher power.

Contents of the invention

The object of the present invention is to provide a memory architecture of a display device and a reading method thereof, which utilizes the architecture of multiple arbitrators so that data in the memory can be read at high speed.

According to a first aspect of the present invention, a memory architecture of a display device is proposed, including a display data memory block and a processor. The display data memory block has N sub-memory and N arbiters, and the N arbiters are respectively coupled to the N sub-memory, and N is a positive integer greater than 1. The processor is used to continuously output corresponding N control signals and N address signals to the N arbiters respectively. Wherein, after receiving the corresponding control signal, the N arbiters respectively output the corresponding address signals to the corresponding sub-memory, so that the N sub-memory respectively access data simultaneously according to the N address signals.

According to a second aspect of the present invention, a method for reading a memory structure of a display device is proposed. The memory structure includes a display data memory block and a processor. The display data memory block has N sub-memory and N arbitrators, where N is a positive integer greater than 1. The reading method includes the following steps. The processor continuously outputs corresponding N control signals and N address signals to the N arbiters respectively. After receiving the corresponding control signal, the N arbiters respectively output the corresponding address signals to the corresponding sub-memory, so that the N sub-memory respectively access data according to the N address signals.

Description of drawings

In order to make the above content of the present invention more obvious and understandable, a preferred embodiment is specifically cited below and described in detail in conjunction with the accompanying drawings as follows, wherein:

FIG. 1 is a block diagram of a conventional display device.

FIG. 2 is a timing diagram of signals of a conventional display device.

FIG. 3 is a block diagram of a display device according to a preferred embodiment of the present invention.

FIG. 4 is a timing diagram of signals of a processor according to a preferred embodiment of the present invention.

5A and 5B are timing diagrams of signals of the arbiter according to a preferred embodiment of the present invention.

FIG. 6 is a timing diagram of signals of a sub-memory according to a preferred embodiment of the present invention.

Detailed ways

The present invention proposes a memory architecture of a display device and a reading method thereof, which uses the architecture of multiple arbitrators and cooperates with the method of reading multiple pixels, so that the data of the memory can be read at high speed and reduce the power consumption of the overall system .

Please refer to FIG. 3 , which shows a block diagram of a display device according to a preferred embodiment of the present invention. The display device 300 includes a processor 320 , a display data memory block 340 and a source driving unit 360 . The display data memory block 340 has N sub-memory and N arbiters, the N arbiters are respectively coupled to the N sub-memory, and N is a positive integer greater than 1. The processor 320 continuously outputs corresponding N control signals and N address signals to the N arbiters respectively. Wherein, after receiving the corresponding control signal, the N arbiters respectively output the corresponding address signals to the corresponding sub-memory, so that the N sub-memory respectively access data simultaneously according to the N address signals. In FIG. 3 , N is equal to 3 as an example for illustration, which means that the data memory block 340 has three sub-memory 344_1 - 344_3 and three arbiters 342_1 - 342_3 , but it is not limited thereto.

Please refer to FIGS. 4 to 6. FIG. 4 shows a timing diagram of signals of a processor according to a preferred embodiment of the present invention, and FIGS. 5A and 5B show timing diagrams of signals of an arbiter according to a preferred embodiment of the present invention. , FIG. 6 shows a timing diagram of signals of the sub-memory according to a preferred embodiment of the present invention. The processor 320 includes a write/read control unit 322 and a display control unit 324 . If it is desired to write pixel data into the display data memory block 340 , the control signal and the address signal output by the processor 320 are respectively a data writing signal and a writing address signal. The write/read control unit 322 continuously outputs three data write signals CPU_write_1 - CPU_write_3 and three corresponding write address signals CPU_add_1 - CPU_add_3 to the arbiters 342_1 - 342_3 respectively.

In this embodiment, each sub-memory is divided into two memory segments, and data corresponding to odd addresses and even addresses are respectively stored as an example for illustration, but it is not limited thereto. For example, the arbiter 342_1 divides the write address signal CPU_add_1 and the corresponding data write signal CPU_write_1 into a sub write address signal CPU_add_arb_odd_1 and a sub data write signal corresponding to odd addresses according to the received write address signal CPU_add_1 write_arb_odd_1, and the sub-write address signal CPU_add_arb_even_1 and the sub-data write signal write_arb_even_1 corresponding to the even address. The arbiter 342_1 outputs the sub-write address signal CPU_add_arb_odd_1 and the sub-data write signal write_arb_odd_1 to the memory segment 344_10 corresponding to the odd address, and outputs the sub-write address signal CPU_add_arb_even_1 and the sub-data write signal write_arb_even_1 to the memory corresponding to the even address Section 344_12.

Similarly, the arbiter 342_2 outputs the sub-write address signal CPU_add_arb_odd_2 and the sub-data write signal write_arb_odd_2 to the memory segment 344_20 corresponding to the odd address, and outputs the sub-write address signal CPU_add_arb_even_2 and the sub-data write signal write_arb_even_2 to the corresponding even number Addresses memory segment 344_22. The arbiter 342_3 outputs the sub-write address signal CPU_add_arb_odd_3 and the sub-data write signal write_arb_odd_3 to the memory segment 344_30 corresponding to the odd address, and outputs the sub-write address signal CPU_add_arb_even_3 and the sub-data write signal write_arb_even_3 to the memory corresponding to the even address Section 344_32.

And if it is desired to read pixel data from the display data memory block 340 , the control signal and address signal output by the processor 320 are respectively a data read signal and a read address signal. The write/read control unit 322 continuously outputs three data read signals CPU_read_1 - CPU_read_3 and corresponding three read address signals CPU_add_1 - CPU_add_3 to the arbiters 342_1 - 342_3 respectively. The arbiter 342_1 divides the read address signal CPU_add_1 and the corresponding data read signal CPU_read_1 into a sub-read address signal CPU_add_arb_odd_1 and a sub-data read signal read_arb_odd_1 corresponding to odd addresses according to the received read address signal CPU_add_1, and the corresponding The sub read address signal CPU_add_arb_even_1 and the sub data read signal read_arb_even_1 at the even address.

The arbiter 342_1 outputs the sub-read address signal CPU_add_arb_odd_1 and the sub-data read signal read_arb_odd_1 to the memory segment 344_10 corresponding to the odd address, and outputs the sub-read address signal CPU_add_arb_even_1 and the sub-data read signal read_arb_even_1 to the memory corresponding to the even address Section 344_12. Similarly, the arbiter 342_2 outputs the sub-read address signal CPU_add_arb_odd_2 and the sub-data read signal read_arb_odd_2 to the memory segment 344_20 corresponding to the odd address, and outputs the sub-read address signal CPU_add_arb_even_2 and the sub-data read signal read_arb_even_2 to the corresponding even number Addresses memory segment 344_22. The arbiter 342_3 outputs the sub-read address signal CPU_add_arb_odd_3 and the sub-data read signal read_arb_odd_3 to the memory segment 344_30 corresponding to the odd address, and outputs the sub-read address signal CPU_add_arb_even_3 and the sub-data read signal read_arb_even_3 to the memory corresponding to the even address Section 344_32.

If a picture is to be displayed on the display device 300, the control signal and the address signal output by the processor 320 are a display read signal and a display address signal respectively. The display control unit 324 continuously outputs three display read signals LCD_read_1 - LCD_read_3 and three corresponding display address signals LCD_add_1 - LCD_add_3 to the arbiters 342_1 - 342_3 respectively. The arbiter 342_1 divides the received display address signal LCD_add_1 into a sub-display address signal LCD_add_arb_odd_1 corresponding to odd addresses and a sub-display address signal LCD_add_arb_even_1 corresponding to even addresses.

The arbiter 342_1 outputs the sub-display address signal LCD_add_arb_odd_1 and the display read signal LCD_read_arb_1 to the memory segment 344_10 corresponding to the odd address, and outputs the sub-display address signal LCD_add_arb_even_1 and the display read signal LCD_read_arb_1 to the memory segment 344_12 corresponding to the even address. Similarly, the arbiter 342_2 outputs the sub-display address signal LCD_add_arb_odd_2 and the display read signal LCD_read_arb_2 to the memory section 344_20 corresponding to the odd address, and outputs the sub-display address signal LCD_add_arb_even_2 and the display read signal LCD_read_arb_2 to the memory section corresponding to the even address Section 344_22. The arbiter 342_3 outputs the sub-display address signal LCD_add_arb_odd_3 and the display read signal LCD_read_arb_3 to the memory segment 344_30 corresponding to the odd address, and outputs the sub-display address signal LCD_add_arb_even_3 and the display read signal LCD_read_arb_3 to the memory segment 344_3 corresponding to the even address.

As shown in FIG. 6, the memory segment 344_10 is enabled according to the write enable signal write_en_odd_1 corresponding to the sub data write signal write_arb_odd_1, the display read enable signal LCD_read_en_1, the sub write address signal CPU_add_arb_even_1 and the sub display address signal LCD_add_arb_odd_1 address signal add_en_odd_1, and output data to the processor 320 accordingly. Similarly, the memory segment 344_12 obtains the enable address signal according to the write enable signal write_en_even_1 corresponding to the sub data write signal write_arb_even_1, the display read enable signal LCD_read_en_1, the sub write address signal CPU_add_arb_even_1 and the sub display address signal LCD_add_arb_even_1 add_en_even_1, and output data to the processor 320 accordingly. That is, the sub-memory 344_1 outputs data to the processor 320 in units of 2 pixels (odd/even pixels). The processor 320 outputs the display data to the source driving unit 360 to display images on the display device 300 . The source driving unit 360 includes circuits such as a shift register and a level shifter.

Similarly, the sub-memory 344_2 ˜ 344_3 also output data to the processor 320 in units of 2 pixels. By comparing Fig. 2 and Fig. 6, it can be seen that in a single cycle (cycle), the data written/read in the sub-memory 344_1-344_3 is far more than the data in the memory 144, which is also consistent with the display device disclosed in the present invention. The advanced memory architecture can provide high-speed access speed faster than traditional ones.

In addition, the present invention also discloses a method for reading a memory structure of a display device. The memory structure includes a display data memory block and a processor, and the display data memory block has N sub-memory and N arbitrators. The reading method includes the following steps. The processor continuously outputs corresponding N control signals and N address signals to the N arbiters respectively. After receiving the corresponding control signal, the N arbiters respectively output the corresponding address signals to the corresponding sub-memory, so that the N sub-memory respectively access data according to the N address signals. Wherein, each sub-memory can be divided into M memory sections.

The operation principle of the above method for reading the memory structure of the display device has been described in detail in the display device 300 , so it will not be repeated here.

The memory architecture of the display device disclosed in the above-mentioned embodiments of the present invention and its reading method have many advantages, and only some of the advantages are listed below:

The memory structure and reading method of the display device disclosed in the present invention utilizes the structure of multiple arbitrators and can cooperate with the method of reading multiple pixels to access the display data memory of the display device. Because the display data memory block of the present invention adopts N arbitrators, the cycle of the control signal and address signal output by the processor only needs to be 1/N of the original cycle, so that the fundamental frequency of the overall system is reduced, and this drop Frequent actions also allow data to have a faster write and read space.

In addition, each sub-memory of the present invention is divided into M memory segments according to addresses. In this way, the data of multiple memory segments can be simultaneously accessed in units of multiple pixels, so that the data reading speed can be increased to M times. In addition, because the display data memory block has a plurality of memory segments, the length of the data wiring can be reduced, thereby reducing the power consumption of the overall system.

To sum up, although the present invention has been disclosed above with preferred embodiments, they are not intended to limit the present invention. Those skilled in the technical field to which the present invention belongs may make various equivalent changes or substitutions without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the appended claims of the application.

Claims (14)

1. A memory architecture of a display device, comprising: A display data memory block, having N sub-memory and N arbiters, the N arbiters are respectively coupled to the N sub-memory, N is a positive integer greater than 1; and A processor, used to successively output corresponding N control signals and N address signals to the N arbiters respectively; Wherein, after receiving the corresponding control signal, the N arbiters respectively output the corresponding address signals to the corresponding sub-memory, so that the N sub-memory respectively access data simultaneously according to the N address signals. 2. The memory architecture of the display device according to claim 1, wherein the control signals are N data write signals, the address signals are N write address signals, and the N arbiters receive the N data write signals respectively. After the N data writing signals, the N sub-memory respectively perform data writing operations simultaneously according to the N writing address signals. 3. The memory architecture of the display device according to claim 2, wherein each sub-memory includes M memory segments, M is a positive integer greater than 1, and each arbiter is based on the received write address signal The write address signal and the corresponding data write signal are divided into M sub-write address signals and M sub-data write signals, and are respectively output to the M memory segments, so that the M memory segments are respectively based on the The M sub-write address signals perform data writing operations. 4. The memory architecture of the display device according to claim 1, wherein the control signals are N data read signals, the address signals are N read address signals, and the N arbiters receive the N data read signals respectively. After the N data read signals, the N sub-memorizers respectively perform data read operations simultaneously according to the N read address signals. 5. The memory architecture of a display device according to claim 4, wherein each sub-memory includes M memory segments, M is a positive integer greater than 1, and each arbiter is based on the received read address signal The read address signal and the corresponding data read signal are divided into M sub-read address signals and M sub-data read signals, and are respectively output to the M memory segments, so that the M memory segments are respectively based on the The M sub-read address signals perform data read operations. 6. The memory architecture of a display device according to claim 1, wherein the control signals are N display read signals, the address signals are N display address signals, and the N arbiters receive the N display address signals respectively. After the display read signals, the N sub-memory respectively read corresponding display data according to the N display address signals and output them to the processor, and the processor receives the display data and outputs them to a source of the display device polar drive unit. 7. The memory architecture of a display device according to claim 6, wherein each sub-memory includes M memory segments, M is a positive integer greater than 1, and each arbiter will The display address signal is divided into M sub-display address signals and output to the M memory segments respectively, so that the M memory segments read corresponding display data simultaneously according to the M sub-display address signals and output to the processor . 8. A memory architecture reading method of a display device, the memory architecture includes a display data memory block and a processor, the display data memory block has N sub-memory and N arbitrators, N is a positive value greater than 1 Integer, the read method includes: The processor continuously outputs corresponding N control signals and N address signals to the N arbiters respectively; and After receiving the corresponding control signals, the N arbiters respectively output the corresponding address signals to the corresponding sub-memory, so that the N sub-memory respectively access data simultaneously according to the N address signals. 9. The memory architecture reading method of a display device according to claim 8, wherein the control signals are N data write signals, and the address signals are N write address signals, and the reading method further comprises: After receiving the N data writing signals respectively, the N arbiters make the N sub-memory respectively perform data writing operations simultaneously according to the N writing address signals. 10. The memory architecture reading method of a display device according to claim 9, wherein each sub-memory comprises M memory segments, and M is a positive integer greater than 1, and the reading method further comprises: Each arbiter distinguishes the write address signal and the corresponding data write signal into M sub-write address signals and M sub-data write signals according to the received write address signal, and outputs them to the M memories respectively section; and The M memory segments respectively perform data writing operations according to the M sub-write address signals. 11. The memory architecture reading method of a display device according to claim 8, wherein the control signals are N data reading signals, and the address signals are N reading address signals, and the reading method further comprises: After receiving the N data read signals respectively, the N arbiters make the N sub-memory respectively perform data read operations simultaneously according to the N read address signals. 12. The memory architecture reading method of a display device according to claim 11, wherein each sub-memory comprises M memory segments, and M is a positive integer greater than 1, and the reading method further comprises: Each arbiter distinguishes the read address signal and the corresponding data read signal into M sub-read address signals and M sub-data read signals according to the received read address signal and outputs them to the M memories respectively section; and The M memory segments perform data reading according to the M sub-read address signals respectively. 13. The memory architecture reading method of a display device according to claim 8, wherein the control signals are N display reading signals, and the address signals are N display address signals, and the reading method further comprises: After the N arbiters respectively receive the N display read signals, the N sub-memory respectively read corresponding display data according to the N display address signals and output them to the processor; and The processor receives the display data and outputs to a source driving unit of the display device. 14. The memory architecture reading method of a display device according to claim 13, wherein each sub-memory comprises M memory segments, and M is a positive integer greater than 1, and the reading method further comprises: Each arbiter divides the display address signal into M sub-display address signals according to the received display address signal and outputs them to the M memory segments respectively; and The M memory segments read corresponding display data simultaneously according to the M sub-display address signals and output them to the processor.

Images