CN114582841B - A MOM capacitor - Google Patents
A MOM capacitorInfo
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- CN114582841B CN114582841B CN202210152934.1A CN202210152934A CN114582841B CN 114582841 B CN114582841 B CN 114582841B CN 202210152934 A CN202210152934 A CN 202210152934A CN 114582841 B CN114582841 B CN 114582841B
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- mom capacitor
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- H10W44/601—
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
- H10D1/692—Electrodes
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Abstract
Disclosed is a MOM capacitor comprising a substrate, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are stacked on the substrate, wherein the first conductive layer and the fourth conductive layer are respectively a polar plate, the second conductive layer comprises a plurality of first electrode strips and second electrode strips which are separated from each other, the third conductive layer comprises a plurality of third electrode strips and fourth electrode strips which are separated from each other, and a plurality of through holes are used for electrically connecting the first conductive layer, the first electrode strips of the second conductive layer, the third electrode strips of the third conductive layer and the fourth conductive layer to form a first electrode, and simultaneously, the second electrode strips of the second conductive layer and the fourth electrode strips of the third conductive layer are electrically connected to form a second electrode, wherein the plurality of second electrode strips are distributed along the same direction, the periphery of each second electrode strip surrounds the first electrode strip, and the fourth electrode strips surround the fourth electrode strip.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a MOM capacitor.
Background
In the field of capacitor array structures, capacitors are a fundamental element of considerable importance. Metal-Oxide-Metal (MOM) capacitors and Metal-Insulator-Metal (MIM) capacitors are two common capacitive structures. The MIM capacitor adopts metal patterns on the same layer or different layers to form the same electrode, and the capacitance value of the MIM capacitor mainly consists of capacitances formed by different conductor layers. The MOM capacitor adopts two electrodes with opposite polarities formed by the same metal pattern layer, so that the capacitance value can comprise the capacitance formed by the same conductor layer.
Referring to fig. 1, the MOM capacitor 100 includes a substrate 101 and a conductive layer M1, the conductive layer M1 includes two comb-shaped first electrodes 102 and second electrodes 103 having opposite polarities, electrode bars included in each of the two comb-shaped structures are staggered so as to form a capacitance between electrode bars of different electrodes, and the capacitance value of the capacitor 100 is equal to the sum of capacitances formed by the electrode bars. The design of the MOM capacitor is beneficial to improving the capacitance per unit area, thereby being beneficial to reducing the occupied area of the MOM capacitor and further being beneficial to improving the integration level of the semiconductor circuit. To increase the capacitance, the MOM capacitor shown in fig. 1 may also be of a stacked design such that the total capacitance is substantially equal to the sum of the capacitance of the same layer, the capacitance between different layers, and the capacitance between the individual electrode strips and the vias.
However, due to the limitation of the design rule, the spacing between the lateral wirings and the spacing between the longitudinal wirings of the electrode bars are different, which may cause limitation to the wiring of the electrode bars.
Disclosure of Invention
In view of the foregoing, an object of the present invention is to provide a MOM capacitor to improve the utilization of the capacitance area.
The present invention provides a MOM capacitor comprising:
A substrate;
A first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked on the substrate, wherein the first conductive layer and the fourth conductive layer are respectively a polar plate, the second conductive layer comprises a plurality of first electrode strips and second electrode strips which are separated from each other, the third conductive layer comprises a plurality of third electrode strips and fourth electrode strips which are separated from each other, and
A plurality of vias for electrically connecting the first conductive layer, the first electrode bar of the second conductive layer, the third electrode bar of the third conductive layer, and the fourth conductive layer to form a first electrode, and for electrically connecting the second electrode bar of the second conductive layer and the fourth electrode bar of the third conductive layer to form a second electrode;
the plurality of second electrode strips are distributed along the same direction, the periphery of each second electrode strip surrounds the first electrode strip, the fourth electrode strip is a polar plate, and the plurality of third electrode strips surround the fourth electrode strip.
Preferably, the plurality of second electrode strips are mutually independent finger electrodes.
Preferably, the plurality of first electrode strips are a plurality of rectangular frames connected together, each rectangular frame having a second electrode strip spaced apart from the rectangular frame.
Preferably, the fourth electrode strip further comprises a finger-shaped electrode strip, and the periphery of the electrode strip is connected with the electrode strip.
Preferably, the electrode plate is rectangular, and the finger electrode strips are positioned on four sides of the electrode plate, are perpendicular to the four sides of the electrode plate, and are connected with the four sides of the electrode plate.
Preferably, the third electrode strip is a rectangular frame, and four sides of the rectangular frame are provided with openings.
Preferably, the projection of the second electrode strip on the third conductive layer is located in the area of the fourth electrode strip.
Preferably, the second conductive layer comprises any number of layers, and any number of layers of the second conductive layer are stacked and arranged between the first conductive layer and the third conductive layer.
Preferably, the second electrode stripes in each of the second conductive layers are arranged in the same first direction.
Preferably, the arrangement direction of the second electrode bars in the same second conductive layer is the same, and the second electrode bars in different second conductive layers are arranged in different directions.
Preferably, the first electrode strips of adjacent second conductive layers are electrically connected, and the second electrode strips of adjacent second conductive layers are electrically connected.
Preferably, the semiconductor device further includes a second conductive layer and a third conductive layer having the same number of layers, and the second conductive layer and the third conductive layer are alternately stacked in a direction perpendicular to the substrate.
Preferably, the semiconductor device further comprises a virtual layer located between the substrate and the first conductive layer, wherein the virtual layer sequentially comprises a well layer, an active layer, a virtual active layer and a virtual gate layer from bottom to top, and the well layer and the active layer are connected through a contact hole.
Preferably, the projections of the first conductive layer and the second conductive layer on the substrate fall into the area where the well layer is located.
According to the MOM capacitor, through the cooperation of the two conductive layers, one conductive layer comprises a plurality of electrodes distributed in the same direction, electrode strips in the other conductive layer are integral electrode plates, the electrodes distributed in the same direction are covered, the electrodes are distributed in the same direction, the limitation of criss-cross wiring is relieved, the wiring of the electrodes is relatively simple, and meanwhile, the integral electrode plates are used as the electrodes, so that the capacitance area is increased.
Furthermore, the MOM capacitor provided by the embodiment of the invention adopts the electrode strip of the first electrode to protect the electrode strip of the second electrode, so that parasitic capacitance is only introduced between the power ground and the first electrode, and the parasitic capacitance between the second electrode and the power ground is basically negligible.
In a preferred embodiment, the overall capacitance value of the MOM capacitor is increased by the stacked design of the fourth conductive layer and the second conductive layer.
In a preferred embodiment, the well layer, the active layer, the dummy active layer and the dummy gate layer are disposed in the semiconductor substrate to block noise from the semiconductor substrate, thereby preventing noise from entering the MOM capacitor.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:
Fig. 1 shows a schematic perspective structure of a MOM capacitor of the prior art;
fig. 2 shows a schematic perspective view of a MOM capacitor according to a first embodiment of the present invention;
fig. 3 shows a schematic top view of a second conductive layer according to a first embodiment of the present invention;
fig. 4 is a schematic top view of a third conductive layer according to a first embodiment of the present invention;
fig. 5 shows a schematic perspective view of a MOM capacitor according to a second embodiment of the present invention;
Fig. 6 is a schematic perspective view showing a MOM capacitor according to a third embodiment of the present invention;
fig. 7 shows a cross-sectional view of a MOM capacitor according to a fourth embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown.
The invention may be embodied in various forms, some examples of which are described below.
Fig. 2 shows a schematic perspective view of a MOM capacitor 200 according to a first embodiment of the present invention, and as shown in fig. 2, the MOM capacitor 200 includes a substrate 201, a plurality of conductive layers 202 on the substrate 201, and insulating layers filled between the conductive layers 202 and between electrode bars of the same conductive layer 202. Wherein the conductive layer 202 includes a first conductive layer 21, a second conductive layer 22, a third conductive layer 23, and a fourth conductive layer 24.
Each of the first to fourth conductive layers 21 to 24 may be made of various metals. The first conductive layer 21 is located over the substrate 201. The first conductive layer 21 and the fourth conductive layer 24 are a metal plate, and no opening or hollow is formed thereon. A second conductive layer 22 is formed over the first conductive layer 21, a third conductive layer 23 is formed over the second conductive layer 22, and a fourth conductive layer 24 is formed over the third conductive layer 23. The second conductive layer 22 and the third conductive layer 23 comprise a plurality of electrode strips, a part of the electrode strips of the second conductive layer 22 are electrically connected with the first conductive layer 21 through the through holes 25, a part of the electrode strips of the third conductive layer 23 are electrically connected with the fourth conductive layer 24 through the through holes 25, and the rest of the electrode strips of the second conductive layer 22 are electrically connected with the rest of the electrode strips of the third conductive layer 23. In the MOM capacitor 200, the first conductive layer 21, the fourth conductive layer 24, a part of the electrode bars of the second conductive layer 22 electrically connected to the first conductive layer 21, and a part of the electrode bars of the third conductive layer 23 electrically connected to the fourth conductive layer 24 are used as the first electrode, and the other part of the electrode bars remaining in the second conductive layer and the other part of the electrode bars remaining in the third conductive layer are used as the second electrode. The first electrode and the second electrode are of opposite polarity, thereby forming a capacitance between the first electrode and the second electrode.
Fig. 3 shows a schematic top view of a second conductive layer according to a first embodiment of the present invention, as shown in fig. 3, the second conductive layer 22 includes a first electrode bar 221 and a second electrode bar 222 that are spaced apart from each other, the second electrode bar 222 is a plurality of mutually independent finger electrodes, the plurality of mutually independent finger electrodes are distributed in a plane of the second conductive layer 22 along a same direction, and the periphery of each second electrode bar 222 surrounds the first electrode bar 221.
In this embodiment, the second conductive layer 22 includes two finger-shaped second electrode strips 222, and the finger-shaped second electrode strips 222 are distributed in the plane of the second conductive layer 22 along the first direction. The first electrode strips 221 are a plurality of rectangular frames connected together, and a second electrode strip 222 is distributed inside the first electrode strip 221 of each rectangular frame so as to realize that the periphery of each second electrode strip 222 surrounds the first electrode strip 221.
Fig. 4 shows a schematic top view of a third conductive layer according to the first embodiment of the present invention, and as shown in fig. 4, the third conductive layer 23 includes a third electrode bar 231 and a fourth electrode bar 232 spaced apart from each other. The fourth electrode strip 232 is a monolithic metal plate, and the third electrode strip 231 surrounds the fourth electrode strip 232.
In this embodiment, the fourth electrode strip 232 includes a rectangular fourth electrode strip 2321 and a plurality of finger-shaped fourth electrode strips 2322, where the plurality of finger-shaped fourth electrode strips 2322 are located on four sides of the rectangular fourth electrode strip 2321, are perpendicular to the four sides of the rectangular fourth electrode strip 2321, and are connected to the four sides of the rectangular fourth electrode strip 2321, and the plurality of finger-shaped fourth electrode strips 2322 extend from the four sides of the rectangular fourth electrode strip 2321 toward a direction away from the rectangular fourth electrode strip 2321.
The third electrode bar 231 is a rectangular frame surrounding the fourth electrode bar 232, and four sides of the rectangular frame are provided with openings 2311, and a finger-shaped fourth electrode bar 2322 passes through the openings 2311 and extends to the outside of the third electrode bar 231 to be connected with adjacent MOM capacitors.
The projection of the second electrode strip 222 onto the third conductive layer 23 is located in the area of the fourth electrode strip 232, i.e. the fourth electrode strip 232 covers the projection of all second electrode strips 122 onto the third conductive layer 23.
The first electrode bar 221 of the second conductive layer 22 is connected to the first conductive layer 21 through a first via 251, the third electrode bar 231 of the third conductive layer 23 is connected to the fourth conductive layer 24 through a second via 252, each second electrode bar 222 of the second conductive layer 22 is connected to the fourth electrode bar 232 of the third conductive layer through a third via 253, and the first electrode bar 221 of the second conductive layer 22 is connected to the third electrode bar 231 of the third conductive layer through a fourth via 254.
In the MOM capacitor 200, the first electrode bar 221, in which the first conductive layer 21, the fourth conductive layer 24, and the second conductive layer 22 are electrically connected to the first conductive layer 21, and the third electrode bar 231, in which the third conductive layer 23 is electrically connected to the fourth conductive layer 24, are used as the first electrodes, and the second electrode bar 222, in which the second conductive layer 22 remains, and the fourth electrode bar 232, in which the third conductive layer 23 remains, are used as the second electrodes. The first electrode and the second electrode are of opposite polarity, thereby forming a capacitance between the first electrode and the second electrode.
For ease of illustration, fig. 3 and 4 show one particular layout design, but the practice of the invention is not limited to that layout design. For example, the layout design shown in fig. 3 is used to explain the core idea that the electrode strips serving as the second electrodes in the second conductive layer are distributed in the same direction, and the electrode strips serving as the second electrodes in the third conductive layer are monolithic electrode plates. In other layout designs, any number of first electrode bars and second electrode bars may be provided, and the same or similar effects can be produced as long as the core ideas described above are satisfied.
In the embodiment, the first electrode and the second electrode are formed by matching the two conductive layers, wherein one conductive layer comprises a plurality of electrodes distributed in the same direction, electrode strips in the other conductive layer are integral electrode plates and cover the electrodes distributed in the same direction, the electrodes are distributed in the same direction, the limitation of criss-cross wiring is relieved, the wiring of the electrodes is relatively simple, and meanwhile, the integral electrode plates are used as the electrodes, so that the capacitance area is increased.
Further, in the present embodiment, since the first conductive layer and the third conductive layer have a planar shape and are used as the first electrode, only the first electrode faces the power ground, so that parasitic capacitance is introduced between only the first electrode opposite to the power ground, and the electrode bar used as the second electrode is surrounded by the electrode bar used as the first electrode, so that parasitic capacitance between the second electrode and the power ground is substantially negligible. In this embodiment, therefore, the parasitic capacitance between the second electrode and the power supply ground can be significantly reduced. Further, by increasing the surface area of the first conductive layer, the parasitic capacitance between the first electrode and the power ground can be further reduced, although the parasitic capacitance before the first electrode and the power ground is also increased.
Of course, the surface area of the first conductive layer may also be reduced appropriately to further reduce the cost. For example, the surface area of the first conductive layer may be reduced to just shield the respective ends of the electrode bars serving as the second electrodes in the second conductive layer, so that although the parasitic capacitance between the second electrodes and the power ground may increase, the magnitude of the increase is within a tolerable range. Typically, the parasitic capacitance should be less than 5% of the capacitance value between the first electrode and the second electrode. In summary, although the MOM capacitor provided in the present embodiment has the parasitic capacitance between the first electrode and the power ground, the parasitic capacitance between the second electrode and the power ground is small, and even approaches 0, because the second electrode is almost completely protected by the first electrode.
Fig. 5 shows a schematic perspective view of a MOM capacitor according to a second embodiment of the present invention, and as shown in fig. 5, the conductive layer 202 of the MOM capacitor according to the present embodiment is provided with an arbitrary number of second conductive layers 22, and the arbitrary number of second conductive layers 22 are stacked and located between the first conductive layers 21 and the third conductive layers 23, compared with the first embodiment. In this embodiment, the overall capacitance of the MOM capacitor is increased by the second conductive layer 22 of the stacked design. But essentially the core idea of such a layout design is the same as the one described above.
Specifically, the shapes of the first electrode bars 221 and the second electrode bars 222 in each second conductive layer 22 are the same, wherein the distribution directions of the second electrode bars 222 in different second conductive layers 22 may be the same or different, for example, in the present embodiment, the second electrode bars 222 in each second conductive layer 22 are arranged in the same first direction, in other embodiments, the arrangement directions of the second electrode bars 222 in the same second conductive layer 22 are the same, and the second electrode bars 222 in different second conductive layers 22 may be arranged in different directions (for example, directions perpendicular to each other).
The first electrode bars 221 of the adjacent second conductive layers 22 are electrically connected, the first electrode bars 221 of the second conductive layers adjacent to the first conductive layer 21 are electrically connected to the first conductive layer 21, the first electrode bars 221 of the second conductive layers 22 adjacent to the third conductive layer 23 are electrically connected to the third electrode bars 231 of the third conductive layer 23, the second electrode bars 222 of the adjacent second conductive layers 22 are electrically connected, and the second electrode bars 222 of the second conductive layers 22 adjacent to the third conductive layer 23 are electrically connected to the fourth electrode bars 232 of the third conductive layer 23.
Fig. 6 shows a schematic perspective view of a MOM capacitor according to a third embodiment of the present invention, and as shown in fig. 6, the conductive layer 202 of the MOM capacitor according to the present embodiment may be provided with an arbitrary number of layers of the second conductive layer 22 and the third conductive layer 23, the number of layers of the second conductive layer 22 and the third conductive layer 23 of the arbitrary layer being the same, and the second conductive layer 22 and the third conductive layer 23 being alternately stacked along a direction perpendicular to the substrate, as compared with the first embodiment.
In fig. 6, two sets of the second conductive layer 22 and the third conductive layer 23 are provided in a direction perpendicular to the substrate, and the second conductive layer and the third conductive layer 23 are alternately laminated in the direction perpendicular to the substrate. In the present embodiment, the overall capacitance value of the MOM capacitor is increased by the plurality of sets of the second conductive layer 22 and the third conductive layer 23 designed in a stacked manner. But essentially the core idea of such a layout design is the same as the one described above.
Fig. 7 shows a cross-sectional view of a MOM capacitor according to a fourth embodiment of the present invention. As shown in fig. 7, compared with the first embodiment, in the MOM capacitor shown in the present embodiment, the MOM capacitor further includes a dummy layer located between the substrate 201 and the first conductive layer 21, the dummy layer includes, from bottom to top, a well layer 401, an active layer 402, a dummy active layer 403, and a dummy gate layer 404, where the well layer 401 and the active layer 402 are connected through a contact hole 405.
For the semiconductor device of the embodiment of the present invention, the well layer 401 and the active layer 402 may act as a barrier to noise from the semiconductor substrate 201, thereby preventing noise from entering the MOM capacitor.
The projection of the MOM capacitor on the upper surface of the semiconductor substrate 201 can be completely in the area where the well layer 401 is located by adjusting the design scheme. This design may better prevent noise from the semiconductor substrate 201 from entering the MOM capacitance.
Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.
Claims (13)
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| CN110416188A (en) * | 2017-11-30 | 2019-11-05 | 联发科技股份有限公司 | Capacitor |
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| KR100971552B1 (en) * | 2008-07-17 | 2010-07-21 | 삼성전자주식회사 | Flash memory device and its operation method |
| US8604531B2 (en) * | 2010-10-15 | 2013-12-10 | Taiwan Semiconductor Manufacturing Company | Method and apparatus for improving capacitor capacitance and compatibility |
| US20140049872A1 (en) * | 2012-08-16 | 2014-02-20 | Himax Technologies Limited | Metal-oxide-metal capacitor able to reduce area of capacitor arrays |
| KR101927667B1 (en) * | 2018-03-15 | 2018-12-10 | 한국과학기술원 | Single event effect and total ionizing effect hardened n-mosfet layout |
| CN111430328B (en) * | 2019-04-25 | 2021-07-27 | 合肥晶合集成电路股份有限公司 | Capacitive semiconductor element |
| WO2021092764A1 (en) * | 2019-11-12 | 2021-05-20 | 华为技术有限公司 | Semiconductor device |
| CN111129304B (en) * | 2019-11-28 | 2023-06-02 | 联芸科技(杭州)股份有限公司 | MOM capacitor, capacitor array structure and layout design method thereof |
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