CN114582282B - ESD protection circuit and display device - Google Patents
ESD protection circuit and display device Download PDFInfo
- Publication number
- CN114582282B CN114582282B CN202210328429.8A CN202210328429A CN114582282B CN 114582282 B CN114582282 B CN 114582282B CN 202210328429 A CN202210328429 A CN 202210328429A CN 114582282 B CN114582282 B CN 114582282B
- Authority
- CN
- China
- Prior art keywords
- transistor
- electrically connected
- module
- node
- esd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001514 detection method Methods 0.000 claims abstract description 67
- 230000002159 abnormal effect Effects 0.000 claims abstract description 36
- 238000007599 discharging Methods 0.000 claims abstract description 29
- 230000003321 amplification Effects 0.000 claims abstract description 8
- 238000003199 nucleic acid amplification method Methods 0.000 claims abstract description 8
- 230000000694 effects Effects 0.000 abstract description 10
- 238000005516 engineering process Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 5
- 150000004706 metal oxides Chemical class 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K9/00—Screening of apparatus or components against electric or magnetic fields
- H05K9/0073—Shielding materials
- H05K9/0079—Electrostatic discharge protection, e.g. ESD treated surface for rapid dissipation of charges
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/04—Display protection
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The ESD protection circuit and the display device provided by the embodiment of the application comprise a detection module, an amplifying module and a discharging module, wherein the detection module can sense that the ESD abnormal charge occurs on the I/O terminal at a higher speed; and then the ESD abnormal charge is amplified through the amplifying module, so that the discharging module is more fully conducted, and a better ESD protection effect is realized. The embodiment of the application adopts the low-temperature polycrystalline oxide transistor technology, can realize a detection module and an amplification module with good performance, ensures that the discharge module has smaller leakage charge in the normal working process, can release the ESD abnormal charge at a relatively high corresponding speed when the ESD abnormal charge occurs, protects an I/O circuit and related circuits thereof, and is not damaged by impact current and impact voltage.
Description
Technical Field
The application relates to the technical field of display, in particular to an ESD protection circuit and a display device.
Background
Currently, an organic light emitting diode display of an active matrix is widely applied to a medium and small sized display panel, and gradually becomes a mainstream of display technology. Specifically, a hybrid transistor technology based on low-temperature polysilicon and metal oxide formation, i.e., a low-temperature polysilicon oxide technology, has begun to become a backlight technology for high-end display. The low-temperature polycrystalline oxide technology has the characteristics of high mobility, high driving capability and low leakage current, and can obviously reduce the leakage current and charge of the internal nodes of the organic light-emitting diode pixels of the active matrix, thereby obviously reducing the display driving power consumption in low-frame occasions.
However, most of the low-temperature poly-oxide transistor technology has been used to improve the performance of the organic light emitting diode pixel circuit of the active matrix, and little research has been done so far to build high-performance peripheral driving circuits, especially with respect to ESD protection circuits.
The existing ESD circuit not only needs to have a strong protection effect, but also needs to ensure that the leakage current is low in the normal working process of the I/O terminal. However, there is a contradiction between the two, and from the viewpoint of improving the ESD protection effect, the smaller the number of TFTs connected in series in the existing ESD circuit, the better, but this causes that a certain amount of high voltage is output from the I/O terminal in normal operation. Therefore, in the existing ESD circuit, because the structural parameters of the device are difficult to optimize and select, and are limited by the principle defects of the circuit, the existing ESD circuit is difficult to simultaneously consider the ESD protection effect, lower leakage, smaller circuit area, lower power consumption and other indexes no matter how the channel width and length of the TFT are selected.
Therefore, how to provide an ESD circuit, which can take into consideration the ESD protection effect, lower leakage, smaller circuit area, lower power consumption, etc. is a difficulty that the existing panel manufacturers need to strive to overcome.
Disclosure of Invention
An object of the embodiment of the present application is to provide an ESD circuit and a display device, which can solve the technical problems that the existing ESD circuit is difficult to simultaneously consider the ESD protection effect, lower leakage, smaller circuit area, lower power consumption and other indexes.
The embodiment of the application provides an ESD circuit, which comprises a first power line, a second power line, a reference high-voltage signal line, a reference low-voltage signal line, a detection module, an amplification module and a discharge module; wherein,,
the first power line is provided with an I/O end, the first power line is used for providing normal working high voltage, the second power line is used for providing discharge voltage, the reference high voltage signal line is used for providing reference high voltage, and the reference low voltage signal line is used for improving reference low voltage;
the detection module is electrically connected with the I/O end, the second power line and the amplifying module, and is used for detecting whether the ESD abnormal charge occurs at the I/O end, and if so, transmitting the ESD abnormal charge to the amplifying module;
the amplifying module is electrically connected with the reference high-voltage signal line, the reference low-voltage signal line, the detecting module and the discharging module, and is used for amplifying the ESD abnormal charge and transmitting the amplified ESD abnormal charge to the discharging module;
the discharging module is electrically connected to the first power line, the second power line and the amplifying module, and is used for releasing the ESD abnormal charge of the I/O terminal when the amplified ESD abnormal charge is received.
In the ESD circuit of the present application, the detection module includes a first resistive element and a second resistive element, one end of the first resistive element is electrically connected to the I/O terminal, the other end of the first resistive element is connected to a first node, one end of the second resistive element is electrically connected to the second power line, and the other end of the second resistive element is electrically connected to the first node.
In the ESD circuit of the present application, the first resistive element includes a first detection transistor, the second resistive element includes a second detection transistor, a gate of the first detection transistor is electrically connected to the first node, one of a source and a drain of the first detection transistor is electrically connected to the I/O terminal, the other of the source and the drain of the first detection transistor is electrically connected to the first node, a gate of the second detection transistor is electrically connected to the second power line, one of the source and the drain of the second detection transistor is electrically connected to the first node, and the other of the source and the drain of the second detection transistor is electrically connected to the second power line.
In the ESD circuit described herein, the channel width of the second detection transistor is a ratio of the channel width of the first detection transistor to 9 to 11.
In the ESD circuit described in this application, the amplifying module includes a first buffer amplifier and a second buffer amplifier, where an input end of the first buffer amplifier is electrically connected to the first node, an output end of the first buffer amplifier is electrically connected to the second node, an input end of the second buffer amplifier is electrically connected to the second node, and an output end of the second buffer amplifier is electrically connected to the third node.
In the ESD circuit described in the application, the first buffer amplifier includes a first amplifying transistor and a second amplifying transistor, the second buffer amplifier includes a third amplifying transistor and a fourth amplifying transistor, the gate of the first amplifying transistor is electrically connected to the first node, one of the source and the drain of the first amplifying transistor is electrically connected to the reference high voltage signal line, the other of the source and the drain of the first amplifying transistor is electrically connected to the second node, the gate of the second amplifying transistor is electrically connected to the second node, one of the source and the drain of the second amplifying transistor is connected to the reference high voltage signal line, the other of the source and the drain of the second amplifying transistor is electrically connected to a third node, the gate of the third amplifying transistor is electrically connected to the first node, one of the source and the drain of the third amplifying transistor is connected to the reference low voltage signal line, the other of the source and the drain of the third amplifying transistor is electrically connected to the first node, the other of the source and the drain of the second amplifying transistor is electrically connected to the second node, and the other of the source and the source of the third amplifying transistor is electrically connected to the third node.
In the ESD circuit described in the present application, the first amplifying transistor and the second amplifying transistor are n-type transistors, and the third amplifying transistor and the fourth amplifying transistor are p-type transistors.
In the ESD circuit of the present application, the discharge module includes a first discharge transistor and a second discharge transistor, a gate of the first discharge transistor is electrically connected to the first power line, one of a source and a drain of the first discharge transistor is electrically connected to the first power line, the other of the source and the drain of the first discharge transistor is electrically connected to one of the source and the drain of the second discharge transistor, the other of the source and the drain of the second discharge transistor is electrically connected to the second power line, and a gate of the second discharge transistor is electrically connected to the third node.
In the ESD circuit described in the present application, the voltage values of the normal operation high voltage, the reference low voltage, and the discharge voltage decrease in order.
The embodiment of the application also provides a display device, which comprises a display panel and a driving chip connected with the display panel; wherein the driving chip is provided with the ESD protection circuit.
In the ESD protection circuit and the display device provided in the embodiments of the present application, a low-temperature polycrystalline oxide transistor technology is adopted, where the ESD protection circuit includes a detection module, an amplifying module, and a discharging module, and the detection module is adopted to sense that an ESD abnormal charge, such as an instantaneous high-level pulse, occurs on an I/O terminal at a relatively high speed; and then the ESD abnormal charge is amplified through the amplifying module, so that the discharging module is more fully conducted, and a better ESD protection effect is realized. Because the embodiment of the application adopts the low-temperature polycrystalline oxide transistor technology, not only an n-type semiconductor transistor, such as a metal oxide transistor, but also a p-type semiconductor transistor, such as a low-temperature polycrystalline silicon transistor, can be realized, so that a detection module and an amplification module with good performance can be realized, the leakage charge of a discharge module is smaller in the normal working process, and the ESD abnormal charge can be released at a faster corresponding speed when the ESD abnormal charge occurs, thereby protecting an I/O circuit and related circuits thereof from being damaged by impact current and impact voltage.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a circuit schematic diagram of an ESD protection circuit provided in the prior art.
Fig. 2 is a schematic structural diagram of a first implementation of the ESD protection circuit provided in the embodiment of the present application.
Fig. 3 is a schematic structural diagram of a second implementation of the ESD protection circuit provided in the embodiment of the present application.
Fig. 4 is a circuit schematic diagram of a second implementation of the ESD protection circuit provided in the embodiment of the present application.
Fig. 5 is a circuit schematic diagram of the ESD protection circuit provided in the embodiment of the present application in a normal working state.
Fig. 6 is a circuit schematic diagram of the ESD protection circuit provided in the embodiment of the present application in a high voltage protection state.
Fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and the source and drain of the transistors used herein are symmetrical, so that the source and drain may be interchanged. In the embodiment of the present application, to distinguish between two electrodes of the transistor except the gate, one electrode is referred to as a source electrode and the other electrode is referred to as a drain electrode. The middle terminal of the switching transistor is defined as a gate, the signal input terminal is defined as a source, and the output terminal is defined as a drain according to the form in the figure.
Referring to fig. 1, fig. 1 is a circuit schematic diagram of an ESD protection circuit provided in the prior art. As shown in fig. 1, the ESD protection circuit of the prior art is composed of three n-type transistors, such as metal oxide transistors, connected in series.
In order to improve the protection effect of the ESD protection circuit, the fewer the number of transistors connected in series in the existing ESD protection circuit, the better. However, in normal operation, the I/O outputs a certain amount of high voltage, and the VGH voltage cannot enter the transistor array in a full range due to the leakage current of the n-type transistors connected in series, and the ESD protection circuit also causes a problem of higher static power consumption due to continuous leakage. In the existing ESD circuit, the structural parameters of the device are difficult to optimize and select, and are limited by the principle defects of the circuit, and the existing ESD circuit is difficult to simultaneously consider the indexes of ESD protection effect, lower electric leakage, smaller circuit area, lower power consumption and the like no matter how the channel width and the length of the transistor are selected.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a first implementation of an ESD protection circuit provided in an embodiment of the present application, and as shown in fig. 2, the ESD protection circuit 10 provided in an embodiment of the present application includes a first power line 101, a second power line 102, a reference high voltage signal line 103, a reference low voltage signal line 104, a detection module 105, an amplifying module 106, and a discharging module 107.
The first power line 101 is provided with an I/O terminal P, and the first power line 101 is configured to provide a normal working high voltage VGH. The second power line 102 is used for providing a discharging voltage VSS. The reference high voltage signal line 103 is used to supply the reference high voltage VH. The reference low voltage signal line 104 is used to raise the reference low voltage VL.
The detection module 105 is electrically connected to the I/O terminal P, the second power line 102, and the amplifying module 106. The detection module 105 is configured to detect whether the ESD abnormal charge VGHH occurs at the I/O terminal P, and if the ESD abnormal charge VGHH occurs, transmit the ESD abnormal charge VGHH to the amplifying module 106.
The amplifying module 106 is electrically connected to the reference high voltage signal line 103, the reference low voltage signal line 104, the detecting module 105 and the discharging module 107. The amplifying module 106 is configured to amplify the ESD abnormal charge VGHH and transfer the amplified ESD abnormal charge VGHH to the discharging module 107.
The discharging module 107 is electrically connected to the first power line 101, the second power line 102, and the amplifying module 106. The discharging module 107 is configured to release the ESD abnormal charge VGHH of the I/O terminal P when the amplified ESD abnormal charge VGHH is received.
It should be noted that, the detection module 105 is adopted to sense that the ESD abnormal charge VGHH, such as an instantaneous high level pulse, appears on the I/O terminal P at a relatively high speed; then amplifying the ESD abnormal charge VGHH by the amplifying module 106; thereby rendering the discharge module 107 more fully conductive for better ESD protection. In addition, since the embodiments of the present application employ low temperature poly-oxide transistor technology, both n-type semiconductor transistors, such as metal oxide transistors, and p-type semiconductor transistors, such as low temperature poly-silicon transistors, are implemented. Therefore, the detection module 105 and the amplification module 106 with good performance can be realized, so that the discharge module 107 has smaller leakage charge in the normal working process, and can release the ESD abnormal charge VGHH at a relatively high corresponding speed when the ESD abnormal charge VGHH occurs, thereby protecting the I/O circuit and related circuits from damage of impact current and impact voltage.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a second implementation of the ESD protection circuit according to the embodiment of the present application. As shown in fig. 3, the detection module 105 includes a first resistive element 1051 and a second resistive element 1052. One end of the first resistive element 1051 is electrically connected to the I/O terminal P, and the other end of the first resistive element 1051 is connected to the first node a. One end of the second resistive element 1052 is electrically connected to the second power line VSS, and the other end of the second resistive element 1052 is electrically connected to the first node a.
The amplifying module 106 includes a first buffer amplifier 1061 and a second buffer amplifier 1062. The input end of the first buffer amplifier 1061 is electrically connected to the first node a, and the output end of the first buffer amplifier 1061 is electrically connected to the second node B. The input end of the second buffer amplifier 1062 is electrically connected to the second node B, and the output end of the second buffer amplifier 1062 is electrically connected to the third node C.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of a second implementation of the ESD protection circuit according to the embodiment of the present application. As shown in fig. 4, the first resistive element 1051 includes a first detection transistor T1. The second resistive element 1052 includes a second detection transistor T2. The gate of the first detection transistor T1 is electrically connected to the first node a, one of the source and the drain of the first detection transistor T1 is electrically connected to the I/O terminal P, and the other of the source and the drain of the first detection transistor T1 is electrically connected to the first node a. The gate of the second detection transistor T2 is electrically connected to the second power line VSS, one of the source and the drain of the second detection transistor T2 is electrically connected to the first node a, and the other of the source and the drain of the second detection transistor T2 is electrically connected to the second power line VSS.
The first buffer amplifier 1061 includes a first amplifying transistor T3 and a second amplifying transistor T4. The second buffer amplifier 1062 includes a third amplifying transistor T5 and a fourth amplifying transistor T6. The gate of the first amplifying transistor T3 is electrically connected to the first node a, one of the source and the drain of the first amplifying transistor T3 is electrically connected to the reference high voltage signal line 103, and the other of the source and the drain of the first amplifying transistor T3 is electrically connected to the second node B. The gate of the second amplifying transistor T4 is electrically connected to the second node B, one of the source and the drain of the second amplifying transistor T4 is connected to the reference high voltage signal line 103, and the other of the source and the drain of the second amplifying transistor T4 is electrically connected to the third node C. The gate of the third amplifying transistor T5 is electrically connected to the first node a, one of the source and the drain of the third amplifying transistor T5 is connected to the reference low voltage signal line 104, and the other of the source and the drain of the third amplifying transistor T5 is electrically connected to the second node B. The gate of the fourth amplifying transistor T6 is electrically connected to the second node B, one of the source and the drain of the fourth amplifying transistor T6 is connected to the reference low voltage signal line 104, and the other of the source and the drain of the fourth amplifying transistor T6 is electrically connected to the third node C.
Note that the amplifying module 106 includes not only the first buffer amplifier 1061 formed of the first amplifying transistor T3 and the second amplifying transistor T4, but also the second buffer amplifier 1062 formed of the third amplifying transistor T5 and the fourth amplifying transistor T6. The amplifying module 106 provided in this embodiment of the present application includes two stages of amplifying units, so that the voltage values of the normal working high voltage VGH, the reference high voltage VH, the reference low voltage VL, and the discharging voltage VSS need to be in a situation of sequentially decreasing, so that the amplifying function of the amplifying module 106 can be better implemented.
The discharging module 107 includes a first discharging transistor T7 and a second discharging transistor T8. The gate of the first discharge transistor T7 is electrically connected to the first power line VGH, one of the source and the drain of the first discharge transistor T7 is electrically connected to the first power line VGH, the other of the source and the drain of the first discharge transistor T7 is electrically connected to one of the source and the drain of the second discharge transistor T8, the other of the source and the drain of the second discharge transistor T8 is electrically connected to the second power line VSS, and the gate of the second discharge transistor T8 is electrically connected to the third node C.
Referring to fig. 5, fig. 5 is a schematic circuit conduction diagram of the ESD protection circuit provided in the embodiment of the present application in a normal operating state. As shown in fig. 5, when the ESD protection circuit is in a state, the voltage of the I/O terminal P is the normal operation high voltage VGH of the first power line 101. Since the first detection transistor T1 and the second detection transistor T2 are in the diode state of the reverse connection, they are in the high-resistance state, and the voltage value of the first node a is k×vgh+vss, where K is the ratio of the channel width of the first detection transistor T1 to the channel width of the second detection transistor T2. At this time, the first discharge transistor T7 is turned on, the third amplification transistor T5 is turned off, and the voltage of the second node B is the reference high level VH. Further, the second amplifying transistor T4 is turned off, the fourth amplifying transistor T6 is turned on, and the potential of the third node C is fixed at the reference low level VL by being pulled down. Thus, the second discharge transistor T8 of the discharge module 107 is turned off, and the discharge module 107 is in a non-operating state.
The first amplifying transistor T3 and the second amplifying transistor T4 are p-type transistors, and the third amplifying transistor T5 and the fourth amplifying transistor T6 are n-type transistors. The p-type transistor is turned on when the grid electrode is at a low level, and turned off when the grid electrode is at a high level; the n-type transistor is turned on when the gate is high, and turned off when the gate is low.
In the normal operation state, the first detection transistor T1 and the second detection transistor T2 are in the reverse-connected diode state, so that the first detection transistor T1 and the second detection transistor T2 are in the high-resistance state, and the device sizes and parameters of the first detection transistor T1 and the second detection transistor T2 need to be properly selected. Specifically, the channel width of the second detection transistor T2 is a ratio of the channel width of the first detection transistor T1 to 9 to 11. The channel width of the second detection transistor T2 is 9, 10 or 11 as the ratio of the channel width of the first detection transistor T1. The specific ratio of the channel width of the second detection transistor T2 to the channel width of the first detection transistor T1 is determined by the specific requirements of the ESD protection circuit 10.
In addition, from the above operation, it can be derived that each voltage should satisfy the following conditions: vgh+vss-VL<Vth n ，VH-(K*VGH+VSS)<|Vth p |，VL-VSS<Vth n . From the above formula, the defined formula for VL can be derived as: VGH+VSS-Vth n <VL<Vth n +VSS。
Wherein Vth n Is the threshold voltage of an n-type transistor, vth p Is the threshold voltage of the p-type transistor.
Referring to fig. 6, fig. 6 is a schematic circuit conduction diagram of the ESD protection circuit provided in the embodiment of the present application in a high voltage protection state. As shown in fig. 6, when the ESD protection circuit is in the high voltage protection state, the voltage of the I/O terminal P is the voltage VGHH of the ESD abnormal charge. Since the first detection transistor T1 and the second detection transistor T2 are in the diode state of the reverse connection, they are in the high-resistance state, and the voltage value of the first node a is k×vghh+vss, where K is the ratio of the channel width of the first detection transistor T1 to the channel width of the second detection transistor T2. At this time, the first discharge transistor T7 is turned off and the third amplification transistor T5 is turned on, and the voltage of the second node B is the reference low level VL. Further, the second amplifying transistor T4 is turned on, the fourth amplifying transistor T6 is turned off, and the potential of the third node C is pulled up and fixed at the reference high level VH. Thus, the second discharge transistor T8 of the discharge module 107 is turned on, and the discharge module 107 is in an operating state, so as to release the ESD abnormal charge at the I/O terminal P more quickly.
From the above operation, it can be seen that the following conditions should be satisfied for each voltage: vghh+vss-VL>Vth n ，VH-(K*VGHH+VSS)<|Vth p |，VL-VSS>Vth n . From the above formula, the conditions for triggering protection of the ESD protection circuit 10 provided in the embodiments of the present application can be deduced as follows: VGHH+VSS-VL>(Vth n +VL-VSS)/K。
Wherein Vth n Is the threshold voltage of an n-type transistor, vth p Is the threshold voltage of the p-type transistor.
The ESD protection circuit 10 provided in the embodiment of the present application can better solve the contradiction in the existing ESD protection circuit, overcome the principle defect of the existing ESD protection circuit architecture, and better give consideration to the indexes of ESD protection effect, lower leakage, smaller circuit area, lower power consumption, and the like. The ESD protection circuit 10 provided in the embodiment of the present application can effectively reduce leakage power consumption of the ESD part in the normal working process by using the characteristic of small leakage current of the metal oxide transistor; meanwhile, the advantage of high response speed of the low-temperature polysilicon transistor is exerted, the low-temperature polysilicon transistor can rapidly respond after the occurrence of ESD abnormal charge, and the possible loss caused by the ESD abnormal charge is restrained.
The embodiment of the application also provides a display device. Referring to fig. 7, fig. 7 is a schematic structural diagram of a display device according to an embodiment of the disclosure. As shown in fig. 7, the display device 100 provided in the embodiment of the present application includes a display panel 100a and a driving chip 100b connected to the display panel 100 a. The ESD protection circuit 10 is provided on the driving chip 100b. The ESD protection circuit 10 may be specifically referred to the above description of the ESD protection circuit, and will not be described herein.
The foregoing has described in detail an ESD protection circuit and a display device provided by embodiments of the present application, and specific examples have been applied herein to illustrate the principles and embodiments of the present application, where the foregoing examples are provided to assist in understanding the methods of the present application and their core ideas; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.
Claims (9)
1. An ESD protection circuit is characterized by comprising a first power line, a second power line, a reference high-voltage signal line, a reference low-voltage signal line, a detection module, an amplification module and a discharge module; wherein,,
the first power line is provided with an I/O end, the first power line is used for providing normal working high voltage, the second power line is used for providing discharge voltage, the reference high voltage signal line is used for providing reference high voltage, and the reference low voltage signal line is used for providing reference low voltage;
the detection module is electrically connected with the I/O end, the second power line and the amplifying module,
the detection module is used for detecting whether the I/O terminal generates ESD abnormal charge or not, and if the ESD abnormal charge is generated, the ESD abnormal charge is transmitted to the amplifying module;
the amplifying module is electrically connected with the reference high-voltage signal line, the reference low-voltage signal line, the detecting module and the discharging module, and is used for amplifying the ESD abnormal charge and transmitting the amplified ESD abnormal charge to the discharging module;
the discharging module is electrically connected to the first power line, the second power line and the amplifying module, and is used for releasing the ESD abnormal charge of the I/O terminal when the amplified ESD abnormal charge is received;
the discharging module comprises a first discharging transistor and a second discharging transistor, wherein a grid electrode of the first discharging transistor is electrically connected to the first power line, one of a source electrode and a drain electrode of the first discharging transistor is electrically connected to the first power line, the other of the source electrode and the drain electrode of the first discharging transistor is electrically connected to one of the source electrode and the drain electrode of the second discharging transistor, the other of the source electrode and the drain electrode of the second discharging transistor is electrically connected to the second power line, and a grid electrode of the second discharging transistor is electrically connected to an output end of the amplifying module.
2. The ESD protection circuit of claim 1, wherein the detection module comprises a first resistive element and a second resistive element, wherein one end of the first resistive element is electrically connected to the I/O terminal, the other end of the first resistive element is connected to a first node, one end of the second resistive element is electrically connected to the second power line, and the other end of the second resistive element is electrically connected to the first node.
3. The ESD protection circuit of claim 2 wherein the first resistive element comprises a first detection transistor, the second resistive element comprises a second detection transistor, the gate of the first detection transistor is electrically connected to the first node, one of the source and the drain of the first detection transistor is electrically connected to the I/O terminal, the other of the source and the drain of the first detection transistor is electrically connected to the first node, the gate of the second detection transistor is electrically connected to the second power line, one of the source and the drain of the second detection transistor is electrically connected to the first node, and the other of the source and the drain of the second detection transistor is electrically connected to the second power line.
4. The ESD protection circuit of claim 3 wherein the channel width of the second detection transistor is a ratio of the channel width of the first detection transistor from 9 to 11.
5. The ESD protection circuit of claim 2, wherein the amplification module comprises a first buffer amplifier and a second buffer amplifier, wherein an input of the first buffer amplifier is electrically connected to the first node, an output of the first buffer amplifier is electrically connected to the second node, an input of the second buffer amplifier is electrically connected to the second node, and an output of the second buffer amplifier is electrically connected to the third node.
6. The ESD protection circuit of claim 5 wherein the first buffer amplifier comprises a first amplifier transistor and a second amplifier transistor, the second buffer amplifier comprises a third amplifier transistor and a fourth amplifier transistor, the gate of the first amplifier transistor is electrically connected to the first node, one of the source and the drain of the first amplifier transistor is electrically connected to the reference high voltage signal line, the other of the source and the drain of the first amplifier transistor is electrically connected to a second node, the gate of the second amplifier transistor is electrically connected to the second node, one of the source and the drain of the second amplifier transistor is connected to the reference high voltage signal line, the other of the source and the drain of the second amplifier transistor is electrically connected to a third node, the gate of the third amplifier transistor is electrically connected to the first node, one of the source and the drain of the third amplifier transistor is connected to the low voltage signal line, the other of the source and the drain of the third amplifier transistor is connected to the second node, the other of the source and the drain of the second amplifier transistor is connected to the third node, the other of the source and the drain of the third amplifier transistor is electrically connected to the third node.
7. The ESD protection circuit of claim 6, wherein the first and second amplifying transistors are p-type transistors and the third and fourth amplifying transistors are n-type transistors.
8. The ESD protection circuit of claim 1, wherein the voltage values of the normal operation high voltage, the reference low voltage, and the discharge voltage decrease in order.
9. The display device is characterized by comprising a display panel and a driving chip connected with the display panel; wherein the drive chip is provided with an ESD protection circuit as claimed in any one of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210328429.8A CN114582282B (en) | 2022-03-30 | 2022-03-30 | ESD protection circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210328429.8A CN114582282B (en) | 2022-03-30 | 2022-03-30 | ESD protection circuit and display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114582282A CN114582282A (en) | 2022-06-03 |
| CN114582282B true CN114582282B (en) | 2023-07-25 |
Family
ID=81782648
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210328429.8A Active CN114582282B (en) | 2022-03-30 | 2022-03-30 | ESD protection circuit and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114582282B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6274908B1 (en) * | 1997-10-09 | 2001-08-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having input-output protection circuit |
| US6369998B1 (en) * | 1999-04-27 | 2002-04-09 | Compaq Information Technologies Group, L.P. | Electrostatic discharge protection clamp for nominal-voltage power supply or I/O with high-voltage reference |
| JP2005156703A (en) * | 2003-11-21 | 2005-06-16 | Seiko Epson Corp | Electrostatic protection circuit for electronic device, electrostatic protection circuit for electro-optical device, and electronic apparatus |
| CN1748237A (en) * | 2003-02-14 | 2006-03-15 | 皇家飞利浦电子股份有限公司 | Electronic device with electrostatic discharge protection circuitry |
| KR20070070965A (en) * | 2005-12-29 | 2007-07-04 | 주식회사 하이닉스반도체 | Electrostatic Discharge Protection Circuit for Semiconductor Devices |
| CN101617238A (en) * | 2008-02-20 | 2009-12-30 | 惠瑞捷（新加坡）私人有限公司 | Detect system, the method and computer program of electrostatic discharge event |
| CN101783343A (en) * | 2008-12-26 | 2010-07-21 | 世界先进积体电路股份有限公司 | Electrostatic discharge protection circuit and integrated circuit |
| CN102217177A (en) * | 2008-11-13 | 2011-10-12 | 莫斯科技株式会社 | Magnetic energy regeneration switch provided with protection circuit |
| CN104979814A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protecting circuit |
| CN107026434A (en) * | 2016-01-29 | 2017-08-08 | 联发科技股份有限公司 | Electrostatic discharge protection circuit and method |
| CN114094560A (en) * | 2021-11-18 | 2022-02-25 | 世邦通信股份有限公司 | ESD protection system, device and manufacturing method thereof |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW518736B (en) * | 2001-09-06 | 2003-01-21 | Faraday Tech Corp | Gate-driven or gate-coupled electrostatic discharge protection circuit |
| US7027276B2 (en) * | 2004-04-21 | 2006-04-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | High voltage ESD protection circuit with low voltage transistors |
| KR100898584B1 (en) * | 2007-09-10 | 2009-05-20 | 주식회사 하이닉스반도체 | Electrostatic discharge circuit |
| CN101442046B (en) * | 2007-11-23 | 2011-05-04 | 上海华虹Nec电子有限公司 | Dynamic detection electrostatic protection circuit structure |
| JP2011130564A (en) * | 2009-12-17 | 2011-06-30 | Hitachi Ltd | Apparatus and method for protecting power semiconductor switch element |
| CN104347622A (en) * | 2014-09-11 | 2015-02-11 | 北京大学 | Direct current triggering power supply clamp ESD (electronic static discharge) protection circuit |
| CN104283201B (en) * | 2014-09-11 | 2017-02-15 | 北京大学 | Input stage esd protection circuit |
| US9893517B2 (en) * | 2014-12-15 | 2018-02-13 | Arm Limited | Electrostatic discharge protection circuitry |
| CN107579064B (en) * | 2017-08-31 | 2024-03-26 | 广东工业大学 | Stacked electrostatic discharge protection circuit |
| CN207303993U (en) * | 2017-10-24 | 2018-05-01 | 佛山市顺德区美的电热电器制造有限公司 | Overcurrent-overvoltage protecting circuit, induction wireless power supply system and cooking apparatus |
| CN108565848A (en) * | 2018-05-26 | 2018-09-21 | 丹阳恒芯电子有限公司 | A kind of electrostatic discharge protective circuit in Internet of Things |
| CN108512210A (en) * | 2018-05-26 | 2018-09-07 | 丹阳恒芯电子有限公司 | A kind of electrostatic discharge protective circuit of input/output port |
| CN211556863U (en) * | 2020-03-10 | 2020-09-22 | 华域视觉科技(上海)有限公司 | Short-circuit protection circuit and device for constant-current driving module of car lamp and car |
| CN112086946B (en) * | 2020-08-13 | 2024-03-19 | 珠海亿智电子科技有限公司 | High voltage resistant clamp circuit with alternating current detection and direct current detection |
-
2022
- 2022-03-30 CN CN202210328429.8A patent/CN114582282B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6274908B1 (en) * | 1997-10-09 | 2001-08-14 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having input-output protection circuit |
| US6369998B1 (en) * | 1999-04-27 | 2002-04-09 | Compaq Information Technologies Group, L.P. | Electrostatic discharge protection clamp for nominal-voltage power supply or I/O with high-voltage reference |
| CN1748237A (en) * | 2003-02-14 | 2006-03-15 | 皇家飞利浦电子股份有限公司 | Electronic device with electrostatic discharge protection circuitry |
| JP2005156703A (en) * | 2003-11-21 | 2005-06-16 | Seiko Epson Corp | Electrostatic protection circuit for electronic device, electrostatic protection circuit for electro-optical device, and electronic apparatus |
| KR20070070965A (en) * | 2005-12-29 | 2007-07-04 | 주식회사 하이닉스반도체 | Electrostatic Discharge Protection Circuit for Semiconductor Devices |
| CN101617238A (en) * | 2008-02-20 | 2009-12-30 | 惠瑞捷（新加坡）私人有限公司 | Detect system, the method and computer program of electrostatic discharge event |
| CN102217177A (en) * | 2008-11-13 | 2011-10-12 | 莫斯科技株式会社 | Magnetic energy regeneration switch provided with protection circuit |
| CN101783343A (en) * | 2008-12-26 | 2010-07-21 | 世界先进积体电路股份有限公司 | Electrostatic discharge protection circuit and integrated circuit |
| CN104979814A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protecting circuit |
| CN107026434A (en) * | 2016-01-29 | 2017-08-08 | 联发科技股份有限公司 | Electrostatic discharge protection circuit and method |
| CN114094560A (en) * | 2021-11-18 | 2022-02-25 | 世邦通信股份有限公司 | ESD protection system, device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114582282A (en) | 2022-06-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US12002415B2 (en) | Display panel and display device | |
| US9246329B2 (en) | Electrostatic discharge protection circuit and display device including the same | |
| CN105226100B (en) | The thin film transistor (TFT) of display device | |
| WO2021139708A1 (en) | Shift register and control method therefor, gate driving circuit, and display panel | |
| WO2013104222A1 (en) | Electrostatic discharge protection circuit and working method therefor | |
| CN111600594B (en) | Level conversion circuit with reverse connection protection | |
| CN113764437B (en) | A display panel and a method for manufacturing the display panel | |
| CN103560782A (en) | NAND gate circuit, displayer backboard and displayer | |
| CN114582282B (en) | ESD protection circuit and display device | |
| CN100353394C (en) | Pixel circuit of display | |
| US7852976B2 (en) | Bidirectional controlling device for increasing resistance of elements on voltage stress | |
| US20240428716A1 (en) | Display substrate and display device | |
| CN107221283B (en) | Gate drive circuit | |
| CN106597768A (en) | Electrostatic discharge protection circuit and liquid crystal display panel | |
| US20090213057A1 (en) | Display device | |
| WO2020252913A1 (en) | Pixel drive circuit and display panel | |
| CN111785227A (en) | Gate Drive Circuits and Gate Drivers | |
| Zhou et al. | P‐1.10: Robust Amorphous IGZO Integrated Gate Driver Circuit for Ultra Large TFT‐LCD Applications | |
| US12230340B2 (en) | Shift register unit, gate driving circuit and display device | |
| EP4354419A1 (en) | Compensation circuit, driving method and display panel | |
| CN110491874B (en) | Electrostatic protection circuit and panel | |
| WO2022111089A1 (en) | Level conversion circuit, display panel drive circuit, and display apparatus | |
| CN201252102Y (en) | ESD protective structure for output buffer of SOI/CMOS integrated circuit | |
| TWI658667B (en) | Driving circuit | |
| KR20090090512A (en) | Level shift circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |