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CN114582282A - ESD protection circuit and display device - Google Patents

ESD protection circuit and display device Download PDF

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Publication number
CN114582282A
CN114582282A CN202210328429.8A CN202210328429A CN114582282A CN 114582282 A CN114582282 A CN 114582282A CN 202210328429 A CN202210328429 A CN 202210328429A CN 114582282 A CN114582282 A CN 114582282A
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Prior art keywords
transistor
electrically connected
node
module
esd
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CN202210328429.8A
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CN114582282B (en
Inventor
张毅先
胡俊艳
陈诚
戴超
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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Wuhan China Star Optoelectronics Semiconductor Display Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K9/00—Screening of apparatus or components against electric or magnetic fields
    • H05K9/0073—Shielding materials
    • H05K9/0079—Electrostatic discharge protection, e.g. ESD treated surface for rapid dissipation of charges
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

The ESD protection circuit and the display device provided by the embodiment of the application comprise a detection module, an amplification module and a discharge module, wherein the detection module can sense the ESD abnormal charge on the I/O end at a higher speed; then, the ESD abnormal charges are amplified through the amplifying module, so that the discharging module is conducted more fully, and a better ESD protection effect is achieved. According to the embodiment of the application, a low-temperature polycrystalline oxide transistor technology is adopted, a detection module and an amplification module with good performance can be realized, the leakage charge of a discharge module in the normal working process is small, and the ESD abnormal charge can be released at a high corresponding speed when the ESD abnormal charge occurs, so that an I/O circuit and related circuits of the I/O circuit are protected, and the I/O circuit and related circuits are not damaged by impact current and impact voltage.

Description

ESD protection circuit and display device
Technical Field
The application relates to the technical field of display, in particular to an ESD protection circuit and a display device.
Background
Currently, the organic light emitting diode display of the active matrix is widely applied to the middle and small-sized display panels, and is gradually becoming the mainstream of the display technology. In particular, a low temperature poly-silicon and metal oxide based hybrid transistor technology, i.e., a low temperature poly-oxide technology, has begun to become a backlight technology for high-end displays. The low-temperature polycrystalline oxide technology has the characteristics of high mobility, high driving capability and low leakage current, and can obviously reduce the leakage current and the electric charge of the internal nodes of the organic light emitting diode pixels of the active matrix, thereby obviously reducing the display driving power consumption in low-frame occasions.
However, most of the related art low temperature poly-oxide transistor technology has been used to improve the performance of the active matrix organic light emitting diode pixel circuit, and there is little research on the implementation of low temperature poly-oxide transistor technology to construct a high performance peripheral driving circuit, especially in ESD protection circuit.
The conventional ESD circuit not only needs to have a strong protection effect, but also needs to ensure that the leakage current is low in the normal working process of the I/O terminal. However, there is a contradiction between the two, and from the viewpoint of improving the ESD protection effect, the number of TFTs connected in series in the conventional ESD circuit is as small as possible, but this causes a certain amount of high voltage to be output from the I/O terminal during normal operation. Therefore, in the conventional ESD circuit, since the device structure parameters are difficult to be optimally selected and limited by the principle defects of the circuit, no matter how the channel width and length of the TFT are selected, the conventional ESD circuit is difficult to simultaneously take into account the ESD protection effect, the low leakage current, the small circuit area, the low power consumption, and other indexes.
Therefore, how to provide an ESD circuit that can achieve the ESD protection effect, lower leakage, smaller circuit area, lower power consumption, and other indicators is a difficult problem for the existing panel manufacturers to overcome.
Disclosure of Invention
An object of the embodiments of the present application is to provide an ESD circuit and a display device, which can solve the technical problem that the conventional ESD circuit is difficult to simultaneously consider the ESD protection effect, lower leakage, smaller circuit area, lower power consumption, and other indicators.
The embodiment of the application provides an ESD circuit, which comprises a first power line, a second power line, a reference high-voltage signal line, a reference low-voltage signal line, a detection module, an amplification module and a discharge module; wherein,
the first power line is provided with an I/O (input/output) end, the first power line is used for providing normal working high voltage, the second power line is used for providing discharge voltage, the reference high-voltage signal line is used for providing reference high voltage, and the reference low-voltage signal line is used for improving reference low voltage;
the detection module is electrically connected to the I/O terminal, the second power line and the amplification module, and is used for detecting whether ESD abnormal charges occur at the I/O terminal, and if the ESD abnormal charges occur, the ESD abnormal charges are transmitted to the amplification module;
the amplifying module is electrically connected to the reference high-voltage signal line, the reference low-voltage signal line, the detecting module and the discharging module, and is used for amplifying the ESD abnormal charges and transmitting the amplified ESD abnormal charges to the discharging module;
the discharge module is electrically connected to the first power line, the second power line and the amplification module, and the discharge module is configured to release the ESD abnormal charge of the I/O terminal when receiving the amplified ESD abnormal charge.
In the ESD circuit described herein, the detection module includes a first resistive element and a second resistive element, one end of the first resistive element is electrically connected to the I/O terminal, the other end of the first resistive element is connected to the first node, one end of the second resistive element is electrically connected to the second power line, and the other end of the second resistive element is electrically connected to the first node.
In the ESD circuit of the present application, the first resistive element includes a first detection transistor, the second resistive element includes a second detection transistor, a gate of the first detection transistor is electrically connected to the first node, one of a source and a drain of the first detection transistor is electrically connected to the I/O terminal, the other of the source and the drain of the first detection transistor is electrically connected to the first node, a gate of the second detection transistor is electrically connected to the second power line, the one of the source and the drain of the second detection transistor is electrically connected to the first node, and the other of the source and the drain of the second detection transistor is electrically connected to the second power line.
In the ESD circuit of the present application, a ratio of a channel width of the second detection transistor to a channel width of the first detection transistor is 9 to 11.
In the ESD circuit of the present application, the amplifying module includes a first buffer amplifier and a second buffer amplifier, an input terminal of the first buffer amplifier is electrically connected to the first node, an output terminal of the first buffer amplifier is electrically connected to the second node, an input terminal of the second buffer amplifier is electrically connected to the second node, and an output terminal of the second buffer amplifier is electrically connected to the third node.
In the ESD circuit of the present application, the first buffer amplifier includes a first amplifying transistor and a second amplifying transistor, the second buffer amplifier includes a third amplifying transistor and a fourth amplifying transistor, a gate of the first amplifying transistor is electrically connected to the first node, one of a source and a drain of the first amplifying transistor is electrically connected to the reference high voltage signal line, the other of the source and the drain of the first amplifying transistor is electrically connected to a second node, a gate of the second amplifying transistor is electrically connected to the second node, one of the source and the drain of the second amplifying transistor is connected to the reference high voltage signal line, the other of the source and the drain of the second amplifying transistor is electrically connected to a third node, and a gate of the third amplifying transistor is electrically connected to the first node, one of a source and a drain of the third amplifying transistor is connected to the reference low-voltage signal line, the other of the source and the drain of the third amplifying transistor is electrically connected to the second node, a gate of the fourth amplifying transistor is electrically connected to the second node, one of the source and the drain of the fourth amplifying transistor is connected to the reference low-voltage signal line, and the other of the source and the drain of the fourth amplifying transistor is electrically connected to the third node.
In the ESD circuit described herein, the first amplification transistor and the second amplification transistor are n-type transistors, and the third amplification transistor and the fourth amplification transistor are p-type transistors.
In the ESD circuit of the present application, the discharge module includes a first discharge transistor and a second discharge transistor, a gate of the first discharge transistor is electrically connected to the first power line, one of a source and a drain of the first discharge transistor is electrically connected to the first power line, the other of the source and the drain of the first discharge transistor is electrically connected to one of a source and a drain of the second discharge transistor, the other of the source and the drain of the second discharge transistor is electrically connected to the second power line, and a gate of the second discharge transistor is electrically connected to the third node.
In the ESD circuit of the present application, the voltage values of the normal operation high voltage, the reference low voltage, and the discharge voltage are sequentially reduced.
The embodiment of the application also provides a display device, which comprises a display panel and a driving chip connected with the display panel; the ESD protection circuit is arranged on the driving chip.
In the ESD protection circuit and the display device provided in the embodiments of the present application, a low temperature poly-oxide transistor technology is adopted, wherein the ESD protection circuit includes a detection module, an amplification module, and a discharge module, and the detection module can sense the occurrence of ESD abnormal charges, such as an instantaneous high level pulse, on the I/O terminal at a high speed; then, the ESD abnormal charges are amplified through the amplifying module, so that the discharging module is conducted more fully, and a better ESD protection effect is achieved. The embodiment of the application adopts the low-temperature polycrystalline oxide transistor technology, so that an n-type semiconductor transistor, such as a metal oxide transistor, and a p-type semiconductor transistor, such as a low-temperature polycrystalline silicon transistor, are realized, a detection module and an amplification module with good performance can be realized, the leakage charge of a discharge module in the normal working process is small, and the ESD abnormal charge can be released at a fast corresponding speed when the ESD abnormal charge occurs, so that an I/O line and related circuits are protected from being damaged by impact current and impact voltage.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a circuit diagram of an ESD protection circuit provided in the prior art.
Fig. 2 is a schematic structural diagram of a first implementation manner of an ESD protection circuit according to an embodiment of the present application.
Fig. 3 is a schematic structural diagram of a second implementation manner of the ESD protection circuit according to the embodiment of the present application.
Fig. 4 is a circuit diagram of a second implementation manner of an ESD protection circuit according to an embodiment of the present application.
Fig. 5 is a circuit schematic diagram of an ESD protection circuit in a normal operating state according to an embodiment of the present application.
Fig. 6 is a schematic circuit diagram illustrating an ESD protection circuit in a high-voltage protection state according to an embodiment of the present disclosure.
Fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics, and since the source and drain of the transistors used herein are symmetrical, the source and drain may be interchanged. In the embodiment of the present application, to distinguish two poles of a transistor except for a gate, one of the two poles is referred to as a source, and the other pole is referred to as a drain. The form in the drawing provides that the middle end of the switching transistor is a grid, the signal input end is a source, and the output end is a drain.
Referring to fig. 1, fig. 1 is a circuit diagram of an ESD protection circuit provided in the prior art. As shown in fig. 1, the ESD protection circuit of the prior art is composed of three n-type transistors, such as metal oxide transistors, connected in series.
In order to improve the protection effect of the ESD protection circuit, the number of transistors connected in series in the conventional ESD protection circuit is preferably smaller. However, during normal operation, the I/O outputs a certain amount of high voltage, and due to the leakage current of the n-type transistors connected in series, the VGH voltage cannot enter the transistor array to the full extent, and the ESD protection circuit also has a problem of high static power consumption due to continuous leakage. In the existing ESD circuit, the device structure parameters are difficult to be selected optimally, and limited by the principle defects of the circuit, and no matter how the channel width and length of the transistor are selected, the existing ESD circuit is difficult to simultaneously give consideration to the indexes of ESD protection effect, lower electric leakage, smaller circuit area, lower power consumption and the like.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a first implementation of an ESD protection circuit according to an embodiment of the present disclosure, and as shown in fig. 2, an ESD protection circuit 10 according to an embodiment of the present disclosure includes a first power line 101, a second power line 102, a reference high-voltage signal line 103, a reference low-voltage signal line 104, a detection module 105, an amplification module 106, and a discharge module 107.
The first power line 101 is provided with an I/O terminal P, and the first power line 101 is used for providing a normal operating high voltage VGH. The second power line 102 is used to provide the discharging voltage VSS. The reference high voltage signal line 103 is used to supply a reference high voltage VH. The reference low voltage signal line 104 is used to raise the reference low voltage VL.
The detecting module 105 is electrically connected to the I/O terminal P, the second power line 102 and the amplifying module 106. The detecting module 105 is used for detecting whether the ESD abnormal charge VGHH appears on the I/O terminal P, and if the ESD abnormal charge VGHH appears, the ESD abnormal charge VGHH is transmitted to the amplifying module 106.
The amplifying module 106 is electrically connected to the reference high-voltage signal line 103, the reference low-voltage signal line 104, the detecting module 105 and the discharging module 107. The amplifying module 106 is used for amplifying the ESD abnormal charge VGHH and transmitting the amplified ESD abnormal charge VGHH to the discharging module 107.
The discharging module 107 is electrically connected to the first power line 101, the second power line 102 and the amplifying module 106. The discharging module 107 is configured to discharge the ESD abnormal charge VGHH of the I/O terminal P when receiving the amplified ESD abnormal charge VGHH.
It should be noted that the detection module 105 can sense the ESD abnormal charge VGHH, such as an instantaneous high-level pulse, appearing on the I/O terminal P at a higher speed; the ESD abnormal charge VGHH is then amplified by the amplification module 106; thereby making the discharge module 107 more sufficiently conductive to achieve a better ESD protection effect. In addition, since the embodiments of the present application adopt the low temperature poly-oxide transistor technology, not only n-type semiconductor transistors, such as metal oxide transistors, but also p-type semiconductor transistors, such as low temperature poly-silicon transistors, are realized. Therefore, the detection module 105 and the amplification module 106 with good performance can be realized, so that the discharge module 107 has small leakage charge during normal operation, and can release the ESD abnormal charge VGHH at a fast corresponding speed when the ESD abnormal charge VGHH occurs, thereby protecting the I/O circuit and the related circuits from being damaged by the impact current and the impact voltage.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a second implementation of an ESD protection circuit according to an embodiment of the present disclosure. As shown in fig. 3, the detection module 105 includes a first resistive element 1051 and a second resistive element 1052. One end of the first resistive element 1051 is electrically connected to the I/O terminal P, and the other end of the first resistive element 1051 is connected to the first node a. One end of the second resistive element 1052 is electrically connected to the second power line VSS, and the other end of the second resistive element 1052 is electrically connected to the first node a.
The amplifying module 106 includes a first buffer amplifier 1061 and a second buffer amplifier 1062. The input terminal of the first buffer amplifier 1061 is electrically connected to the first node a, and the output terminal of the first buffer amplifier 1061 is electrically connected to the second node B. The input terminal of the second buffer amplifier 1062 is electrically connected to the second node B, and the output terminal of the second buffer amplifier 1062 is electrically connected to the third node C.
Referring to fig. 4, fig. 4 is a circuit diagram illustrating a second implementation manner of an ESD protection circuit according to an embodiment of the present disclosure. As shown in fig. 4, the first resistive element 1051 includes a first detection transistor T1. The second resistive element 1052 includes a second detection transistor T2. The gate of the first detection transistor T1 is electrically connected to the first node a, one of the source and the drain of the first detection transistor T1 is electrically connected to the I/O terminal P, and the other of the source and the drain of the first detection transistor T1 is electrically connected to the first node a. The gate of the second detecting transistor T2 is electrically connected to the second power line VSS, one of the source and the drain of the second detecting transistor T2 is electrically connected to the first node a, and the other of the source and the drain of the second detecting transistor T2 is electrically connected to the second power line VSS.
The first buffer amplifier 1061 includes a first amplifying transistor T3 and a second amplifying transistor T4. The second buffer amplifier 1062 includes a third amplifying transistor T5 and a fourth amplifying transistor T6. The gate of the first amplifying transistor T3 is electrically connected to the first node a, one of the source and the drain of the first amplifying transistor T3 is electrically connected to the reference high voltage signal line 103, and the other of the source and the drain of the first amplifying transistor T3 is electrically connected to the second node B. The gate of the second amplifying transistor T4 is electrically connected to the second node B, one of the source and the drain of the second amplifying transistor T4 is connected to the reference high voltage signal line 103, and the other of the source and the drain of the second amplifying transistor T4 is electrically connected to the third node C. The gate of the third amplifying transistor T5 is electrically connected to the first node a, one of the source and the drain of the third amplifying transistor T5 is connected to the reference low voltage signal line 104, and the other of the source and the drain of the third amplifying transistor T5 is electrically connected to the second node B. The gate of the fourth amplifying transistor T6 is electrically connected to the second node B, one of the source and the drain of the fourth amplifying transistor T6 is connected to the reference low voltage signal line 104, and the other of the source and the drain of the fourth amplifying transistor is electrically connected to the third node C.
It should be noted that the amplifying module 106 includes not only the first buffer amplifier 1061 formed by the first amplifying transistor T3 and the second amplifying transistor T4, but also a second buffer amplifier 1062 formed by the third amplifying transistor T5 and the fourth amplifying transistor T6. The amplifying module 106 provided in the embodiment of the application includes two stages of amplifying units, and therefore, the voltage values of the normal operating high voltage VGH, the reference high voltage VH, the reference low voltage VL, and the discharging voltage VSS need to be sequentially reduced, so that the amplifying function of the amplifying module 106 can be better realized.
The discharge module 107 includes a first discharge transistor T7 and a second discharge transistor T8. The gate of the first discharge transistor T7 is electrically connected to the first power line VGH, one of the source and the drain of the first discharge transistor T7 is electrically connected to the first power line VGH, the other of the source and the drain of the first discharge transistor T7 is electrically connected to one of the source and the drain of the second discharge transistor T8, the other of the source and the drain of the second discharge transistor T8 is electrically connected to the second power line VSS, and the gate of the second discharge transistor T8 is electrically connected to the third node C.
Referring to fig. 5, fig. 5 is a circuit conducting schematic diagram of the ESD protection circuit in a normal operating state according to the embodiment of the present disclosure. As shown in fig. 5, when the ESD protection circuit is in a state, the voltage of the I/O terminal P is the normal operation high voltage VGH of the first power line 101. Since the first detecting transistor T1 and the second detecting transistor T2 are in the reverse diode state, both are in the high impedance state, and the voltage value of the first node a is K × VGH + VSS, where K is the ratio of the channel width of the first detecting transistor T1 to the channel width of the second detecting transistor T2. At this time, the first discharge transistor T7 is turned on, the third amplification transistor T5 is turned off, and the voltage of the second node B is the reference high level VH. Further, the second amplifying transistor T4 is turned off, the fourth amplifying transistor T6 is turned on, and the potential of the third node C is pulled down to be fixed at the reference low level VL. Accordingly, the second discharge transistor T8 of the discharge module 107 is turned off, and the discharge module 107 is in an inactive state.
The first and second amplifying transistors T3 and T4 are p-type transistors, and the third and fourth amplifying transistors T5 and T6 are n-type transistors. The p-type transistor is switched on when the grid is at a low level and switched off when the grid is at a high level; the n-type transistor is turned on when the gate is at a high level and turned off when the gate is at a low level.
It should be noted that, in the normal operation state, since the first detecting transistor T1 and the second detecting transistor T2 are in the reverse diode state, the first detecting transistor T1 and the second detecting transistor T2 are both in the high-impedance state, and therefore the device size and parameters of the first detecting transistor T1 and the second detecting transistor T2 need to be selected appropriately. Specifically, the channel width of the second detection transistor T2 is a ratio of the channel width of the first detection transistor T1 to 9 to 11. The channel width of the second detection transistor T2 is a ratio of the channel width of the first detection transistor T1 to 9, 10, or 11. The channel width of the second detection transistor T2 is a specific ratio of the channel width of the first detection transistor T1 determined by the specific requirements of the ESD protection circuit 10.
In addition, from the above working process, it can be concluded that each voltage should satisfy the following conditions: k VGH + VSS-VL<Vthn，VH-(K*VGH+VSS)<|Vthp|，VL-VSS<Vthn. The limiting formula for VL can be derived from the above formula: k VGH + VSS-Vthn<VL<Vthn+VSS。
Wherein, VthnIs the threshold voltage, Vth, of an n-type transistorpIs the threshold voltage of the p-type transistor.
Referring to fig. 6, fig. 6 is a circuit conducting schematic diagram of the ESD protection circuit in a high-voltage protection state according to the embodiment of the present disclosure. As shown in fig. 6, when the ESD protection circuit is in the high-voltage protection state, the voltage of the I/O terminal P is the voltage VGHH of the ESD abnormal charge. Since the first detecting transistor T1 and the second detecting transistor T2 are in the reverse diode state, both are in the high impedance state, and the voltage value of the first node a is K × VGHH + VSS, where K is the ratio of the channel width of the first detecting transistor T1 to the channel width of the second detecting transistor T2. At this time, the first discharging transistor T7 is turned off, the third amplifying transistor T5 is turned on, and the voltage of the second node B is the reference low level VL. Further, the second amplification transistor T4 is turned on, the fourth amplification transistor T6 is turned off, and the potential of the third node C is pulled up and fixed at the reference high level VH. Accordingly, the second discharge transistor T8 of the discharge module 107 is turned on, and the discharge module 107 is in an operating state, thereby rapidly discharging the ESD abnormal charge at the I/O terminal P.
Wherein, according to the working process, the following conditions can be met for each voltage: k VGHH + VSS-VL>Vthn，VH-(K*VGHH+VSS)<|Vthp|，VL-VSS>Vthn. From the above formula, it can be derived that the conditions for triggering protection of the ESD protection circuit 10 provided in the embodiment of the present application are: VGHH + VSS-VL>(Vthn+VL-VSS)/K。
Wherein, VthnThreshold voltage of n-type transistor, VthpIs the threshold voltage of the p-type transistor.
The ESD protection circuit 10 provided in the embodiment of the present application can better solve the contradiction in the existing ESD protection circuit, overcome the principle defect of the existing ESD protection circuit architecture, and better consider the ESD protection effect, the lower leakage current, the smaller circuit area, the lower power consumption, and other indicators. The ESD protection circuit 10 provided in the embodiment of the present application utilizes the characteristic of small leakage current of the metal oxide transistor, and can effectively reduce the leakage power consumption of the ESD part in the normal working process; meanwhile, the advantage of high response speed of the low-temperature polysilicon transistor is exerted, the response is fast after ESD abnormal charges occur, and possible loss caused by the ESD abnormal charges is restrained.
The embodiment of the application also provides a display device. Referring to fig. 7, fig. 7 is a schematic structural diagram of a display device according to an embodiment of the present disclosure. As shown in fig. 7, the display device 100 provided in the embodiment of the present application includes a display panel 100a and a driving chip 100b connected to the display panel 100 a. The ESD protection circuit 10 is provided on the driver chip 100 b. For the ESD protection circuit 10, reference may be made to the above description of the ESD protection circuit, which is not described herein again.
The ESD protection circuit and the display device provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to illustrate the principles and implementations of the present application, and the description of the embodiments above is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, the specific implementation manner and the application scope may be changed, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (10)

1. An ESD protection circuit is characterized by comprising a first power line, a second power line, a reference high-voltage signal line, a reference low-voltage signal line, a detection module, an amplification module and a discharge module; wherein,
the first power line is provided with an I/O (input/output) end, the first power line is used for providing normal working high voltage, the second power line is used for providing discharge voltage, the reference high-voltage signal line is used for providing reference high voltage, and the reference low-voltage signal line is used for improving reference low voltage;
the detection module is electrically connected to the I/O terminal, the second power line and the amplification module, and is used for detecting whether ESD abnormal charges occur at the I/O terminal, and if the ESD abnormal charges occur, the ESD abnormal charges are transmitted to the amplification module;
the amplifying module is electrically connected to the reference high-voltage signal line, the reference low-voltage signal line, the detecting module and the discharging module, and is used for amplifying the ESD abnormal charges and transmitting the amplified ESD abnormal charges to the discharging module;
the discharge module is electrically connected to the first power line, the second power line and the amplification module, and the discharge module is configured to release the ESD abnormal charge of the I/O terminal when receiving the amplified ESD abnormal charge.
2. The ESD protection circuit of claim 1, wherein the detection module comprises a first resistive element and a second resistive element, one end of the first resistive element is electrically connected to the I/O terminal, the other end of the first resistive element is connected to a first node, one end of the second resistive element is electrically connected to the second power line, and the other end of the second resistive element is electrically connected to the first node.
3. The ESD protection circuit of claim 2, wherein the first resistive element comprises a first detection transistor, the second resistive element comprises a second detection transistor, a gate of the first detection transistor is electrically connected to the first node, one of a source and a drain of the first detection transistor is electrically connected to the I/O terminal, the other of the source and the drain of the first detection transistor is electrically connected to the first node, a gate of the second detection transistor is electrically connected to the second power line, one of the source and the drain of the second detection transistor is electrically connected to the first node, and the other of the source and the drain of the second detection transistor is electrically connected to the second power line.
4. The ESD protection circuit of claim 2, wherein a ratio of a channel width of the second detection transistor to a channel width of the first detection transistor is 9 to 11.
5. The ESD protection circuit of claim 2, wherein the amplifying module comprises a first buffer amplifier and a second buffer amplifier, an input of the first buffer amplifier is electrically connected to the first node, an output of the first buffer amplifier is electrically connected to the second node, an input of the second buffer amplifier is electrically connected to the second node, and an output of the second buffer amplifier is electrically connected to the third node.
6. The ESD protection circuit according to claim 5, wherein the first buffer amplifier includes a first amplifying transistor and a second amplifying transistor, the second buffer amplifier includes a third amplifying transistor and a fourth amplifying transistor, the gate of the first amplifying transistor is electrically connected to the first node, one of the source and the drain of the first amplifying transistor is electrically connected to the reference high voltage signal line, the other of the source and the drain of the first amplifying transistor is electrically connected to a second node, the gate of the second amplifying transistor is electrically connected to the second node, one of the source and the drain of the second amplifying transistor is connected to the reference high voltage signal line, the other of the source and the drain of the second amplifying transistor is electrically connected to a third node, the gate of the third amplifying transistor is electrically connected to the first node, one of a source and a drain of the third amplifying transistor is connected to the reference low-voltage signal line, the other of the source and the drain of the third amplifying transistor is electrically connected to the second node, a gate of the fourth amplifying transistor is electrically connected to the second node, one of the source and the drain of the fourth amplifying transistor is connected to the reference low-voltage signal line, and the other of the source and the drain of the fourth amplifying transistor is electrically connected to the third node.
7. The ESD protection circuit of claim 6, wherein the first amplification transistor and the second amplification transistor are p-type transistors, and wherein the third amplification transistor and the fourth amplification transistor are n-type transistors.
8. The ESD protection circuit of claim 5, wherein the discharge module comprises a first discharge transistor and a second discharge transistor, the gate of the first discharge transistor is electrically connected to the first power line, one of the source and the drain of the first discharge transistor is electrically connected to the first power line, the other of the source and the drain of the first discharge transistor is electrically connected to one of the source and the drain of the second discharge transistor, the other of the source and the drain of the second discharge transistor is electrically connected to the second power line, and the gate of the second discharge transistor is electrically connected to the third node.
9. The ESD protection circuit of claim 1, wherein the voltage values of the normal operation high voltage, the reference low voltage, and the discharge voltage decrease in sequence.
10. The display device is characterized by comprising a display panel and a driving chip connected with the display panel; wherein the driving chip is provided with the ESD protection circuit according to any one of claims 1 to 9.
CN202210328429.8A 2022-03-30 2022-03-30 ESD protection circuit and display device Active CN114582282B (en)

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