CN114580339A - Signal line electromigration inspection method and device, electronic device and storage medium - Google Patents

Abstract

A signal line electromigration inspection method, signal line electromigration inspection apparatus, electronic device, and non-transitory computer-readable storage medium. The signal line electromigration inspection method is applied to an integrated circuit design, the integrated circuit design includes a top-level design and a plurality of sub-designs, and the signal line electromigration inspection method includes: generating multiple boundary model files corresponding to the multiple sub-designs one-to-one, wherein each Each boundary model file includes description information of multiple interaction elements in the sub-design corresponding to the boundary model file, and the multiple interaction elements are used to realize the relationship between the sub-design and the top-level design and/or the sub-designs in the multiple sub-designs except for the sub-designs corresponding to the boundary model file. to interact with other sub-designs; obtain description files corresponding to the top-level design; perform signal line electromigration checks on the top-level design based on multiple boundary model files and description files corresponding to the top-level design.

Description

Signal line electromigration inspection method and device, electronic device and storage medium

technical field

Embodiments of the present disclosure relate to a signal line electromigration inspection method, a signal line electromigration inspection apparatus, an electronic device, and a non-transitory computer-readable storage medium.

Background technique

With the continuous progress of the preparation process, the increase of the process accuracy, the continuous reduction of the process line width, the continuous increase of the integration degree of the chip design, the gradual increase of the current density per unit line width, and the reliability requirements for the signal line electromigration inspection of the chip. Both scale and iteration time presented serious challenges.

SUMMARY OF THE INVENTION

At least one embodiment of the present disclosure provides a signal line electromigration inspection method, which is applied to an integrated circuit design, wherein the integrated circuit design includes a top-level design and a plurality of sub-designs, and the signal line electromigration inspection method includes: generating and The multiple sub-designs correspond to multiple boundary model files one-to-one, wherein each boundary model file includes description information of multiple interaction elements in the sub-design corresponding to the boundary model file, and the multiple interaction elements are used to realize The sub-design interacts with the top-level design and/or sub-designs other than the sub-design corresponding to the boundary model file in the top-level design and/or the plurality of sub-designs; obtaining a description file corresponding to the top-level design; based on the A plurality of boundary model files and description files corresponding to the top-level design are used to perform signal line electromigration inspection on the top-level design.

For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, for the i-th sub-design in the plurality of sub-designs, the i-th sub-design includes a plurality of logic units and a plurality of boundary signal connection nets and a plurality of pins, i is a positive integer, the plurality of logic units include at least one boundary driving unit and at least one boundary receiving unit, and the plurality of pins include at least one boundary input pin and at least one boundary output pin , each boundary signal connection net is used for connecting a boundary input pin and a boundary receiving unit or connecting a boundary output pin and a boundary driving unit, and the multiple interactive elements in the i-th sub-design include the at least one A boundary driving unit, the at least one boundary receiving unit, the at least one boundary input pin, the at least one boundary output pin, and the plurality of boundary signal connection nets.

For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, the i-th sub-design further includes at least one feedthrough connection net, and the plurality of pins further includes at least one feedthrough input pin and At least one feedthrough output pin, each feedthrough connection net represents a connection net directly connected from a feedthrough input pin of the i-th sub-design to a feed-through output pin, in the i-th sub-design The plurality of interactive elements also include the at least one feedthrough connection net, the at least one feedthrough input pin, and the at least one feedthrough output pin.

For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, generating multiple boundary model files corresponding to the multiple sub-designs one-to-one includes: acquiring multiple boundary model files corresponding to the multiple sub-designs one-to-one. and generating the plurality of boundary model files based on the plurality of description files corresponding to the plurality of sub-designs one-to-one.

For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, generating the plurality of boundary model files based on the plurality of description files corresponding to the plurality of sub-designs one-to-one includes: for each sub-design : delete the description information corresponding to the elements in each sub-design except the multiple interaction elements in each sub-design from the description file corresponding to each sub-design, so as to obtain the corresponding boundary of each sub-design model file.

For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, generating a plurality of boundary model files corresponding to the plurality of sub-designs one-to-one includes: for each sub-design: obtaining information in each sub-design. description information of multiple interaction elements, so as to obtain the boundary model file corresponding to each sub-design.

For example, the signal line electromigration inspection method provided by at least one embodiment of the present disclosure further includes: acquiring a plurality of description files corresponding to the plurality of sub-designs respectively; and performing a signal analysis on each sub-design based on the description file corresponding to each sub-design Wire Electromigration Check.

For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, the description file corresponding to the top-level design is configured to be able to call multiple description files corresponding to the multiple sub-designs respectively.

For example, in the signal line electromigration inspection method provided by at least one embodiment of the present disclosure, the description file corresponding to the top-level design is a design exchange format file.

At least one embodiment of the present disclosure provides a signal line electromigration inspection apparatus, which is applied to an integrated circuit design, wherein the integrated circuit design includes a top-level design and a plurality of sub-designs, and the signal line electromigration inspection apparatus includes: an acquisition unit, is configured to obtain a description file corresponding to the top-level design; the generating unit is configured to generate a plurality of boundary model files corresponding to the plurality of sub-designs one-to-one, wherein each boundary model file includes the boundary model file Description information of multiple interaction elements in the corresponding sub-design, the multiple interaction elements are used to implement the sub-design and the top-level design and/or the sub-designs in the multiple sub-designs except for the sub-design corresponding to the boundary model file The sub-designs outside the design interact; the inspection unit is configured to perform signal line electromigration inspection on the top-level design based on the plurality of boundary model files and the description file corresponding to the top-level design.

At least one embodiment of the present disclosure provides an electronic device, comprising: a memory non-transitory storing computer-executable instructions; a processor configured to execute the computer-executable instructions, wherein the computer-executable instructions are When the processor is running, the signal line electromigration inspection method according to any embodiment of the present disclosure is implemented.

At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement a The signal line electromigration inspection method described in any embodiment of the present disclosure.

Description of drawings

In order to explain the technical solutions of the embodiments of the present disclosure more clearly, the accompanying drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limit the present disclosure. .

FIG. 1 is a schematic flowchart of a signal line electromigration inspection method provided by at least one embodiment of the present disclosure;

2 is a schematic structural diagram of a sub-design provided by at least one embodiment of the present disclosure;

3 is a schematic structural diagram of a top-level design provided by at least one embodiment of the present disclosure;

4 is a schematic diagram of a signal line electromigration inspection apparatus according to at least one embodiment of the present disclosure;

5 is a schematic diagram of an electronic device according to at least one embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present disclosure.

Unless otherwise defined, technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. As used in this disclosure, "first," "second," and similar terms do not denote any order, quantity, or importance, but are merely used to distinguish the various components. "Comprises" or "comprising" and similar words mean that the elements or things appearing before the word encompass the elements or things recited after the word and their equivalents, but do not exclude other elements or things. Words like "connected" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "Down", "Left", "Right", etc. are only used to represent the relative positional relationship, and when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits a detailed description of some well-known functions and well-known components.

Due to the increasing scale of chip (ie integrated circuit) design and the proliferation of computing nodes in the chip, the requirements for the capacity of electronic design automation (EDA) tools and the storage capacity of servers are getting higher and higher. Especially for ultra-large-scale designs such as CPU (central processing unit, central processing unit)/GPU (graphics processing unit, graphics processing unit) that require performance and computing power to perform full-chip signal line electromigration signoff inspection, it often occurs that the design capacity exceeds the EDA. The capacity limitation of the tool makes the EDA tool unsupportable, and the problems such as the excessively long iteration time become more and more frequent.

Usually, the chip design can be divided into multiple layers according to the design scale and design strategy. For example, the chip design can include a top-level design and a bottom-level design. The signal line electromigration check on the chip design is to flatten the entire chip design from top to bottom. , is to read all the top-level design and bottom-level design of the chip design into the tool to perform the overall signal line electromigration inspection of the chip design. Because the computing capacity of chip design is very large, the iteration time is very long, and the storage capacity is very large. If the size of the chip design exceeds the capacity limit of the tool, the tool will not be able to perform checks on the chip design, causing the tool process to crash.

The hierarchical processing method is a method of performing signal electromigration inspection on the top-level design and bottom-level design of the chip design respectively. When the signal line electromigration sign-off check is performed on the top-level design, the top-level design and the bottom-level design are read into the tool for inspection, and the EDA tool is set to use the top only mode. The top only mode represents a mode for the EDA tool to check the signal line electromigration. , In this top only mode, the EDA tool only performs signal line electromigration check on the signal net (signal net) that completely defines the logical connection and physical connection in the Design Exchange Format (DEF) file of the top-level design. Therefore, when the configuration tool uses the top only mode, the electromigration check is performed on the signal lines in the top-level design and the interaction signal lines between the top-level design and the bottom-level design. However, even if the top-level design is separated from the bottom-level design for signal line electromigration inspection, in top only mode, the processing time for the top-level design is still very long and the storage capacity is very large. After the top-level design and the bottom-level design are all read into the tool, when the read data exceeds the upper limit of the tool capacity, the signal line electromigration check of the top-level design cannot be completed, resulting in a crash of the tool process.

At least one embodiment of the present disclosure provides a signal line electromigration inspection method. The signal line electromigration inspection method is applied to an integrated circuit design, the integrated circuit design includes a top-level design and a plurality of sub-designs, and the signal line electromigration inspection method includes: generating multiple boundary model files corresponding to the multiple sub-designs one-to-one, wherein each Each boundary model file includes description information of multiple interaction elements in the sub-design corresponding to the boundary model file, and the multiple interaction elements are used to realize the relationship between the sub-design and the top-level design and/or the sub-designs in the multiple sub-designs except for the sub-designs corresponding to the boundary model file. Interact with sub-designs outside; obtain description files corresponding to the top-level design; perform signal line electromigration checks on the top-level design based on multiple boundary model files and description files corresponding to the top-level design.

In the signal line electromigration inspection method provided by the embodiment of the present disclosure, the signal line electromigration inspection can be performed on the top-level design based on the boundary model of the sub-design and the description file of the top-level design, so as to realize the hierarchical signal line electromigration inspection, This solves the problem of the bottleneck of the upper limit of the tool capacity, avoids the read data exceeding the upper limit of the tool capacity, prevents the tool process from crashing, realizes the signal line electromigration inspection for large-scale designs, reduces the iterative running time of the signal line electromigration inspection, and reduces the cost of Server storage capacity requirements.

At least one embodiment of the present disclosure further provides a signal line electromigration inspection apparatus, an electronic device, and a non-transitory computer-readable storage medium applied to the above signal line electromigration inspection method.

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

FIG. 1 is a schematic flowchart of a signal line electromigration inspection method provided by at least one embodiment of the present disclosure.

The signal line electromigration inspection method provided by the embodiments of the present disclosure can be applied to integrated circuit design (ie, integrated circuit), for example, the integrated circuit design can be a large-scale integrated circuit design. For example, the integrated circuit design may be divided into multiple levels according to the design scale and design strategy. For example, in some embodiments, the integrated circuit design may include a top-level design and multiple sub-designs. The top-level design includes logic units (driving units and receiving cells), non-logic cells, nets, pins, etc., each sub-design also includes one or more of logic cells, non-logic cells, nets, pins, etc.

As shown in FIG. 1 , the signal line electromigration inspection method may include the following steps S10 to S12.

Step S10: generating multiple boundary model files corresponding to multiple sub-designs one-to-one;

Step S11: obtaining a description file corresponding to the top-level design;

Step S12: Perform signal line electromigration inspection on the top-level design based on the multiple boundary model files and the description files corresponding to the top-level design.

For example, in step S10, each boundary model file includes description information of multiple interaction elements in the sub-design corresponding to the boundary model file, and each sub-design may only interact with the top-level design, or may only interact with other sub-designs. Interact with, or interact with both the top-level design and other sub-designs. Multiple interactive elements in the sub-design are used to realize the interaction between the sub-design and the top-level design and/or sub-designs other than the sub-design in the sub-designs. interact.

For example, the description information of each interactive element may include the name of the interactive element, the name of the element/pin to which the interactive element is connected, the direction, attribute, position, shape and other information corresponding to the interactive element. The direction of the interactive component is for logic. For example, if the interactive component is a pin, the direction corresponding to the interactive component indicates whether the pin is an output pin or an input pin, and the attribute corresponding to the interactive component is used to indicate that the pin belongs to Pins for power, ground, signal, or clock, etc.

For example, in an integrated circuit design, each sub-design may include multiple logic cells, multiple connection nets, and multiple pins, and the multiple connection nets may include a clock net (clock net), a power net (power net), a ground net (ground net), signal connection network (signal net), etc. The signal connections may include boundary signal connections, internal signal connections, feedthrough connections, and the like. Each connection net is used to implement a connection function, for example, each connection net may include a connection line (metal wire, etc.), and may also include structures such as vias.

For example, in step S10, the boundary model file corresponding to each sub-design is a file based on the design exchange format.

For example, in some embodiments, for the i-th sub-design among the plurality of sub-designs, the i-th sub-design includes a plurality of logic cells, a plurality of boundary signal connection nets, and a plurality of pins, i is a positive integer, and the plurality of logic cells It includes at least one border driving unit and at least one border receiving unit, the plurality of pins includes at least one border input pin and at least one border output pin, and each border signal connection net is used to connect one border input pin and one border receiving pin unit or connecting one boundary output pin and one boundary driving unit, the plurality of interactive elements in the ith sub-design include at least one boundary driving unit, at least one boundary receiving unit, at least one boundary input pin, at least one boundary output pin Connect the network with multiple boundary signals. In this case, the boundary model file corresponding to the ith sub-design includes description information of at least one boundary driving unit, description information of at least one boundary receiving unit, description information of at least one boundary input pin, and description information of at least one boundary output pin. Description information and description information of multiple boundary signal connection nets, description information of physical and logical connections between each boundary driving unit and corresponding boundary output pins, and the relationship between each boundary receiving unit and corresponding boundary input pins. Description of the physical and logical connections between them.

It should be noted that the ith sub-design may be any sub-design among multiple sub-designs.

For example, for each boundary signal connection net in a sub-design, if the boundary signal connection net is connected to a boundary receiving unit in the sub-design, the driver unit corresponding to the boundary signal connection net is located in the top-level design or multiple sub-designs In another sub-design in addition to this sub-design; if the boundary signal connection net is connected to a boundary drive unit in the sub-design, the receiver unit corresponding to the boundary signal connection network is located in the top-level design or multiple sub-designs in another sub-design in addition to this sub-design. For example, in some examples, the boundary receiving unit in a sub-design is connected to the boundary input pin in the sub-design through the boundary signal connection net in the sub-design, then the boundary input pin in the sub-design can be connected by A connection net connects to a driver cell in the top-level design, or a boundary input pin in this subdesign can be connected through a connection net to a boundary output pin in another subdesign, the boundary The output pins are connected to a driver unit in the other sub-design through the boundary signal connection net in the other sub-design.

It should be noted that, for example, a sub-design may include boundary driving units, boundary output pins, and boundary signal connection nets, but not boundary receiving units and boundary input pins. In this case, the multiple interaction elements in the sub-design include Boundary drive unit, boundary output pin and boundary signal connection net; for another example, the sub-design may include boundary reception unit, boundary input pin and boundary signal connection net, but does not include boundary drive unit and boundary output pin, in this case, The multiple interaction elements in this sub-design include boundary receive cells, boundary input pins and boundary signal connection nets. The embodiments of the present disclosure do not specifically limit the number and type of interaction elements in each sub-design, and the specific type and number of interaction elements in each sub-design are determined according to the sub-design.

It should be noted that, in the embodiments of the present disclosure, each signal connection net can be used to connect one driving unit and at least one receiving unit, that is, each signal connecting net can connect one driving unit to one receiving unit or connect at most one driving unit to one receiving unit. receiving unit.

For example, in some embodiments, the ith sub-design further includes at least one feedthrough connection net, the plurality of pins further includes at least one feedthrough input pin and at least one feedthrough output pin, each feedthrough connection net representing A net that connects directly from a feedthrough input pin of the ith subdesign to a feedthrough output pin. The plurality of interactive elements in the ith sub-design also includes at least one feedthrough connection net, at least one feedthrough input pin, and at least one feedthrough output pin. In this case, the boundary model file corresponding to the ith sub-design further includes description information of at least one feedthrough connection net, description information of at least one feedthrough input pin, description information of at least one feedthrough output pin, and each Description information of the physical and logical connections between the feedthrough connection net and the feedthrough input pins and feedthrough output pins to which the feedthrough connection net is connected.

For example, in some embodiments, step S10 may include: acquiring multiple description files corresponding to multiple sub-designs one-to-one; and generating multiple boundary model files based on multiple description files corresponding to multiple sub-designs one-to-one.

For example, in step S10, generating multiple boundary model files based on multiple description files corresponding to multiple sub-designs one-to-one includes: for each sub-design: deleting from the description file corresponding to each sub-design, except for each sub-design The description information corresponding to the components other than the multiple interaction components in the sub-design is obtained, so as to obtain the boundary model file corresponding to each sub-design.

For example, in some embodiments, elements in each sub-design other than the plurality of interaction elements in each sub-design may include at least one non-logical unit, and in this case, each sub-design is deleted from the description file corresponding to each sub-design The description information corresponding to the elements other than the multiple interaction elements in each sub-design may include: deleting the description information corresponding to at least one non-logical unit in the sub-design from the description file corresponding to each sub-design.

For example, in other embodiments, each sub-design further includes at least one internal signal connection net, the plurality of logic units in each sub-design include at least one internal driving unit and at least one internal receiving unit, and each internal signal connecting net is used for In order to connect an internal driving unit and an internal receiving unit, the elements in each sub-design other than the plurality of interactive elements in each sub-design may include at least one non-logic unit, at least one internal signal connection network, at least one internal driving unit and at least one internal receiver unit. At this time, deleting from the description file corresponding to each sub-design the description information corresponding to the elements in each sub-design except for the multiple interaction elements in each sub-design may include: deleting the sub-design from the description file corresponding to each sub-design Descriptive information corresponding to at least one non-logic unit in the design, delete the descriptive information corresponding to the internal signal net in the sub-design, delete the descriptive information corresponding to the internal driving unit and the internal receiving unit in the sub-design (including the internal driving unit and the internal receiving unit). Description information of the internal receiving unit, description information of the logical connection and physical connection corresponding to the internal driving unit and the internal receiving unit).

For example, the non-logical cells may include physical fillers, etc., and the non-logical cells have no logical function. The physical filling unit may be a metal filling unit, a decoupling capacitor filling unit, and the like.

For example, in other embodiments, step S10 may include: for each sub-design: acquiring description information of multiple interaction elements in each sub-design, so as to obtain a boundary model file corresponding to each sub-design.

For example, in some embodiments, in step S10, acquiring description information of multiple interaction elements in each sub-design may include: acquiring descriptions of multiple interaction elements in each sub-design from a description file corresponding to each sub-design information.

For example, in some other embodiments, in step S10, acquiring the description information of the multiple interaction elements in each sub-design may include: acquiring the sub-design from a design library file corresponding to a tool that executes the layout and routing of the sub-design. The description information of multiple interactive elements.

For example, if the multiple interaction elements in each sub-design include at least one boundary driving unit, at least one boundary receiving unit, at least one boundary input pin, at least one boundary output pin, and multiple boundary signal connection nets, obtain each sub-design The description information of multiple interaction elements in the design includes: obtaining description information of at least one boundary driving unit, description information of at least one boundary receiving unit, description information of at least one boundary input pin, description information of at least one boundary output pin , the description information of multiple boundary signal connection nets, the physical connection and logic between each boundary drive unit and the corresponding boundary output pin (the corresponding boundary output pin represents the output pin connected to the boundary drive unit) The description information of the connection, the description information of the physical connection and the logical connection between each boundary receiving unit and the corresponding boundary input pin (the corresponding boundary input pin represents the input pin connected to the boundary receiving unit).

For example, if the multiple interaction elements in each subdesign further include at least one feedthrough connection net, at least one feedthrough input pin, and at least one feedthrough output pin, obtain the descriptions of the multiple interaction elements in each subdesign The information further includes: acquiring description information of at least one feedthrough connection network, description information of at least one feedthrough input pin, description information of at least one feedthrough output pin, and each feedthrough connection network is connected to the feedthrough connection network. Description of the physical and logical connections between the connected feedthrough input pins and feedthrough output pins.

For example, the description file corresponding to the top-level design is a design exchange format file, and the description file corresponding to each sub-design may also be a design exchange format file. The description file corresponding to the top-level design and the description file corresponding to each sub-design may also be other suitable files, which are not specifically limited in this embodiment of the present disclosure.

For example, the description file corresponding to the top-level design is configured to be able to call multiple description files corresponding to multiple sub-designs respectively. The description file corresponding to the top-level design can include the description information of the physical connections and logical connections of the connection nets that interact with all sub-designs, and can also include the description information of the internal elements of the top-level design and the physical and logical connections between the internal elements. description information. The description file corresponding to the sub-design may include description information of all elements included in the sub-design and description information of physical connections and logical connections between all the elements. The description file corresponding to the top-level design does not include the description information of the physical connection and logical connection between the components included in the sub-design.

It should be noted that the integrated circuit design can be divided into more than two layers. In other embodiments, the integrated circuit design includes a top-level design, a plurality of first-layer sub-designs and a plurality of second-layer sub-designs, each of which is a second-layer sub-design. The description file corresponding to the layer sub-design includes at least one element included in the second-layer sub-design and its connection relationship, and the description file corresponding to each first-layer sub-design may include part of the second-layer sub-design. The connection (including physical connection and logical connection) relationship between layer sub-designs and the connection relationship between this part of the second-layer sub-design and the first-layer sub-design, for example, the description file corresponding to each first-layer sub-design It may also include at least one element inside the first-level sub-design and its connection relationship, and the top-level design includes the connection relationship (including physical connection and logical connection) between some of the first-level sub-designs in the multiple first-level sub-designs. and the connection relationship between the part of the first-level sub-design and the top-level design, for example, the description file corresponding to the top-level design may also include at least one element inside the top-level design and its connection relationship. The description file corresponding to the top-level design can call the description file corresponding to the first-level sub-design, and the description file corresponding to the first-level sub-design can call the description file corresponding to the corresponding second-level sub-design.

For example, the description information of logical connections includes logical connection relationships (represented by netlists), physical constraints, and the like. The description information of the physical connection includes the layout plan, layout position and direction, and routing rules (eg, routing geometry data, etc.).

For example, when designing an integrated circuit, a corresponding description file may be set for the top-level design and a corresponding description file may be set for each sub-design, so that in step S11, the description file corresponding to the top-level design settings may be directly obtained.

For example, in step S12, a signal line electromigration check may be performed on the signal lines in the top-level design based on the multiple boundary model files and the description files corresponding to the top-level design.

FIG. 2 is a schematic structural diagram of a sub-design provided by at least one embodiment of the present disclosure. The sub-design provided by the embodiment of the present disclosure will be described in detail below with reference to FIG. 2 .

As shown in FIG. 2 , in some embodiments, the sub-design 100 may include a boundary driving unit S1 , a boundary receiving unit S2 , a first connecting net L1 , a second connecting net L2 , a third connecting net L3 , and a fourth connecting net L4 , Internal driving unit S5, internal receiving unit S6, feed-through input pin S31, feed-through output pin S32, boundary output pin S41, boundary input pin S42. It should be noted that the feedthrough input pin S31 and the boundary input pin S42 are both input pins, the difference is that the feedthrough input pin S31 is directly connected to the The output pin S32 is fed through, and the boundary input pin S42 is connected to a boundary receiving unit S2 through a connection net (eg, the third connection net L3). Similarly, the feedthrough output pin S32 and the boundary output pin S41 are both output pins, and the feedthrough output pin S32 is directly connected to the feedthrough input pin S31 through a connection net (eg, the second connection net L2), And the boundary output pin S41 is connected to a boundary driving unit S1 through a connection net (eg, the fourth connection net L4).

The first connection network L1 is an internal signal connection network, and the first connection network L1 is used to connect the internal driving unit S5 and the internal receiving unit S6.

The second connection net L2 is a feedthrough connection net, and the second connection net L2 is directly connected from the feedthrough input pin S31 of the sub-design 100 to the feedthrough output pin S32 .

The third connection network L3 and the fourth connection network L4 are both boundary signal connection networks, the third connection network L3 is used to connect the boundary input pin S42 to the boundary receiving unit S2, and the fourth connection network L4 is used to output the boundary Pin S41 is connected to the boundary drive unit S1.

It should be noted that the sub-design 100 may further include at least one non-logic unit (not shown in FIG. 2 ).

The following describes the process of generating the boundary model file corresponding to each sub-design by taking the sub-design 100 shown in FIG. 2 as an example.

For example, in one embodiment, in step S10, first, a description file (eg, a design exchange format file) corresponding to the sub-design 100 may be obtained, and then at least one of the sub-designs 100 is deleted from the description file corresponding to the sub-design 100 The description information corresponding to a non-logic unit, the description information corresponding to the internal signal connection network (ie the first connection network L1) in the sub-design 100, the logic except the boundary driving unit S1 and the boundary receiving unit S2 in the sub-design 100 The description information corresponding to the unit (for example, the internal driving unit S5 and the internal receiving unit S6 in FIG. 2 , etc.) is obtained to obtain the boundary model file corresponding to the sub-design 100 . At this time, the boundary model file corresponding to the sub-design 100 includes the description information of the boundary output pin S41, the description information of the boundary input pin S42, the description information of the boundary signal connection nets L3 and L4, the description information of the boundary driving unit S1, the boundary information Description information of the receiving unit S2, description information of the physical connection and logical connection between the boundary driving unit S1 and the boundary output pin S41, description information of the physical connection and logical connection between the boundary receiving unit S2 and the boundary input pin S42 , the description information of the feedthrough connection network L2, the description information of the feedthrough input pin S31, the description information of the feedthrough output pin S32, the description information of the feedthrough connection network L2 and the feedthrough input pin S31 and the feedthrough output pin S32 Description of the physical and logical connections between them.

For example, in another embodiment, in step S10, first, the description file corresponding to the sub-design 100 may be obtained, and then the description information of the boundary output pin S41 and the boundary input pin can be extracted from the description file corresponding to the sub-design 100 Description information of S42, description information of boundary signal connection nets L3 and L4, description information of boundary driving unit S1, description information of boundary receiving unit S2, physical connection and logical connection between boundary driving unit S1 and boundary output pin S41 description information, description information of the physical connection and logical connection between the boundary receiving unit S2 and the boundary input pin S42, description information of the feedthrough connection network L2, description information of the feedthrough input pin S31, feedthrough output pin The description information of S32, the description information of the physical connection and logical connection between the feedthrough connection net L2 and the feedthrough input pin S31 and the feedthrough output pin S32, so as to obtain the boundary model file corresponding to the sub-design 100.

FIG. 3 is a schematic structural diagram of a top-level design provided by at least one embodiment of the present disclosure.

As shown in FIG. 3 , the integrated circuit design may include a top-level design 200 and a plurality of sub-designs including a first sub-design 210 and a second sub-design 220 .

For example, as shown in FIG. 3, the top-level design 200 may include an internal receiving unit TS21, a border receiving unit TS22, a border receiving unit TS23, an internal driving unit TS11, a border driving unit TS12, a border driving unit TS13, and a border driving unit TS14. The border receiving unit TS22, the border receiving unit TS23, the border driving unit TS12, the border driving unit TS13 and the border driving unit TS14 are used for connection with the sub-design.

For example, as shown in FIG. 3 , the first sub-design 210 may include a boundary driving unit SS11 , a boundary driving unit SS12 , a boundary receiving unit SS21 , a feedthrough connection net SL1 , a boundary signal connection net SL2 , a boundary signal connection net SL3 , and a boundary signal connection net SL1 . Connection net SL4, feedthrough input pin SP11, feedthrough output pin SP21, boundary input pin SP12, boundary output pin SP22 and boundary output pin SP23.

Inside the first sub-design 210, the feedthrough connection net SL1 is used to connect the feedthrough input pin SP11 and the feedthrough output pin SP21, the boundary signal connection net SL2 is used to connect the boundary output pin SP22 and the boundary drive unit SS11, The boundary signal connection net SL3 is used for connecting the boundary input pin SP12 and the boundary receiving unit SS21, and the boundary signal connection net SL4 is used for connecting the boundary output pin SP23 and the boundary driving unit SS12.

For example, as shown in FIG. 3, the second sub-design 220 may include a border receiving unit SS22, a border receiving unit SS23, a border receiving unit SS24, a border driving unit SS13, a border signal connection net SL5 to a border signal connection net SL8, a border input lead Pin SP13, boundary input pin SP14, boundary input pin SP15 and boundary output pin SP24.

Inside the second sub-design 220, the boundary signal connection net SL5 is used to connect the boundary input pin SP13 and the boundary receiving unit SS22, the boundary signal connection net SL6 is used to connect the boundary input pin SP14 and the boundary receiving unit SS23, and the boundary signal connection The net SL7 is used for connecting the border input pin SP15 and the border receiving unit SS24, and the border signal connecting net SL8 is used for connecting the border output pin SP24 and the border driving unit SS13.

For example, as shown in FIG. 3, the top-level design 200 may further include an internal connection network TL1, boundary signal connection networks TL2-TL8, and the boundary signal connection networks TL2-TL8 are used to connect each sub-design and connect each sub-design with the top-level design The boundary driving unit and the boundary receiving unit are connected. For example, in the top-level design 200, the internal signal connection net TL1 is used to connect the internal receiving unit TS21 and the internal driving unit TS11, and the boundary signal connection net TL2 is used to connect the boundary driving unit TS12 and the feedthrough input pin of the first sub-design 210. SP11, the boundary signal connection net TL3 is used for connecting the boundary driving unit TS13 and the boundary input pin SP12 of the first subdesign 210, and the boundary signal connection net TL4 is used for connecting the boundary receiving unit TS22 and the boundary output pin of the first subdesign 210 SP22, the boundary signal connection net TL5 is used to connect the feedthrough output pin SP21 of the first sub-design 210 and the boundary input pin SP13 of the second sub-design 220, and the boundary signal connection net TL6 is used to connect the boundary of the first sub-design 210 The output pin SP23 and the boundary input pin SP14 of the second sub-design 220, the boundary signal connection net TL7 is used to connect the boundary output pin SP24 of the second sub-design 220 and the boundary receiving unit TS23, and the boundary signal connection net TL8 is used to connect The boundary input pin SP15 of the second sub-design 220 and the boundary driving unit TS14.

It should be noted that for each pin in the sub-design, the pin is an input pin relative to the sub-design, and the pin is an output pin relative to the top-level design.

In the example shown in FIG. 3 , the boundary model file corresponding to the first sub-design 210 includes the description information of each element, connection nets and pins included in the first sub-design 210 shown in FIG. 3 , and their physical connections to each other and the description information of the logical connection, the boundary model file corresponding to the second sub-design 220 includes the description information of each element, the connection net and the pin included in the second sub-design 220 shown in FIG. The description information of the connection, the description file corresponding to the top-level design 200 includes the description information of each element and the connection net in the top-level design 200 shown in FIG. Description information of physical connections and logical connections, and description information of physical connections and logical connections between the first sub-design 210 and the second sub-design 220 .

It should be noted that each of the first sub-design 210 , the second sub-design 220 and the top-level design 200 may further include at least one non-logic unit (not shown in FIG. 3 ).

For example, in some embodiments, the signal line electromigration inspection method may further include: acquiring multiple description files corresponding to multiple sub-designs; and performing signal line electromigration inspection on each sub-design based on the description file corresponding to each sub-design.

The signal line electromigration inspection method provided by the embodiments of the present disclosure effectively solves the problem of a large demand for the storage capacity of the server, effectively solves the bottleneck problem of the upper limit of the tool capacity, effectively solves the problem of long iterative running time, and avoids the read-in data. Exceeding the upper limit of tool capacity, thereby preventing tool process crashes, realizing signal line electromigration inspection of large-scale designs, reducing iterative running time of signal line electromigration inspection, and reducing server storage capacity.

FIG. 4 is a schematic diagram of a signal line electromigration inspection apparatus according to at least one embodiment of the present disclosure.

At least one embodiment of the present disclosure further provides a signal line electromigration inspection apparatus, which is applied to integrated circuit design. An integrated circuit design includes a top-level design and multiple sub-designs. For the related description of the top-level design and the multiple sub-designs, reference may be made to the description in the above-mentioned embodiments of the signal line electromigration inspection method, and repeated details will not be repeated.

As shown in FIG. 4 , the signal line electromigration inspection apparatus 400 may include a generation unit 401 , an acquisition unit 402 and an inspection unit 403 .

The generating unit 401 is configured to generate a plurality of boundary model files corresponding to the plurality of sub-designs one-to-one. Each boundary model file includes description information of multiple interaction elements in the sub-design corresponding to the boundary model file, and the multiple interaction elements are used to realize the sub-design and the top-level design and/or the sub-designs in the multiple sub-designs except for the sub-design corresponding to the boundary model file to interact with other subdesigns. The generating unit 401 is configured to implement the step S10 shown in FIG. 1 , and the specific operations performed by the generating unit 401 may refer to the description of the step S10 above, which will not be repeated here.

The obtaining unit 402 is configured to obtain the description file corresponding to the top-level design. The obtaining unit 402 is configured to implement the step S11 shown in FIG. 1 , and the specific operations performed by the obtaining unit 402 may refer to the description of the step S11 above, which will not be repeated here.

The checking unit 403 is configured to perform signal line electromigration checking on the top-level design based on the plurality of boundary model files and the description files corresponding to the top-level design. The checking unit 403 is configured to implement step S12 shown in FIG. 1 . For specific operations performed by the checking unit 403 , reference may be made to the description of step S12 above, which will not be repeated here.

For example, in some embodiments, the generating unit 401, the obtaining unit 402, and/or the checking unit 403 may be implemented by hardware, software, firmware, and combinations thereof.

For example, in some embodiments, the generating unit 401, the obtaining unit 402 and/or the checking unit 403 may comprise codes and programs stored in a memory; the codes and programs may be executed by the processor to implement the generating unit 401, Some or all of the functions of the acquisition unit 402 and/or the inspection unit 403. For example, the generating unit 401, the obtaining unit 402 and/or the checking unit 403 may be dedicated hardware devices for implementing some or all of the functions of the generating unit 401, the obtaining unit 402 and/or the checking unit 403 as described above. For example, the generating unit 401, the obtaining unit 402 and/or the checking unit 403 may be one circuit board or a combination of a plurality of circuit boards for implementing the functions as described above. In an embodiment of the present disclosure, the one circuit board or a combination of multiple circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processors ; and (3) firmware executable by the processor stored in memory.

For example, in some embodiments, for the i-th sub-design among the plurality of sub-designs, the i-th sub-design includes a plurality of logic cells, a plurality of boundary signal connection nets, and a plurality of pins, i is a positive integer, and the plurality of logic cells It includes at least one border driving unit and at least one border receiving unit, the plurality of pins includes at least one border input pin and at least one border output pin, and each border signal connection net is used to connect one border input pin and one border receiving pin unit or connecting one boundary output pin and one boundary driving unit, the plurality of interactive elements in the ith sub-design include at least one boundary driving unit, at least one boundary receiving unit, at least one boundary input pin, at least one boundary output pin Connect the network with multiple boundary signals.

For example, in some embodiments, the ith sub-design further includes at least one feedthrough connection net, the plurality of pins further includes at least one feedthrough input pin and at least one feedthrough output pin, each feedthrough connection net representing A connection net directly connected from a feedthrough input pin of the ith sub-design to a feedthrough output pin, and the plurality of interactive elements in the ith sub-design further include at least one feedthrough connection net, at least one feedthrough input pin pin and at least one feedthrough output pin.

For example, in some embodiments, when performing the operation of generating multiple boundary model files corresponding to multiple sub-designs one-to-one, the generating unit 401 is configured to: acquire multiple description files corresponding to multiple sub-designs one-to-one; Multiple description files corresponding to multiple sub-designs one-to-one generate multiple boundary model files.

For example, in some embodiments, when performing an operation of generating a plurality of boundary model files based on a plurality of description files corresponding to a plurality of sub-designs one-to-one, the generating unit 401 is configured to: for each sub-design: from each sub-design: The description information corresponding to the components in each sub-design except for the multiple interaction components in each sub-design is deleted from the corresponding description file, so as to obtain a boundary model file corresponding to each sub-design.

For example, in other embodiments, when performing the operation of generating multiple boundary model files corresponding to multiple sub-designs one-to-one, the generating unit 401 is configured to: for each sub-design: acquire multiple interactions in each sub-design Component description information to get the boundary model file corresponding to each sub-design.

For example, in some embodiments, the acquiring unit 402 is further configured to acquire multiple description files corresponding to the multiple sub-designs respectively; the checking unit 403 is further configured to perform signal wiring for each sub-design based on the description file corresponding to each sub-design Electromigration check.

For example, in some embodiments, the description file corresponding to the top-level design is configured to be able to call multiple description files corresponding to multiple sub-designs respectively.

For example, in some embodiments, the description file corresponding to the top-level design is a design interchange format file.

It should be noted that, the signal line electromigration inspection apparatus can achieve similar technical effects as the aforementioned signal line electromigration inspection method, which will not be repeated here.

At least one embodiment of the present disclosure further provides an electronic device, and FIG. 5 is a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure.

For example, as shown in FIG. 5 , the electronic device 500 includes a processor 501 and a memory 502 . It should be noted that the components of the electronic device 500 shown in FIG. 5 are only exemplary and not restrictive, and the electronic device 500 may also have other components according to actual application requirements.

For example, the processor 501 and the memory 502 may communicate with each other. In some examples, processor 501 and memory 502 may communicate through communication bus 503, or may communicate through a network. For example, the communication bus 503 may be a Peripheral Component Interconnect Standard (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus 503 may be divided into an address bus, a data bus, a control bus, and the like. For ease of representation, only one thick line is used to represent the communication bus 503 in FIG. 5, but it does not represent that there is only one bus or one type of bus. The network may include a wireless network, a wired network, and/or any combination of wireless and wired networks. Embodiments of the present disclosure do not limit the type and function of the network and communication bus 503 .

For example, memory 502 is used for non-transitory storage of computer-executable instructions. Processor 501 is used to execute computer-executable instructions. When the computer-executable instructions are executed by the processor 501, the signal line electromigration inspection method according to any of the above embodiments is implemented. For the specific implementation of each step of the signal line electromigration inspection method and related explanation contents, reference may be made to the above-mentioned embodiments of the signal line electromigration inspection method, which will not be repeated here.

For example, other implementation manners of the signal line electromigration inspection method implemented by the processor 501 executing the computer-readable instructions stored in the memory 502 are the same as the implementation manners mentioned in the foregoing method embodiment section, and will not be repeated here.

For example, the electronic device 500 may further include a communication interface 504 for enabling communication between the electronic device 500 and other devices.

For example, the processor 501 and the memory 502 may be provided on the server side (or the cloud).

For example, processor 501 may control other components in electronic device 500 to perform desired functions. The processor 501 may be a central processing unit (CPU), a network processing unit (NP), a tensor processing unit (TPU), a graphics processing unit (GPU), or other devices with data processing capability and/or program execution capability; it may also be Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The central processing unit (CPU) can be an X86 or an ARM architecture or the like.

For example, memory 502 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or nonvolatile memory. Volatile memory may include, for example, random access memory (RAM) and/or cache memory, among others. Non-volatile memory may include, for example, read only memory (ROM), hard disk, erasable programmable read only memory (EPROM), portable compact disk read only memory (CD-ROM), USB memory, flash memory, and the like. One or more computer-readable instructions may be stored on the computer-readable storage medium, and the processor 501 may execute the computer-readable instructions to implement various functions of the electronic device 500 . Various application programs, various data and the like can also be stored in the storage medium.

For example, for a detailed description of the process of performing the signal line electromigration inspection by the electronic device 500, reference may be made to the relevant descriptions in the embodiments of the signal line electromigration inspection method, and repeated descriptions will not be repeated.

FIG. 6 is a schematic diagram of a non-transitory computer-readable storage medium provided by at least one embodiment of the present disclosure. For example, as shown in FIG. 6 , one or more computer-executable instructions 601 may be non-transitory stored on a non-transitory computer-readable storage medium 600 . For example, when the computer-executable instructions 601 are executed by a processor, one or more steps of the signal line electromigration inspection method according to any of the above embodiments may be performed.

For example, the non-transitory computer-readable storage medium 600 may be applied to the electronic device 500 described above, for example, the non-transitory computer-readable storage medium 600 may include the memory 502 in the electronic device 500 .

For example, for the description of the non-transitory computer-readable storage medium 600, reference may be made to the description of the memory 502 in the embodiment of the electronic device 500, and repeated details will not be repeated.

For the present disclosure, the following points need to be noted:

(1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

(2) In the drawings for describing the embodiments of the present invention, the thickness and size of layers or structures are exaggerated for clarity. It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element, Or intermediate elements may be present.

(3) The embodiments of the present disclosure and the features in the embodiments may be combined with each other to obtain new embodiments without conflict.

The above descriptions are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims (12)

1. A signal line electromigration inspection method is applied to an integrated circuit design, wherein the integrated circuit design comprises a top layer design and a plurality of sub-designs,

the signal line electromigration detection method comprises the following steps:

generating a plurality of boundary model files in one-to-one correspondence with the plurality of sub-designs, wherein each boundary model file comprises description information of a plurality of interactive elements in the sub-design corresponding to the boundary model file, and the plurality of interactive elements are used for realizing the interaction between the sub-design and the top-level design and/or the sub-design except the sub-design corresponding to the boundary model file;

acquiring a description file corresponding to the top layer design;

and performing signal line electromigration check on the top-level design based on the plurality of boundary model files and the description file corresponding to the top-level design.

2. The signal line electromigration inspection method of claim 1, wherein for an ith sub-design of the plurality of sub-designs, the ith sub-design includes a plurality of logic cells, a plurality of boundary signal connection nets, and a plurality of pins, i being a positive integer,

the plurality of logic units comprise at least one boundary driving unit and at least one boundary receiving unit, the plurality of pins comprise at least one boundary input pin and at least one boundary output pin, each boundary signal connection net is used for connecting one boundary input pin and one boundary receiving unit or connecting one boundary output pin and one boundary driving unit,

the plurality of interactive elements in the ith sub-design include the at least one boundary driving unit, the at least one boundary receiving unit, the at least one boundary input pin, the at least one boundary output pin, and the plurality of boundary signal connection nets.

3. The signal line electromigration inspection method of claim 2, wherein the ith sub-design further includes at least one feedthrough connection web, the plurality of pins further includes at least one feedthrough input pin and at least one feedthrough output pin, each feedthrough connection web representing a connection web directly connected from one feedthrough input pin to one feedthrough output pin of the ith sub-design,

the plurality of interactive elements in the ith sub-design further comprise the at least one feedthrough connection network, the at least one feedthrough input pin, and the at least one feedthrough output pin.

4. The signal line electromigration inspection method of claim 1, wherein generating a plurality of boundary model files in one-to-one correspondence with the plurality of sub-designs comprises:

acquiring a plurality of description files corresponding to the plurality of sub-designs one by one;

and generating the plurality of boundary model files based on a plurality of description files in one-to-one correspondence with the plurality of sub-designs.

5. The signal line electromigration inspection method of claim 4, wherein generating the plurality of boundary model files based on a plurality of description files that are in one-to-one correspondence with the plurality of sub-designs comprises:

for each sub-design:

and deleting the description information corresponding to the elements in each sub-design except for the plurality of interactive elements in each sub-design from the description file corresponding to each sub-design to obtain a boundary model file corresponding to each sub-design.

6. The signal line electromigration inspection method of claim 1, wherein generating a plurality of boundary model files in one-to-one correspondence with the plurality of sub-designs comprises:

for each sub-design:

and obtaining the description information of the plurality of interactive elements in each sub-design to obtain a boundary model file corresponding to each sub-design.

7. The signal line electromigration inspection method as set forth in any one of claims 1 to 6, further including:

obtaining a plurality of description files corresponding to the plurality of sub-designs respectively;

and performing signal line electromigration check on each sub-design based on the description file corresponding to each sub-design.

8. The signal line electromigration check method according to claim 7, wherein the description file corresponding to the top-level design is configured to be able to call a plurality of description files corresponding to the plurality of sub-designs respectively.

9. The signal line electromigration test method as set forth in any of claims 1 to 6, wherein the description file corresponding to the top-level design is a design exchange format file.

10. A signal line electro-migration inspection device is applied to an integrated circuit design, wherein the integrated circuit design comprises a top layer design and a plurality of sub-designs,

the signal line electromigration inspection apparatus includes:

an acquisition unit configured to acquire a description file corresponding to the top-level design;

a generating unit, configured to generate a plurality of boundary model files in one-to-one correspondence with the plurality of sub-designs, wherein each boundary model file includes description information of a plurality of interactive elements in the sub-design corresponding to the boundary model file, and the plurality of interactive elements are used for realizing interaction between the sub-design and the top-level design and/or the sub-design in the plurality of sub-designs except the sub-design corresponding to the boundary model file;

and the checking unit is configured to perform signal line electromigration check on the top-level design based on the plurality of boundary model files and the description file corresponding to the top-level design.

11. An electronic device, comprising:

a memory non-transiently storing computer-executable instructions;

a processor configured to execute the computer-executable instructions,

wherein the computer-executable instructions, when executed by the processor, implement the signal line electromigration check method of any of claims 1 to 9.

12. A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions that, when executed by a processor, implement the signal line electromigration inspection method according to any one of claims 1 to 9.

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