CN112100952A - Post-simulation method and device for integrated circuit, electronic equipment and storage medium - Google Patents

Abstract

The present application relates to an integrated circuit post-emulation method, device, electronic device and storage medium, and belongs to the technical field of integrated circuit design. The method includes: obtaining simulation parameters including a netlist required for the respective simulation of the top layer and each sub-module in the integrated circuit to be subjected to post-simulation, wherein the netlists corresponding to the top layer and each sub-module are independent and different from each other; For each sub-module, the sub-module is post-simulated by using the simulation parameters corresponding to the sub-module to obtain the corresponding simulation results, and the top layer is post-simulated by using the simulation parameters corresponding to the top layer to obtain the simulation results of the top layer. Since the top layer and each sub-module are based on their independent netlists during post-simulation, by splitting the original overall simulation, each part can be simulated in parallel, which significantly improves the post-simulation speed of the chip, making the The correctness of timing function can be fully verified before chip tape out, thereby reducing chip cost.

Description

A kind of integrated circuit post-simulation method, device, electronic device and storage medium

technical field

The present application belongs to the technical field of integrated circuits, and in particular relates to a post-emulation method, device, electronic device and storage medium of an integrated circuit.

Background technique

With the development of microelectronics design technology, the scale and logic complexity of its circuit design are also increasing day by day, which leads to the increasing time spent by integrated circuit design tools, which makes the hierarchical design process emerge as the times require. The so-called hierarchical design process refers to dividing the entire design object into multiple sub-modules for hierarchical design, so as to divide the huge workload into several parts and carry out the design at the same time, and finally combine the design of each sub-module with the top layer, to save time spent running and modifying the tool. In the process of design, it is necessary to consider the relationship between each level, such as the relationship between the top level and each bottom level sub-module, the optimization within the level, etc., so that each module can meet its own design requirements and meet the top-level design requirements at the same time.

Among them, in the design process of integrated circuits, simulation and verification are an important link, and it is an indispensable link to check whether the circuits involved meet the requirements. Simulation can be divided into pre-function simulation and post-sequence simulation. A complete circuit design process should include two processes: pre-function simulation and post-sequence simulation. The pre-function simulation is the simulation for the register transfer level (RTL), the goal is to analyze the correctness of the logic relationship of the circuit, and the simulation speed is fast. Post-sequential simulation is the simulation of the gate-level netlist, which takes into account the gate delay parameters of the circuit and the connection between various circuit units and simulates. The result can determine whether the timing is correct, and the simulation result directly affects the function power consumption assessment, accuracy of IR drop analysis, etc.

For post-sequential simulation, the traditional approach is to put the entire gate-level netlist into the simulation environment of the System On Chip (SOC) for simulation, and read in the Standard Delay Format (SDF) during simulation. , modify the simulation environment of part of the SOC, and judge whether the simulation is correct by applying excitation and monitoring the output and internal signals of the netlist. Although this method can handle small and medium-scale circuits well, it has the problem of long simulation time when dealing with super-large-scale simulation circuits, which makes it impossible to provide a fast signal database (FSDB) before chip tape out (Fast SignalDatabase, FSDB). file for accurate power consumption evaluation and IR drop analysis, which leads to the need to leave enough margin in the back-end implementation, which indirectly affects the cost of the chip.

SUMMARY OF THE INVENTION

In view of this, the purpose of the present application is to provide an integrated circuit post-simulation method, device, electronic device and storage medium, so as to improve the existing post-simulation method for post-simulation of large-scale integrated circuits, which has the problem of long simulation time.

The embodiments of the present application are implemented as follows:

In a first aspect, an embodiment of the present application provides a method for post-simulation of an integrated circuit, including: acquiring simulation parameters including a netlist required for the respective simulations of the top layer and each sub-module in the integrated circuit to be post-simulated, wherein, The netlists corresponding to the top layer and each sub-module are independent and different from each other; for each sub-module, use the simulation parameters corresponding to the sub-module to perform post-simulation on the sub-module to obtain the corresponding simulation results and the fast signal database FSDB file, and performing post-simulation on the top layer by using the simulation parameters corresponding to the top layer to obtain the simulation result and FSDB file of the top layer. In this embodiment of the present application, when performing post-simulation, the top-level post-simulation is performed by obtaining the simulation parameters including the netlist required for the top-level simulation, and the pair of simulation parameters including the netlist required for the sub-module simulation is obtained. This sub-module performs post-simulation. Since the top-level and each sub-module are based on their independent netlists during post-simulation (so that each sub-module and top-level can be simulated in parallel), by splitting the original overall simulation, After splitting, each part can be simulated in parallel, which significantly improves the post-simulation speed of the chip and shortens the post-simulation time, so that the correctness of timing functions can be fully verified before the chip is taped out, and an accurate FSDB file can be generated for subsequent process analysis. The margin reserved in the design, thereby reducing the cost of the chip.

With reference to a possible implementation of the embodiment of the first aspect, the step of acquiring simulation parameters including a netlist required for the respective simulation of each submodule includes: for each submodule, acquiring the module test corresponding to the submodule file, input excitation and output reference value, module netlist and module standard delay format SDF file; correspondingly, use the simulation parameters corresponding to the submodule to simulate the submodule, including: The module test file is compiled to generate an executable file of the simulation circuit; according to the SDF file, the delay information of the connection between the standard unit and the standard unit is reversed in the simulation circuit, and run; in the process of running, the input The excitation is loaded into each input pin of the simulation circuit, and the value output by the simulation circuit is compared with the corresponding output reference value to obtain the corresponding simulation result and the FSDB file. In the embodiment of the present application, the simulation is performed by acquiring the simulation parameters including the module test file, input excitation and output reference value, module netlist, and module SDF file corresponding to each sub-module, while ensuring that the simulation can be performed normally, It can also simulate each sub-module in parallel. Compared with the traditional overall simulation, the simulation time is significantly shortened due to the smaller scale of the simulation circuit.

With reference to a possible implementation of the embodiment of the first aspect, the step of acquiring the module test file, input excitation and output reference value corresponding to the sub-module includes: acquiring the netlist of the integrated circuit, the standard parasitic parameter exchange format SPEF file, standard design constraint SDC constraint file, register transfer level RTL code and pre-simulation test case; according to the netlist of the integrated circuit, the SPEF file, and the SDC constraint file, the module test file corresponding to the sub-module and A script for grabbing the input excitation and output reference value of the submodule; using the script grabbing the input excitation and output reference value of the submodule to obtain the data generated when the RTL code runs the pre-simulation test case, The input excitation and output reference values of the sub-module are obtained. In the embodiment of the present application, according to the obtained netlist, SPEF file, SDC constraint file, RTL code and pre-simulation test case, the corresponding module test file, input stimulus and output reference value of each sub-module can be quickly obtained. The parameters required in the simulation of each sub-module are separated, so that the simulation of the module can be parallelized, thereby improving the simulation efficiency.

With reference to a possible implementation of the embodiment of the first aspect, the step of acquiring simulation parameters including a netlist required for the respective simulation of each submodule includes: for each submodule, acquiring the module test corresponding to the submodule file, register scan chain information, input excitation and output reference values, module netlist, and module SDF file, wherein the register scan chain information includes each register in the submodule extracted in the order of the scan test chain at a specified time. register value; correspondingly, using the simulation parameters corresponding to the submodule to simulate the submodule, including: compiling the module netlist and the module test file to generate a simulation circuit executable file; according to the module SDF file In the simulation circuit, the delay information of the connection between the standard unit and the standard unit is reversed, and the registers in the simulation circuit are assigned values according to the register scan chain information, and run; The input excitation is loaded into each input pin of the simulation circuit, and the value output by the simulation circuit is compared with the corresponding output reference value to obtain the corresponding simulation result and FSDB file. In the embodiments of the present application, the module test files, register scan chain information, input excitation and output reference values, module netlists, and module SDF files required for the respective simulation of each sub-module are obtained, so as to ensure that the simulation can be performed normally, and at the same time Simulate each sub-module in parallel, and at the same time, assign a value to the register in the simulation circuit through the register scan chain information (including the register value at the specified time extracted from each register in the sub-module in the order of scanning the test chain), to By skipping the initialization, the initialization time can be saved, thereby further improving the simulation efficiency.

With reference to a possible implementation of the embodiment of the first aspect, the step of acquiring the module test file, register scan chain information, input excitation and output reference value corresponding to the sub-module includes: acquiring the netlist, SPEF of the integrated circuit file, SDC constraint file, RTL code and pre-simulation test case; according to the netlist of the integrated circuit, the SPEF file, and the SDC constraint file, the module test file corresponding to the sub-module is obtained, which is used to capture the sub-module The script of input excitation and output reference value at the specified time of the module, and according to the netlist of the integrated circuit and the SDC constraint file, the script for grabbing the register scan chain information at the designated time of the sub-module is obtained; using grabbing The script of the input stimulus and output reference value at the specified time of the sub-module obtains the data generated when the RTL code runs the pre-simulation test case, obtains the input stimulus and output reference value at the specified time of the sub-module, and uses The script that captures the register scan chain information at the specified time of the submodule obtains the register value at the specified time generated when the RTL code runs the pre-simulation test case, and obtains the register scan chain information at the specified time of the submodule. In the embodiment of the present application, according to the acquired netlist, SPEF file, SDC constraint file, RTL code and pre-simulation test case, the corresponding module test file, register scan chain information, input stimulus and Output the reference value. By obtaining the simulation parameters of each sub-module, the simulation is parallelized, thereby improving the simulation efficiency. At the same time, the register scan chain information is used to assign values to the registers during simulation to skip initialization, which can further improve the simulation efficiency. .

With reference to a possible implementation of the embodiment of the first aspect, the step of acquiring simulation parameters including a netlist required for the top-level simulation includes: acquiring a top-level test file of the top-level, input excitations of all submodules and output reference value, top-level netlist and top-level SDF file; correspondingly, using the simulation parameters corresponding to the top-level to perform post-simulation on the top-level, including: compiling the top-level netlist and the top-level test file to generate a simulation The circuit executable file; according to the top-level SDF file, the delay information of the connection between the standard unit and the standard unit in the simulation circuit is reversed and run; in the process of running, the input excitation of all the sub-modules is loaded to each input pin of the simulation circuit, and compare the output value of the simulation circuit with the corresponding output reference value to obtain the corresponding simulation result and the FSDB file. In the embodiment of the present application, the top-level post-simulation is performed by acquiring the top-level test files required for the top-level simulation, the input excitation and output reference values of all submodules, the top-level netlist, and the top-level SDF file. Relationships are also taken into account, ensuring the correctness of the top-level simulation.

With reference to a possible implementation of the embodiment of the first aspect, the step of acquiring the top-level test file of the top-level, input excitations and output reference values of all sub-modules includes: acquiring the netlist of the integrated circuit, the SPEF file, SDC constraint file, RTL code and pre-simulation test case; according to the netlist of the integrated circuit, the SPEF file, and the SDC constraint file, a script for capturing the input excitation and output reference values of all sub-modules is obtained and the The respective input and output IO delay signals and corresponding clock domain signals of each sub-module; according to the respective IO delay signals and corresponding clock domain signals of each sub-module, the top-level test file for controlling the simulation process is generated; The RTL code and the data generated when the pre-simulation test case is run are obtained by using the script that captures the input excitation and output reference values of all submodules, and the input excitation and output reference values of all the submodules are obtained. In the embodiment of the present application, according to the acquired netlist of the integrated circuit, the SPEF file, and the SDC constraint file, a script for capturing the input excitation and output reference values of all submodules and the respective IO delay signals of each submodule are obtained and the corresponding clock domain signal, and then generate the top-level test file for controlling the simulation process according to the respective IO delay signal of each sub-module and the corresponding clock domain signal, and capture the input excitation and output reference of all sub-modules To obtain the RTL code and the data generated when running the pre-simulation test case, the input excitation and output reference values of all sub-modules can be obtained, because the parameters required for the top-level simulation are a combination of the The input excitation and output reference values of each sub-module, as well as the respective IO delay signals and corresponding clock domain signals of each sub-module, ensure the correctness of the top-level simulation. In addition, after obtaining the respective input excitation and output reference values of each sub-module Values and IO delay signals and corresponding clock domain signals, the parameters required for the top-level simulation can be obtained without additional time.

In a second aspect, an embodiment of the present application further provides an integrated circuit post-simulation device, including: an acquisition module and a simulation module; and an acquisition module for acquiring the respective simulation requirements of the top layer and each sub-module in the integrated circuit to be post-simulated The simulation parameters including the netlist, wherein the netlists corresponding to the top layer and each submodule are independent and different from each other; the simulation module is used for each submodule to use the simulation parameters corresponding to the submodule to the submodule. The module performs post-simulation to obtain corresponding simulation results and FSDB files, and uses the simulation parameters corresponding to the top-level to perform post-simulation on the top-level to obtain the top-level simulation results and FSDB files.

In combination with a possible implementation of the embodiment of the second aspect, an acquisition module is used to acquire, for each submodule, the module test file, input excitation and output reference value, module netlist, and module SDF file corresponding to the submodule; Correspondingly, the simulation module is used for: compiling the module netlist and the module test file to generate a simulation circuit executable file; according to the module SDF file, back-marking the connection between the standard unit and the standard unit in the simulation circuit; Line delay information, and run; in the process of running, load the input excitation to each input pin of the simulation circuit, and compare the output value of the simulation circuit with the corresponding output reference value to obtain the corresponding output value. The simulation results and FSDB files.

In combination with a possible implementation of the embodiment of the second aspect, an acquisition module is specifically configured to: acquire the netlist, SPEF file, SDC constraint file, RTL code, and pre-simulation test case of the integrated circuit; Netlist, described SPEF file, described SDC constraint file, obtain the module test file corresponding to this submodule and the script for capturing the input excitation and output reference value of this submodule; utilize the input of capturing this submodule The script of excitation and output reference value acquires the data generated when the RTL code runs the pre-simulation test case, and obtains the input excitation and output reference value of the sub-module.

In combination with a possible implementation of the embodiment of the second aspect, an acquisition module is configured to acquire, for each submodule, the module test file, register scan chain information, input excitation and output reference values, module netlist, and Module SDF file; correspondingly, the simulation module is used for: compiling the module netlist and the module test file to generate a simulation circuit executable file; back-marking standard cells and standard cells in the simulation circuit according to the module SDF file The delay information of the connection between the two, and assign values to the registers in the simulation circuit according to the register scan chain information, and run; in the process of running, load the input excitation to each input of the simulation circuit pin, and compare the output value of the simulation circuit with the corresponding output reference value to obtain the corresponding simulation result and FSDB file.

In combination with a possible implementation of the embodiment of the second aspect, an acquisition module is specifically configured to: acquire the netlist, SPEF file, SDC constraint file, RTL code, and pre-simulation test case of the integrated circuit; The netlist, the SPEF file, the SDC constraint file, obtain the module test file corresponding to the sub-module, the script for capturing the input excitation and output reference value at the specified time of the sub-module, and according to the integrated circuit The netlist and the SDC constraint file are used to capture the script of the register scan chain information at the specified moment of the submodule; use the script of capturing the input excitation and output reference value of the submodule to obtain the RTL code to run the described RTL code. The data generated during the pre-simulation test case, obtain the input excitation and output reference value at the specified time of the sub-module, and use the script that grabs the register scan chain information of the sub-module to obtain the RTL code to run the described The register value at the specified time generated during the previous simulation test case is obtained, and the register scan chain information at the specified time of the submodule is obtained.

In combination with a possible implementation of the embodiment of the second aspect, an acquisition module is used to acquire the top-level test file of the top-level, the input excitation and output reference values of all sub-modules, the top-level netlist, and the top-level SDF file; accordingly, The simulation module is used for: compiling the top-level netlist and the top-level test file to generate a simulation circuit executable file; according to the top-level SDF file, the extension of the connection between the standard cell and the standard cell in the simulation circuit is reversed. In the process of running, the input excitation of all the sub-modules is loaded into each input pin of the simulation circuit, and the value output by the simulation circuit is compared with the corresponding output reference value to obtain Corresponding simulation results and FSDB files.

In combination with a possible implementation of the embodiment of the second aspect, an acquisition module is specifically configured to: acquire the netlist, SPEF file, SDC constraint file, RTL code, and pre-simulation test case of the integrated circuit; The netlist, the SPEF file, the SDC constraint file, obtain the script for capturing the input excitation and output reference value of all submodules and the respective IO delay signals and corresponding clock domain signals of each submodule; according to The respective IO delay signal of each submodule and the corresponding clock domain signal generate the top-level test file used to control the simulation process; use the script to capture the input excitation and output reference value of all submodules to obtain The RTL code and the data generated when the pre-simulation test case is run are used to obtain input excitation and output reference values of all the submodules.

With reference to a possible implementation manner of the embodiment of the second aspect, a simulation module is used to perform post-simulation of the sub-module by using the simulation parameters corresponding to the sub-module to obtain corresponding simulation results and FSDB files.

With reference to a possible implementation manner of the embodiment of the second aspect, a simulation module is configured to perform post-simulation on the top layer by using the simulation parameters corresponding to the top layer to obtain the simulation result and FSDB file of the top layer.

In a third aspect, an embodiment of the present application further provides an electronic device, including: a memory and a processor, the processor is connected to the memory; the memory is used to store a program; the processor is used to call The program stored in the memory is used to execute the above-mentioned embodiment of the first aspect and/or the method provided in combination with any possible implementation manner of the embodiment of the first aspect.

In a fourth aspect, an embodiment of the present application further provides a storage medium on which a computer program is stored, and when the computer program is run by a processor, executes the above-mentioned first aspect embodiment and/or combines the first aspect embodiment. The method provided by any of the possible implementations.

Other features and advantages of the present application will be set forth in the description which follows, and, in part, will be apparent from the description, or may be learned by practice of the embodiments of the present application. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and drawings.

Description of drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the accompanying drawings required in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some of the present application. In the embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort. The above and other objects, features and advantages of the present application will be more apparent from the accompanying drawings. The same reference numerals refer to the same parts throughout the drawings. The drawings are not intentionally scaled to actual size, and the emphasis is on illustrating the subject matter of the present application.

FIG. 1 shows a schematic structural diagram of a method for post-simulation of an integrated circuit provided by an embodiment of the present application.

FIG. 2 shows a schematic diagram of a principle of acquiring a test file, input excitation, and output reference value provided by an embodiment of the present application.

FIG. 3 shows a schematic diagram of a principle of acquiring a test file, register scan chain information, input excitation, and output reference value provided by an embodiment of the present application.

FIG. 4 shows a schematic schematic diagram of a method for post-simulation of an integrated circuit provided by an embodiment of the present application.

FIG. 5 shows a schematic block diagram of an integrated circuit post-emulation device provided by an embodiment of the present application.

FIG. 6 shows a schematic structural diagram of an electronic device provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures. Meanwhile, in the description of this application, relational terms such as "first", "second", etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or that there is any such actual relationship or sequence between operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Furthermore, the term "and/or" in this application is only an association relationship to describe related objects, indicating that there can be three kinds of relationships, for example, A and/or B, it can mean that A exists alone, and A and B exist at the same time. B, there are three cases of B alone.

Aiming at the traditional post-simulation method for post-simulation of large-scale integrated circuits, there is a problem of long simulation time, which makes it impossible to provide a Fast Signal Database (FSDB) file before the chip is taped out, so as to perform accurate functions. Consumption assessment and analysis of IR drop lead to the need to leave enough margin in the back-end implementation, which indirectly affects the cost of the chip. Based on this, the embodiments of the present application provide a method for post-simulation of integrated circuits, so as to speed up the simulation speed and solve the problems of slow post-simulation of large-scale integrated circuits and difficulty in post-simulation for ultra-large-scale integrated circuits in existing methods. For ease of understanding, The following describes the integrated circuit post-simulation method provided by the embodiment of the present application with reference to FIG. 1 .

Step S101 : acquiring simulation parameters including a netlist required for the respective simulations of the top layer and each sub-module in the integrated circuit to be subjected to post-simulation.

When the integrated circuit to be post-simulated needs to be simulated, the simulation parameters including the netlist required for the respective simulation of the top layer and each sub-module (Tile) in the integrated circuit to be post-simulated are obtained. Among them, post-simulation is the simulation of the gate-level netlist, which takes into account the gate delay parameters of the circuit and the connection between various circuit units and then simulates. The results can determine whether the timing is correct, and the simulation results directly affect Power consumption assessment, accuracy of IR drop analysis, etc.

Among them, it should be noted that the netlists corresponding to the top layer and each submodule are independent and different from each other, that is, the netlist required by the top layer during post-simulation and the netlist required by each submodule during post-simulation. The tables are independent and different from each other, and the netlists required for post-simulation between submodules are also independent and different from each other. For example, the netlist required for submodule A simulation and the netlist required for submodule B simulation Tables are independent and not the same. Since the post-simulation of the top-level and each sub-module is performed based on their independent netlists, rather than the post-simulation based on the netlist of the entire integrated circuit, the top-level and each sub-module can be post-simulated in parallel, which speeds up the simulation speed. . Among them, in view of the increasing scale of integrated circuits, the overall back-end implementation is often time-consuming or even impossible to achieve. Therefore, the current large-scale chip design and implementation process is a top-down and bottom-up process. Usually, the chips divided by function are divided into tiles (tiles) from top to bottom according to their physical locations (that is, a large physically achievable module is formed by combining physically similar modules according to data flow and function), so that the The entire chip is divided into multiple physically achievable tiles and top layers. After the division, each tile and top layer have fewer logic gates, which makes physical implementation possible. After each tile and top layer complete the physical implementation, the final result of each part is obtained. The netlist is then combined from bottom to top to form the netlist of the entire chip. Finally, various inspections (including timing acceptance, physical verification, post-gate-level netlist simulation, etc.) are completed on the netlist. piece.

In one embodiment, the simulation parameters required for the simulation of each sub-module include, in addition to the module netlist corresponding to the sub-module, the corresponding module test file (test bench), input stimulus (input pattern) and output reference value (output pattern) and module standard delay format (Standard Delay Format, SDF) file, that is, for each submodule, the simulation parameters required for the simulation include: the module test file, input stimulus and output corresponding to the submodule References, block netlists, and block SDF files. The simulation parameters required for the simulation of each sub-module include the same parameter types and different specific parameter values.

Among them, the module netlist of each submodule and the module SDF file can be obtained when the submodule's respective physical implementation is completed in the hierarchical design stage.

Wherein, the process of obtaining the module test file, input excitation and output reference value corresponding to each sub-module may be: first obtain the netlist of the integrated circuit, the standard parasitic parameter exchange format (Standard Parasitic ExchangeFormat, SPEF) file (for integrated circuit design Standard media file for transferring interconnect parasitic parameters between EDA tools in the process), Standard Design Constraints (SDC) file (the constraint file in the design, which constrains the timing, area, and power consumption of the circuit, determines the The specification of whether the chip meets the design requirements), Register Transfer Level (RTL) code and pre-simulation test cases, and then based on the acquired integrated circuit netlist, SPEF file, SDC constraint file, RTL code and pre-simulation test Use case, the module test file, input stimulus and output reference value corresponding to each sub-module can be obtained, that is, according to the netlist, SPEF file, and SDC constraint file of the integrated circuit, the module test file corresponding to the sub-module and the output reference value can be obtained. The script to capture the input excitation and output reference value of the submodule; obtain the input excitation and output reference value of the submodule according to the script, RTL code and pre-simulation test case for capturing the input excitation and output reference value of the submodule .

Optionally, according to the netlist, SPEF file, and SDC constraint file of the integrated circuit, the process of obtaining the module test file corresponding to the submodule and the script for capturing the input excitation and output reference value of the submodule may be: first. According to the SPEF file and SDC constraint file of the integrated circuit, calculate the respective IO (input input, output out) interface signals, corresponding clock domain signals and IO delay signals of each sub-module in the integrated circuit's netlist, and then according to each sub-module The corresponding IO delay signal and clock domain signal generate the module test file corresponding to the sub-module for controlling the simulation process, and the corresponding IO interface signal and clock domain signal for each sub-module are generated to capture the sub-module. Scripts for the input stimulus and output reference of the module.

According to the script, RTL code and pre-simulation test case for capturing the input stimulus and output reference value of the submodule, the process of obtaining the input stimulus and output reference value of the submodule can be as follows: using the capture input stimulus and output reference value of the submodule The script that outputs the reference value obtains the data generated when the test case is simulated before the RTL code runs, and then the input stimulus and output reference value of the sub-module can be obtained.

For ease of understanding, the process of how to obtain the module test file, input excitation and output reference value corresponding to each sub-module will be described with reference to FIG. 2 . The process can be divided into two parts, A and B. In Part A, input the netlist, SPEF file, and SDC constraint file of the integrated circuit into the Electronic Design Automation (EDA) tool (such as prime time), and cooperate with the script (the script finds the first one below the top level through the built-in command of the tool) The module name of each sub-module of the hierarchy, the input/output port of the sub-module, and the clock and IO delay information corresponding to the input/output port, and the subsequent files required for each sub-module simulation are generated one by one according to this information. It can output the corresponding block test files (including multiple) of each sub-module for controlling the simulation process, the script for capturing the input excitation and output reference value of each sub-module, and the respective IO delay of each sub-module. time signals and corresponding clock domain signals (used to generate top-level test files required for top-level simulation). Among them, after using the EDA tool to read the netlist, SPEF file, and SDC constraint file of the integrated circuit, the tool will automatically calculate the input and output pins of each sub-module in the netlist, obtain the IO interface signals of each sub-module, and calculate delay information of the standard cell (cell) in each submodule and the connection (net) between the standard cells, and extract the delay information of each pin in the current environment to obtain the corresponding IO delay signal of each submodule, and You can also query the clock domain where each input and output pin is located to obtain the corresponding clock domain signal of each sub-module. For each sub-module, after obtaining the IO interface signal, the corresponding clock domain signal and the IO delay signal of the sub-module, the corresponding IO delay signal and clock domain signal are generated to control the simulation process. The active module test file generates a script for capturing the respective input excitation and output reference value of the submodule according to the IO interface signal and the clock domain signal.

After obtaining the script used to capture the input and output patterns of each submodule, use the script to obtain the data generated when the RTL code is run before the simulation test case (that is, the test case used in the pre-simulation of the integrated circuit), The input excitation and output reference value of each sub-module can be obtained. That is, the top-level pre-simulation environment in Part B reads the script files, RTL codes and pre-simulation test cases used to capture the respective input excitation and output reference values of each sub-module to run the simulation. After the simulation is completed, you can get Input stimulus and output reference for each submodule. Among them, after the simulation clock is generated, the script can sample the input and output port signals on the rising edge of the clock and output it to the file, that is, when the rising edge of the clock is running normally, it will simulate all the test cases before running the RTL code. The input and output port signals of the sub-module are captured and stored as a post-imitation pattern file to obtain the input pattern and output pattern.

Among them, the module test file (test bench) is used to control the simulation process, including IO delay signal, input stimulus, output comparison and other indication information, such as instructing what the module simulation environment needs to do during simulation, such as instructing its The module netlist needs to be instantiated, the input excitation needs to be turned on, and the output comparison needs to be done (that is, the simulation output is compared with the output pattern), etc.

As another implementation manner, the simulation parameters required for the simulation of each sub-module include, in addition to the module netlist corresponding to the sub-module, the corresponding module test file (test bench), register scan chain information (including The value of the register at the specified time extracted from the sequence of the scan test), the input stimulus (input pattern), the output reference value (output pattern), and the module standard delay format (Standard Delay Format, SDF) file, that is, for each sub The simulation parameters required for the simulation include: the module test file corresponding to the sub-module, the register scan chain information, the input excitation and output reference values, the module netlist, and the module SDF file.

The step of obtaining the module test file, register scan chain information, input excitation and output reference value corresponding to the sub-module may be: obtaining the module test file corresponding to the sub-module according to the netlist, SPEF file, and SDC constraint file of the integrated circuit file, the script used to capture the input excitation and output reference value at the specified time of the submodule, and the register scan used to capture the specified time of the submodule according to the netlist of the integrated circuit and the SDC constraint file The script of the chain information; according to the script, RTL code and pre-simulation test case that captures the input stimulus and output reference value at the specified time of the submodule, the input stimulus and output reference value at the specified time of the submodule are obtained (that is, using the capture The script of the input stimulus and output reference value of the specified time block of the submodule captures the specified time data generated when the RTL code is run before simulating the test case, and obtains the input stimulus and output reference value at the specified time of the submodule), and according to the capture Take the script, RTL code and pre-simulation test case of the register scan chain information at the specified time of the submodule, and obtain the register scan chain information at the specified time of the submodule (that is, use the method of capturing the register scan chain information at the specified time of the submodule). The script grabs the value of the register at the specified time generated when the test case is simulated before the RTL code runs, and extracts it in the order of the scan test to obtain the register scan chain information at the specified time of the submodule). The schematic diagram of the principle of this embodiment is shown in FIG. 3 . Compared with the embodiment shown in FIG. 2 , it is equivalent to additionally outputting the register scan chain information used to capture the register scan chain information at the specified time of the sub-module on the original basis of Part A. Script, and input the script into part B, in order to use the script to obtain the specified time generated when the RTL code is simulated before the test case is run (the value of each register, the register scan chain information of each submodule can be obtained, where, After the EDA tool (such as prime time) reads the netlist and SDC, the chip is set to test mode, each tile has an independent scan chain, and the next input pin driven by the pin is tracked through the known scan chain input pin of each tile. stage register, and then trace from the output pin of the next stage drive register to the next stage drive register, trace step by step until reaching the output pin of the scan chain of the tile, then record the sequence of the scan chain, and generate in this order Script to capture scan chain information. That is, in part A, after inputting the netlist, SPEF file, and SDC constraint file of the integrated circuit into the EDA tool, set the chip to test mode, and the EDA tool can automatically generate the scan chain information. The script to take the respective register scan chain information (scan chain, the chain formed by stringing the registers together during the chip scan test) at the specified time of each submodule. This script is used to simulate the test case before the RTL runs. The values of the registers are extracted in the order of the scan test. In part B, the top-level pre-simulation environment reads in the script file used to capture the input stimulus and output reference value of each sub-module at the specified time, and captures the respective registers of each sub-module The script, RTL code and pre-simulation test case of the scan chain information run the simulation, and after the simulation is finished, the input excitation and output reference values of each sub-module after the specified time can be obtained, as well as the register scan chain information at the specified time. , in order to avoid redundancy, the part that is not described in this embodiment, please refer to the same part in the implementation shown in Figure 2. Wherein, the register scan chain information is used in simulation, at a specific moment (such as about to be loaded in the simulation process) When inputting excitation) assign values to all registers in the order of scan chain to skip initialization, thereby speeding up the simulation. Among them, the module test file and module pattern in Figure 2 and Figure 3 (that is, input pattern, output pattern) , and the module scan chain in FIG. 3 is represented by a dashed box, which indicates that the number is multiple.

Among them, the simulation parameters required for the top-level simulation include, in addition to the top-level netlist, the top-level test file, the input excitation and output reference values of all sub-modules, and the top-level SDF file, that is, the simulation parameters required for the top-level simulation include: Test files, input stimuli and output references for all submodules, top-level netlist, and top-level SDF files. Among them, the top-level top-level netlist and the top-level SDF file can be obtained when the top-level physical implementation is completed in the hierarchical design stage of the integrated circuit.

Among them, the process of obtaining the top-level top-level test file, the input excitation and output reference values of all sub-modules may be to obtain the netlist of the integrated circuit, the SPEF file, the SDC constraint file, the RTL code and the pre-simulation test case, and then according to the obtained integration The netlist, SPEF file, SDC constraint file, RTL code and pre-simulation test case of the circuit can obtain the top-level top-level test file, the input excitation and output reference values of all sub-modules, that is, according to the netlist of the integrated circuit, SPEF file, SDC constraint file, get the script used to capture the input excitation and output reference value of all sub-modules, as well as the respective IO delay signals and corresponding clock domain signals of each sub-module; according to the respective IO delay signals of each sub-module and the corresponding clock domain signal to generate a top-level test file for controlling the simulation process; according to the script, RTL code and pre-simulation test case that captures the input stimulus and output reference value of all sub-modules, the input of all sub-modules is obtained Excitation and output reference values. For example, according to the SPEF file and SDC constraint file of the integrated circuit, calculate the respective IO interface signals, corresponding clock domain signals and IO delay signals of each sub-module in the integrated circuit's netlist, and then calculate the respective IO interface signals of each sub-module according to the respective IO interface signals. and the corresponding clock domain signal, generate a capture script for capturing the input excitation and output reference value of all sub-modules, and finally generate a simulation based on the respective IO delay signals and corresponding clock domain signals of each sub-module. The top-level test file that controls the flow, and the data generated when the RTL code is simulated before the execution of the RTL code is obtained by using the grab script, and the input stimulus and output reference value of all sub-modules can be obtained.

The process of obtaining the top-level top-level test file, input excitation and output reference value of all sub-modules is described in conjunction with the above-mentioned Figure 2. In part A, the integrated circuit netlist, SPEF file, and SDC constraint file are input into the EDA tool, and cooperate with Script processing (the script finds the module name of each sub-module at the first level below the top level, the input/output port of the sub-module, and the clock and IO delay information corresponding to the input/output port through the built-in command of the tool, and according to the information The subsequent files required for the simulation of each sub-module are generated one by one, and the corresponding module test files (including multiple) for controlling the simulation process, the input excitation and The script that outputs the reference value and the respective IO delay signals of each sub-module and the corresponding clock domain signals (including multiple). That is to say, after using the EDA tool to read in the netlist SPEF file and SDC constraint file of the integrated circuit, the tool will automatically calculate the input and output pins of each submodule in the netlist, obtain the respective IO interface signals of each submodule, and calculate The delay information of the standard unit (cell) in each sub-module and the connection (net) between the standard units, and the delay information of each pin in the current environment is extracted to obtain the corresponding IO delay signal of each sub-module, In addition, the clock domain where each input and output pin is located can be queried to obtain the corresponding clock domain signal of each sub-module. For each sub-module, after obtaining the IO interface signal, the corresponding clock domain signal and the IO delay signal of the sub-module, the corresponding IO delay signal and clock domain signal are generated to control the simulation process. The active module test file generates a script for capturing the respective input excitation and output reference value of the submodule according to the IO interface signal and the clock domain signal. In part B, the scripts, RTL codes and pre-simulation test cases used to capture the input and output patterns of each sub-module, as well as the respective IO interface signals and corresponding clock domain signals of each sub-module, are input into the top-level front of part B. By simulating in the simulation environment, the input and output patterns and top-level test files of each sub-module can be obtained. That is, the top-level pre-simulation environment in Part B reads the script files, RTL codes and pre-simulation test cases used to capture the input stimulus and output reference value of each sub-module to run the simulation. Input stimulus and output reference for the submodule. Generate a top-level test file for controlling the simulation process according to the obtained IO delay signals and corresponding clock domain signals of each sub-module. For example, use the input IO interface signals and corresponding clock domain signals of each sub-module. Signal, modify the top-level pre-simulation environment, add patterns to read in, output signal comparison, etc., and generate top-level test files.

Step S102: for each sub-module, use the simulation parameters corresponding to the sub-module to perform post-simulation on the sub-module, obtain corresponding simulation results and FSDB files, and use the simulation parameters corresponding to the top-level to perform post-simulation on the top-level , to get the top-level simulation results and FSDB files.

After obtaining the simulation parameters corresponding to the top layer and each sub-module in the integrated circuit to be post-simulated, for each sub-module, post-simulate the sub-module using the simulation parameters corresponding to the sub-module, and then the corresponding sub-module can be obtained. The simulation result and the FSDB file, and the post-simulation of the top layer by using the simulation parameters corresponding to the top layer, the simulation result and the FSDB file of the top layer can be obtained. By splitting the original overall simulation, each part can be simulated in parallel after splitting, which significantly improves the post-simulation speed of the chip, so that the correctness of timing functions can be fully verified before the chip is taped out, and an accurate FSDB file is generated for Analysis of IR drop, power consumption, etc., thereby reducing chip cost.

Wherein, as an implementation manner, for each submodule, the acquired simulation parameters required for the simulation corresponding to the submodule include: module test file, input excitation and output reference values, module netlist, and module SDF file. Correspondingly, when the sub-module is post-simulated by using the simulation parameters corresponding to the sub-module, the module simulation environment reads the simulation parameter module test file, input excitation and output reference value, module netlist and module SDF file corresponding to the sub-module. Perform post-simulation to obtain simulation results and FSDB files. The process can be that the module simulation environment compiles the module netlist and module test file corresponding to the sub-module to generate the simulation circuit executable file, and then back-labels the standard cell (cell) and the standard cell in the simulation circuit according to the module SDF file. The delay information of the connection (net), and run, in the process of running, load the input excitation to each input pin of the simulation circuit, and compare the output value of the simulation circuit with the corresponding output reference value, Obtain the corresponding simulation results and FSDB files. Wherein, using the simulation parameters corresponding to the sub-module to perform post-simulation on the sub-module, in addition to obtaining the corresponding simulation results, the module fast signal database (FSDB) file can also be obtained, that is, using the simulation parameters corresponding to the sub-module for this sub-module. After the sub-module is simulated, the corresponding simulation results and the module FSDB file are obtained. Among them, the FSDB file is a waveform file format, which is used to record the change of the signal over time for subsequent module power consumption analysis and IR drop analysis.

Wherein, as another implementation manner, for each sub-module, the acquired simulation parameters required for the simulation corresponding to the sub-module include: module test file, register scan chain information, input excitation and output reference values, module netlist and module SDF files. Correspondingly, when the sub-module is post-simulated using the simulation parameters corresponding to the sub-module, the module simulation environment reads the simulation parameters corresponding to the sub-module. The module test file, register scan chain information, input excitation and output reference values, module network The table and module SDF files are post-simulated, and the simulation results and FSDB files are obtained. The process can be that the module simulation environment compiles the module netlist and module test file corresponding to the sub-module to generate the simulation circuit executable file, and then back-labels the standard cell (cell) and the standard cell in the simulation circuit according to the module SDF file. Delay information of the connection (net), and assign values to the registers in the simulation circuit according to the register scan chain information and run, and in the process of running, load the input excitation to each input pin of the simulation circuit , and compare the output value of the simulation circuit with the corresponding output reference value to obtain the corresponding simulation result and FSDB file. The process of initializing based on the reset information in the input excitation can be skipped by assigning values to the registers in the simulation circuit according to the register scan chain information, thereby improving the simulation speed. The reset information in the input excitation is used to reset (initialize) the simulation circuit, and each part operates normally after reset.

The obtained simulation parameters required for the top-level simulation include the top-level test file, input stimulus and output reference values for all submodules, the top-level netlist, and the top-level SDF file. Correspondingly, using the simulation parameters corresponding to the top layer to perform post-simulation on the top layer, which is equivalent to that the top-level simulation environment reads the top-level test file, the input excitation and output reference values of all sub-modules, the top-level netlist and the top-level SDF file for post-simulation, and obtains Top-level simulation results and FSDB files. The process can be that the top-level simulation environment compiles the top-level netlist and the top-level test file to generate a simulation circuit executable file, and then inverses the delay information of the connection between the standard cell and the standard cell in the simulation circuit according to the top-level SDF file, And run, in the process of running, load the input excitation of all sub-modules to each input pin of the simulation circuit, and compare the output value of the simulation circuit with the corresponding output reference value to obtain the corresponding simulation results and FSDB file. Among them, using the simulation parameters corresponding to the top layer to perform post-simulation on the top layer, in addition to obtaining the corresponding top-level simulation results, the top-level fast signal database (FSDB) file can also be obtained. Corresponding top-level simulation results and top-level FSDB files.

The flow chart of the whole simulation process can be illustrated in Figure 4, and the whole process can be summarized as four parts A, B, C and D. Among them, A and B are the simulation preparation stages, which are used to obtain the test files and input excitation and output reference values required by the top-level and each sub-module during post-simulation, that is, to obtain the required simulation values of each sub-module. Module test files, input stimuli, and output references, as well as top-level test files, input stimuli, and output references for all submodules needed to get the top-level simulation. Part C represents the post-simulation process of each sub-module, and part D represents the post-simulation part at the top level. Among them, the corresponding module simulation environments are different when different sub-modules perform post-simulation.

Since the top-level and each sub-module are based on their independent netlists during post-simulation, each sub-module and top-level can be simulated in parallel. (input pattern) and output reference value (output pattern), then use the input pattern of each sub-module as an incentive to perform post-simulation on the sub-module, and evaluate whether the simulation passes by judging the consistency of the output and output pattern of the sub-module, And use the input pattern of each sub-module as an incentive to perform post-simulation on the top layer, and evaluate whether the simulation passes by judging the consistency of the output of the top layer and the corresponding output pattern, so that each sub-module and the top layer can be simulated in parallel, solving large-scale problems. The post-simulation of the integrated circuit is slow, and it is difficult to realize the post-simulation problem on a large scale, and the FSDB file can be quickly generated for power consumption analysis and IR drop analysis.

The embodiment of the present application further provides a post-integrated circuit emulation apparatus 100, as shown in FIG. 5 . The integrated circuit post-simulation apparatus 100 includes: an acquisition module 110 and a simulation module 120 .

The acquisition module 110 is used to acquire simulation parameters including netlists required for the simulation of the top layer and each submodule in the integrated circuit to be post-simulated, wherein the netlists corresponding to the top layer and each submodule are independent and mutually exclusive. different.

The simulation module 120 is used for performing a post-simulation on the sub-module with the simulation parameters corresponding to the sub-module for each sub-module, obtaining corresponding simulation results and FSDB files, and using the simulation parameters corresponding to the top-level to perform a post-simulation on the top-level Perform post-simulation to obtain the top-level simulation result and FSDB file.

Wherein, optionally, the acquisition module 110 is configured to, for each sub-module, acquire the module test file, input excitation and output reference value, module netlist and module SDF file corresponding to the sub-module; correspondingly, the simulation module 120, Used for: compiling the module netlist and the module test file to generate a simulation circuit executable file; according to the module SDF file, the delay information of the connection between the standard unit and the standard unit in the simulation circuit is reversed, and run; in the process of running, load the input excitation to each input pin of the simulation circuit, and compare the output value of the simulation circuit with the corresponding output reference value to obtain the corresponding simulation result and FSDB file .

Optionally, the obtaining module 110 is specifically configured to: obtain the netlist of the integrated circuit, the SPEF file, the SDC constraint file, the RTL code and the pre-simulation test case; according to the netlist of the integrated circuit, the SPEF file, The SDC constraint file, obtains the module test file corresponding to the submodule and the script for grabbing the input excitation and output reference value of the submodule; utilize the script for grabbing the input excitation and output reference value of the submodule to obtain The data generated when the RTL code runs the pre-simulation test case, obtains the input excitation and output reference value of the sub-module.

Optionally, the obtaining module 110 is used to obtain the module test file, register scan chain information, input excitation and output reference value, module netlist and module SDF file corresponding to the submodule for each submodule; accordingly, the simulation module 120 is used for: compiling the module netlist and the module test file to generate a simulation circuit executable file; back-marking the delay information of the connection between the standard unit and the standard unit in the simulation circuit according to the module SDF file , and assign values to the registers in the simulation circuit according to the register scan chain information, and run; in the process of running, the input excitation is loaded into each input pin of the simulation circuit, and the simulation circuit is The output value is compared with the corresponding output reference value, and the corresponding simulation result and FSDB file are obtained.

Optionally, the obtaining module 110 is specifically configured to: obtain the netlist of the integrated circuit, the SPEF file, the SDC constraint file, the RTL code and the pre-simulation test case; according to the netlist of the integrated circuit, the SPEF file, In the SDC constraint file, the module test file corresponding to the submodule, the script for capturing the input excitation and output reference value at the specified time of the submodule, and the netlist of the integrated circuit and the SDC constraint file are obtained. , obtain a script for grabbing the register scan chain information at the specified moment of the submodule; use the script for capturing the input excitation and output reference value at the specified moment of the submodule to obtain the RTL code when running the pre-simulation test case Generated data, obtain the input excitation and output reference value at the specified time of the submodule, and use the script that grabs the register scan chain information at the specified time of the submodule to obtain the RTL code to run the pre-simulation test The register value at the specified time generated by the use case is obtained, and the register scan chain information at the specified time of the submodule is obtained.

Optionally, the acquisition module 110 is configured to acquire the top-level test file of the top-level, the input excitation and output reference values of all sub-modules, the top-level netlist and the top-level SDF file; correspondingly, the simulation module 120 is configured to: The top-level netlist and the top-level test file are compiled to generate a simulation circuit executable file; according to the top-level SDF file, the delay information of the connection between the standard cell and the standard cell is reversed in the simulation circuit, and run; In the process, the input excitations of all the submodules are loaded into each input pin of the simulation circuit, and the value output by the simulation circuit is compared with the corresponding output reference value to obtain the corresponding simulation result and FSDB file.

Optionally, the obtaining module 110 is specifically configured to: obtain the netlist of the integrated circuit, the SPEF file, the SDC constraint file, the RTL code and the pre-simulation test case; according to the netlist of the integrated circuit, the SPEF file, The SDC constraint file obtains the script used to capture the input excitation and output reference values of all submodules and the respective IO delay signals and corresponding clock domain signals of each submodule; according to the respective IO delay signals of each submodule Generate the top-level test file used to control the simulation flow with the corresponding clock domain signal; use the script that captures the input excitation and output reference values of all submodules to obtain the RTL code and run the pre-processing. The data generated during the simulation of the test case are obtained to obtain the input excitation and output reference values of all the sub-modules.

The implementation principle and the technical effects of the integrated circuit post-emulation device 100 provided by the embodiments of the present application are the same as those of the foregoing method embodiments. For brief description, for the parts not mentioned in the device embodiments, reference may be made to the corresponding method embodiments in the foregoing method embodiments. content.

As shown in FIG. 6 , FIG. 6 shows a structural block diagram of an electronic device 200 provided by an embodiment of the present application. The electronic device 200 includes: a transceiver 210 , a memory 220 , a communication bus 230 and a processor 240 .

The transceiver 210 , the memory 220 , and the processor 240 are electrically connected to each other directly or indirectly to realize data transmission or interaction. For example, these elements can be electrically connected to each other through one or more communication buses 230 or signal lines. The transceiver 210 is used for sending and receiving data. The memory 220 is used to store computer programs, such as the software function modules shown in FIG. 5 , that is, the post-integrated circuit emulation apparatus 100 . The post-integrated circuit emulation apparatus 100 includes at least one software function module that can be stored in the memory 220 in the form of software or firmware or solidified in an operating system (OS) of the electronic device 200 . The processor 240 is configured to execute executable modules stored in the memory 220, such as software function modules or computer programs included in the integrated circuit post-emulation apparatus 100. For example, the processor 240 is configured to obtain simulation parameters including netlists required for the simulation of the top layer and each submodule in the integrated circuit to be post-simulated, wherein the netlists corresponding to the top layer and each submodule are independent of each other and different from each other; for each submodule, use the corresponding simulation parameters of the submodule to carry out post-simulation on the submodule, obtain the corresponding simulation results and the FSDB file, and use the simulation parameters corresponding to the top layer to perform post-simulation on the top layer. Simulation is performed to obtain the simulation result and FSDB file of the top-level.

Wherein, the memory 220 may be, but not limited to, random access memory (Random Access Memory, RAM), read only memory (Read Only Memory, ROM), programmable read only memory (Programmable Read-Only Memory, PROM), erasable memory In addition to read-only memory (Erasable Programmable Read-Only Memory, EPROM), Electrical Erasable Programmable Read-Only Memory (Electric Erasable Programmable Read-Only Memory, EEPROM) and the like.

The processor 240 may be an integrated circuit chip with signal processing capability. The above-mentioned processor may be a general-purpose processor, including a central processing unit (Central Processing Unit, CPU), a network processor (Network Processor, NP), etc.; may also be a digital signal processor (Digital Signal Processor, DSP), application-specific integrated circuit (Application Specific Integrated Circuit, ASIC), Field Programmable Gate Array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components. The methods, steps, and logic block diagrams disclosed in the embodiments of this application can be implemented or executed. A general purpose processor may be a microprocessor or the processor 240 may be any conventional processor or the like.

The above-mentioned electronic device 200 includes, but is not limited to, a computer, a server, and the like.

Embodiments of the present application also provide a non-volatile computer-readable storage medium (hereinafter referred to as storage medium), where a computer program is stored on the storage medium, and the computer program is executed by a computer such as the above-mentioned electronic device 200 when running. The integrated circuit post-emulation method shown above.

It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. For the same and similar parts of the various embodiments, refer to each other Can.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may also be implemented in other manners. The apparatus embodiments described above are merely illustrative, for example, the flowcharts and block diagrams in the accompanying drawings illustrate the architectures, functions and possible implementations of apparatuses, methods and computer program products according to various embodiments of the present application. operate. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code that contains one or more functions for implementing the specified logical function(s) executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It is also noted that each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented in dedicated hardware-based systems that perform the specified functions or actions , or can be implemented in a combination of dedicated hardware and computer instructions.

In addition, each functional module in each embodiment of the present application may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

If the functions are implemented in the form of software function modules and sold or used as independent products, they may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art or the part of the technical solution. The computer software product is stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a notebook computer, a server, or an electronic device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

The above are only specific embodiments of the present application, but the protection scope of the present application is not limited to this. should be covered within the scope of protection of this application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims (10)

1. an integrated circuit post-simulation method, is characterized in that, comprises: Obtain simulation parameters including netlists required for the respective simulations of the top layer and each submodule in the integrated circuit to be simulated, wherein the netlists corresponding to the top layer and each submodule are independent and different from each other; For each submodule, use the simulation parameters corresponding to the submodule to perform post-simulation on the submodule to obtain the corresponding simulation results and the fast signal database FSDB file, and use the simulation parameters corresponding to the top layer to perform post-simulation on the top layer , to get the top-level simulation results and FSDB files. 2. The method according to claim 1, wherein the step of obtaining the simulation parameters including the netlist required for the simulation of each submodule, comprising: For each sub-module, obtain the module test file, input excitation and output reference value, module netlist and module standard delay format SDF file corresponding to the sub-module; correspondingly, use the simulation parameters corresponding to the sub-module to this sub-module Run simulations, including: Compile the module netlist and the module test file to generate a simulation circuit executable file; According to the SDF file, the delay information of the connection between the standard unit and the standard unit is reversed in the simulation circuit, and the operation is performed; During operation, the input excitation is loaded into each input pin of the simulation circuit, and the value output by the simulation circuit is compared with the corresponding output reference value to obtain the corresponding simulation result and FSDB file. 3. method according to claim 2, is characterized in that, the step that obtains the module test file corresponding to this submodule, input excitation and output reference value, comprise: Obtain the netlist of the integrated circuit, the standard parasitic parameter exchange format SPEF file, the standard design constraint SDC constraint file, the register transfer level RTL code and the pre-simulation test case; According to the netlist of the integrated circuit, the SPEF file, and the SDC constraint file, a module test file corresponding to the submodule and a script for capturing the input excitation and output reference value of the submodule are obtained; The data generated when the RTL code runs the pre-simulation test case is obtained by using the script that captures the input stimulus and output reference value of the submodule, and the input stimulus and output reference value of the submodule are obtained. 4. The method according to claim 1, wherein the step of obtaining the simulation parameters including the netlist required for the respective simulation of each submodule, comprises: For each sub-module, obtain the module test file, register scan chain information, input excitation and output reference values, module netlist and module SDF file corresponding to the sub-module, wherein the register scan chain information includes the sub-module in the The register values of each register at the specified time are extracted in the order of scanning the test chain; accordingly, the sub-module is simulated by using the corresponding simulation parameters of the sub-module, including: Compile the module netlist and the module test file to generate a simulation circuit executable file; According to the module SDF file, the delay information of the connection between the standard cell and the standard cell in the simulation circuit is reversed, and the register in the simulation circuit is assigned and run according to the register scan chain information; During operation, the input excitation is loaded into each input pin of the simulation circuit, and the value output by the simulation circuit is compared with the corresponding output reference value to obtain the corresponding simulation result and FSDB file. 5. The method according to claim 4, wherein the step of acquiring the module test file, register scan chain information, input excitation and output reference value corresponding to the submodule comprises: Obtain the netlist, SPEF file, SDC constraint file, RTL code and pre-simulation test case of the integrated circuit; According to the netlist of the integrated circuit, the SPEF file, and the SDC constraint file, a module test file corresponding to the submodule, a script for capturing the input excitation and output reference value at the specified time of the submodule are obtained, and According to the netlist of the integrated circuit and the SDC constraint file, a script for capturing the register scan chain information at the specified time of the submodule is obtained; Use the script that captures the input stimulus and output reference value at the specified time of the submodule to obtain the data generated when the RTL code runs the pre-simulation test case, and obtain the input stimulus and output reference value at the specified time of the submodule , and utilize the script that captures the register scan chain information of the specified moment of this submodule to obtain the register value of the specified moment when the RTL code runs the described pre-simulation test case, and obtains the register scan of the specified moment of this submodule chain information. 6. The method according to claim 1, wherein the step of obtaining simulation parameters including a netlist required for the top-level simulation comprises: Obtain the top-level test file of the top-level, the input excitation and output reference values of all submodules, the top-level netlist, and the top-level SDF file; accordingly, use the simulation parameters corresponding to the top-level to perform post-simulation on the top-level, including: Compile the top-level netlist and the top-level test file to generate a simulation circuit executable file; According to the top-level SDF file, the delay information of the connection between the standard cell and the standard cell is reversed in the simulation circuit, and the operation is performed; During operation, the input excitations of all the sub-modules are loaded into each input pin of the simulation circuit, and the value output by the simulation circuit is compared with the corresponding output reference value to obtain the corresponding simulation result and FSDB document. 7. The method according to claim 6, wherein the step of acquiring the top-level test file of the top-level, the input excitation of all submodules and the output reference value comprises: Obtain the netlist, SPEF file, SDC constraint file, RTL code and pre-simulation test case of the integrated circuit; According to the netlist of the integrated circuit, the SPEF file, and the SDC constraint file, a script for capturing the input excitation and output reference values of all submodules, and the respective input and output IO delay signals of each submodule and Corresponding clock domain signal; Generate the top-level test file for controlling the simulation process according to the respective IO delay signals of each submodule and the corresponding clock domain signals; The data generated when the RTL code runs the pre-simulation test case is obtained by using the script for capturing the input stimulus and output reference value of all submodules, and the input stimulus and output reference value of all the submodules are obtained. 8. An integrated circuit post-emulation device, characterized in that, comprising: The acquisition module is used to acquire simulation parameters including netlists required for the simulation of the top layer and each submodule in the integrated circuit to be post-simulated, wherein the netlists corresponding to the top layer and each submodule are independent and different from each other ; The simulation module is used for performing post-simulation on the sub-module with the corresponding simulation parameters of the sub-module for each sub-module, obtaining the corresponding simulation results and the FSDB file, and using the simulation parameters corresponding to the top-level to perform the simulation on the top-level. After simulation, the simulation result and FSDB file of the top layer are obtained. 9. An electronic device, characterized in that, comprising: a memory and a processor, the processor being connected to the memory; the memory for storing programs; The processor is configured to call a program stored in the memory to execute the method according to any one of claims 1-7. 10. A storage medium, characterized in that a computer program is stored thereon, and when the computer program is run by a processor, the method according to any one of claims 1-7 is executed.

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