CN114578610B - display panel - Google Patents

Abstract

A display panel, comprising: at least one thin film transistor; a circuit layer electrically connected with the thin film transistor; a pixel definition layer arranged on the circuit layer; the light-emitting elements are arranged on the circuit layer and are electrically connected to the thin film transistor through the circuit layer, wherein the light-emitting elements respectively comprise a plurality of light-emitting layers and are positioned in the pixel definition layer; the display panel is provided with a plurality of pixel areas, the photo sensors are respectively positioned in the pixel areas and form a plurality of overlapping areas with the circuit layer, the overlapping areas are equal to each other, and the photo sensors provide the function of identifying fingerprints.

Description

display panel

This application is a divisional application of an invention patent application whose applicant is AU Optronics Co., Ltd., with an application date of January 28, 2019, application number 201910079389.6, and an invention title of "display panel".

technical field

The invention relates to a display panel.

Background technique

With the development of technology, various portable electronic devices have successively become mainstream commodities in the consumer market, such as smart phones, smart watches, tablet computers or notebook computers. The functions of these portable electronic devices are gradually becoming more and more abundant along with the market trend, for example, users' private information, photos, and mobile payment authorizations can all be recorded in them. Therefore, such portable electronic devices are also configured with identity authentication to ensure the privacy of users.

In this regard, due to the uniqueness of the fingerprint, it has been applied to identity authentication, so that a portable electronic device equipped with fingerprint authentication has also been developed. However, fingerprint authentication needs to be equipped with an additional sensor, which also leads to the issue of how to integrate the sensor with the original electronic device.

Contents of the invention

An embodiment of the present invention provides a display panel, including a first thin film transistor, a pixel electrode, a display medium layer, a light shielding layer, a color filter layer, and a light sensor. The pixel electrode is electrically connected to the first thin film transistor. The display medium layer is arranged on the pixel electrode. The light-shielding layer is disposed on the display medium layer and includes a first opening pattern and a second opening pattern. The color filter layer is arranged on the display medium layer, wherein the vertical projection of the color filter layer on the display medium layer partially overlaps with the vertical projection of the first opening pattern of the light shielding layer on the display medium layer. The light sensor is arranged on the display medium layer, wherein the vertical projection of the light sensor on the display medium layer partially overlaps with the vertical projection of the second opening pattern of the light shielding layer on the display medium layer.

In some embodiments, the display panel further includes a second thin film transistor. The second thin film transistor is electrically connected to the light sensor, wherein the light shielding layer is located between the display medium layer and the second thin film transistor.

In some embodiments, the light sensor includes a metal electrode layer, and the vertical projection of the metal electrode layer on the display medium layer partially overlaps with the vertical projection of the first thin film transistor on the display medium layer.

In some embodiments, the light sensor further includes a light sensing layer, the light sensing layer has a lower surface and a side surface, the lower surface faces the array substrate and is connected to the side surface, and the lower surface and the side surface are covered by a metal electrode layer .

In some embodiments, the display panel further includes an insulating layer. The insulating layer is disposed on the light-shielding layer and extends through the second opening pattern towards the display medium layer to form a recess, wherein the photosensor is located in the recess and is separated from the light-shielding layer by the insulating layer.

In some embodiments, the vertical projection of the light sensor on the display medium layer partially overlaps with the vertical projection of the light shielding layer on the display medium layer.

In some embodiments, the photosensors are respectively located in the pixel area of the display panel, and the display panel further includes a circuit layer located between the first thin film transistor and the pixel electrode, wherein the photosensors and the light-shielding layer form a plurality of blocks overlapping areas, and the overlapping areas of these multiple blocks are equal to each other.

An embodiment of the present invention provides a display panel, including a thin film transistor, a wiring layer, a light emitting layer, and a light sensor. The thin film transistor is electrically connected to the circuit layer. The luminescent layer is disposed on the circuit layer and electrically connected to the circuit layer. The light sensor is arranged on the circuit layer, wherein the display panel has a pixel area, and the light sensor is respectively located in the pixel area, and forms a plurality of overlapping areas with the circuit layer, and the overlapping areas of the multiple blocks are equal to each other.

In some implementations, in each pixel area, there are three light-emitting elements and they are respectively used to provide colored lights of different wavelengths, the number of photosensors is one, and the photosensors will emit light at three same side of the element.

In some embodiments, the thin film transistor, circuit layer, pixel definition layer, and light emitting element are formed on the first substrate, and the photosensor is formed on the second substrate, and the thin film transistor, circuit layer, pixel definition layer, light emitting element, and light emitting element are formed on the second substrate. The sensor is located between the first substrate and the second substrate, and the display panel further includes a dielectric layer disposed between the pixel definition layer and the light sensor.

Through the above configuration, in addition to integrating the light sensor into the display panel to provide the function of identifying fingerprint patterns, since each pixel area of the display panel can provide the function of identifying fingerprints, it can be used to improve the performance of the display panel. screen-to-body ratio, and also makes the display panel suitable for a full-screen display device.

Description of drawings

FIG. 1A is a top view showing a plurality of pixel regions of a display panel according to a first embodiment of the disclosure.

Fig. 1B is a schematic cross-sectional view along line 1B-1B' of Fig. 1A.

Fig. 1C is a schematic cross-sectional view along line 1C-1C' of Fig. 1A.

FIG. 1D shows a schematic diagram of a display panel to which the first embodiment is applied.

FIG. 2A is a top view showing a plurality of pixel regions of a display panel according to a second embodiment of the disclosure.

Fig. 2B is a schematic cross-sectional view along line 2B-2B' of Fig. 2A.

Fig. 2C is a schematic cross-sectional view along line 2C-2C' of Fig. 2A.

FIG. 2D shows a schematic diagram of assembling the lower substrate and the upper substrate.

FIG. 2E shows a schematic diagram of a display panel to which the second embodiment is applied.

Explanation of reference signs:

10 fingers

20 rays

100A, 100B display panel

102, 106 pixel area

104A, 104B, 104C, 108A, 108B, 108C sub-pixel areas

110 backlight module

200, 500 lower substrates

210 first polarizer

220 first substrate

222 first shading layer

224 first buffer layer

230 first thin film transistor

240 first gate insulating layer

242 first interlayer dielectric layer

244 first source/drain contact layer

246 first passivation layer

248 common electrodes

250 first dielectric layer

252 pixel electrodes

300 display medium layer

400, 600 upper substrate

410 second dielectric layer

420 color filter layer

422 red filter layer

424 green filter layer

426 blue filter layer

430 second shading layer

432 first opening pattern

434 second opening pattern

440 third dielectric layer

442 depression

450, 620 light sensor

452, 622 metal electrode layer

454, 624 light sensing layer

456, 626 transparent electrode layer

462 fourth dielectric layer

464 second source/drain contact layer

466 second interlayer dielectric layer

468 second gate insulating layer

470 second thin film transistor

480 second buffer layer

482 third shading layer

484 second substrate

486 second polarizer

502, 602 layers

510 third substrate

512 third buffer layer

520 third thin film transistor

530 capacitive element

540 third gate insulating layer

542 first conductive layer

544 fourth gate insulating layer

546 second conductive layer

548 third interlayer dielectric layer

550 third source/drain contact layer

552 fifth dielectric layer

554 third conductive layer

556 second passivation layer

560 px definition layer

567 openings

570, 570A, 570B light-emitting elements

572 lower electrode

574 luminous layers

576 upper electrode

610 sixth dielectric layer

630 seventh dielectric layer

632 fourth source/drain contact layer

634 fourth interlayer dielectric layer

636 fifth gate insulating layer

640 fourth thin film transistor

650 fourth buffer layer

652 fourth shading layer

654 fourth substrate

656 third polarizer

700 clearance

702 Support structure

1B-1B', 1C-1C', 2B-2B', 2C-2C' line segments

D drain region

G grid

DH horizontal direction

DV portrait orientation

L1 distance

L2 distance

S source region

S1 lower surface

S2 side surface

SC channel area

TH1 first contact hole

TH2 second contact hole

TH3 third contact hole

TH4 fourth contact hole

TH5 fifth contact hole

TH6 sixth contact hole

TH7 seventh contact hole

TH8 eighth contact hole

TH9 Ninth Contact Hole

TH10 Tenth Contact Hole

Detailed ways

A number of implementations of the present invention will be disclosed below with the accompanying drawings. For the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the present invention, these practical details are unnecessary. In addition, for the sake of simplifying the drawings, some conventional structures and elements will be shown in a simple and schematic way in the drawings.

In this document, terms such as first, second, and third are used to describe various elements, components, regions, and layers to be understood. But these elements, components, regions, layers should not be limited by these terms. These terms are limited to identify a single element, component, region, layer. Therefore, a first element, component, region, or layer hereinafter may also be referred to as a second element, component, region, or layer without departing from the spirit of the present invention.

Please refer to FIG. 1A, FIG. 1B and FIG. 1C, FIG. 1A is a top view of a plurality of pixel regions 102 of a display panel 100A according to a first embodiment of the present disclosure, and FIG. 1B is a schematic cross-sectional view along line 1B-1B' of FIG. 1A , FIG. 1C is a schematic cross-sectional view along the line segment 1C-1C' of FIG. 1A.

As shown in FIG. 1A , the display panel 100A has a plurality of pixel regions 102 , and the pixel regions 102 can be arranged in an array along the horizontal direction DH and the vertical direction DV of FIG. 1A . For each pixel area 102, it can have three sub-pixel areas 104A, 104B, 104C, wherein the sub-pixel areas 104A, 104B, 104C can provide different colors, such as red, green, and blue.

1B and 1C, the display panel 100A includes a backlight module 110, a lower substrate 200, a display medium layer 300, and an upper substrate 400, wherein the backlight module 110 is connected to the lower substrate 200, and the display medium layer 300 is located between the lower substrate 200 and the upper substrate 400. Between the substrates 400. The backlight module 110 is used to emit light toward the lower substrate 200 , the display medium layer 300 and the upper substrate 400 , and the upper surface of the upper substrate 400 can be used as the display surface of the display panel 100A.

The lower substrate 200 includes a first polarizer 210, a first substrate 220, a first light shielding layer 222, a first buffer layer 224, a plurality of first thin film transistors 230, a first gate insulating layer 240, a first interlayer dielectric layer 242, the first source/drain contact layer 244, the first passivation layer 246, the common electrode 248, the first dielectric layer 250 and the pixel electrode 252, wherein the first polarizer 210 is configured between the backlight module 110 and the first between the substrates 220 . In some embodiments, the materials of the buffer layer, insulating layer, dielectric layer and passivation layer of the lower substrate 200 can be organic materials or inorganic materials, such as epoxy resin, silicon oxide (SiOx), silicon nitride ( SiNx), a composite layer composed of silicon oxide and silicon nitride, or other suitable dielectric materials.

The first substrate 220 is disposed on the first polarizer 210, wherein the first substrate 220 can be used as the carrier substrate of the lower substrate 200 in the process, for example, it can be a glass substrate, so that other elements or layers of the lower substrate 200 can be formed on the first substrate 220 .

The first light shielding layer 222 , the first buffer layer 224 , the plurality of first thin film transistors 230 and the first gate insulating layer 240 are disposed on the first substrate 220 . The first buffer layer 224 is disposed on the first light-shielding layer 222 , which can facilitate the formation of the first thin film transistor 230 . The formation position of the first thin film transistor 230 is corresponding to the first light-shielding layer 222, wherein the first light-shielding layer 222 has light-shielding properties, and it can be made of metal, organic or inorganic materials, so as to shield the light traveling toward the first thin film transistor 230 from below, In this way, the first thin film transistor 230 is prevented from deriving leakage current due to light exposure.

Each first thin film transistor 230 includes a source region S, a drain region D, a channel region SC, and a gate G, wherein the source region S, the drain region D, and the channel region SC can be formed from the same layer, and can be formed by diffusion The process adjusts the carrier concentration of the same layer to define the position of each region, wherein the layer may be a crystalline silicon material. The first gate insulating layer 240 will cover the source region S, the drain region D and the channel region SC, and the gate G is arranged on the first gate insulating layer 240, and the setting position of the gate G will be in the same position as the channel region. SC corresponds.

The first interlayer dielectric layer 242 is disposed on the first gate insulating layer 240 and covers the gate G, wherein the first gate insulating layer 240 and the first interlayer dielectric layer 242 share a first contact hole TH1 . A first source/drain contact layer 244 is disposed on the first interlayer dielectric layer 242 , wherein the first source/drain contact layer 244 may include a metal material. The first source/drain contact layer 244 can contact the source region S and the drain region D of the first thin film transistor 230 through the first contact hole TH1 to be electrically connected to the first thin film transistor 230 . The gate G and the first source/drain contact layer 244 of the first thin film transistor 230 can be regarded as the wiring layer of the lower substrate 200 .

The first passivation layer 246 is disposed on the first interlayer dielectric layer 242 and covers at least part of the first source/drain contact layer 244 . The common electrode 248 and the first dielectric layer 250 are disposed on the first passivation layer 246, wherein the first dielectric layer 250 covers the common electrode 248, and the first dielectric layer 250 and the first passivation layer 246 can have the first passivation layer 246 in common. Two contact hole TH2. The pixel electrode 252 is disposed on the first dielectric layer 250, and the pixel electrode 252 can contact the first source/drain contact layer 244 through the first dielectric layer 250 and the second contact hole TH2 of the first passivation layer 246, Therefore, it is electrically connected to the drain region D of the first thin film transistor 230 through the first source/drain contact layer 244 . In some embodiments, the materials of the common electrode 248 and the pixel electrode 252 include transparent conductive materials, such as indium tin oxide, indium zinc oxide, zinc oxide, carbon nanotubes, indium gallium zinc oxide or other suitable materials.

The display medium layer 300 is disposed on the common electrode 248 and the pixel electrode 252 and may have a display medium. For example, the display medium layer 300 may be a liquid crystal layer and have liquid crystal molecules. When the first thin film transistor 230 is driven to make the common electrode 248 and the pixel electrode 252 have different potentials, the common electrode 248 and the pixel electrode 252 can couple out an electric field, thereby controlling the display medium of the display medium layer 300 to control the potential from the bottom substrate 200 is the polarization of light traveling to the upper substrate 400 .

The upper substrate 400 includes a second dielectric layer 410, a color filter layer 420, a second light shielding layer 430, a third dielectric layer 440, a photosensor 450, a fourth dielectric layer 462, a second source/drain The contact layer 464 , the second interlayer dielectric layer 466 , the second gate insulating layer 468 , the second thin film transistor 470 , the second buffer layer 480 , the third light-shielding layer 482 , the second substrate 484 and the second polarizer 486 . In some embodiments, the materials of the buffer layer, insulating layer, dielectric layer and passivation layer of the upper substrate 400 can be organic materials or inorganic materials, such as epoxy resin, silicon oxide (SiOx), silicon nitride ( SiNx), a composite layer composed of silicon oxide and silicon nitride, or other suitable dielectric materials.

The second dielectric layer 410 is disposed on the display medium layer 300 . The color filter layer 420 and the second light shielding layer 430 are disposed on the second dielectric layer 410 . The second light-shielding layer 430 has a first opening pattern 432 and a second opening pattern 434. The first opening pattern 432 and the second opening pattern 434 can be formed by a patterning process. For example, a light-shielding material can be used to form a layer first, and then the The light-shielding material is patterned to form a second light-shielding layer 430 having a first opening pattern 432 and a second opening pattern 434 . The vertical projection of the color filter layer 420 on the display medium layer 300 partially overlaps the vertical projection of the first opening pattern 432 of the second light shielding layer 430 on the display medium layer 300 . Specifically, the color filter layer 420 includes a red filter layer 422, a green filter layer 424, and a blue filter layer 426, wherein the bottom of the red filter layer 422 is located between the second light shielding layer 430 and the second dielectric layer. 410, and the top of the red filter layer 422 is located in the first opening pattern 432, so the vertical projection of the red filter layer 422 in the first opening pattern 432 on the display medium layer 300 will be consistent with the second light-shielding pattern. The vertical projections of the first opening pattern 432 of the layer 430 on the display medium layer 300 overlap. The arrangement of the green filter layer 424 and the blue filter layer 426 can be similar to that of the red filter layer 422 , which will not be repeated here. Through this configuration, the light traveling from the display medium layer 300 to the upper substrate 400 can pass through the first opening pattern 432 of the second light-shielding layer 430 and the color filter layer 420 therein, thereby having a corresponding color, and In this way, the display panel 100A displays images.

The third dielectric layer 440 is disposed on the color filter layer 420 and the second light-shielding layer 430 , wherein part of the third dielectric layer 440 passes through the second opening pattern 434 of the second light-shielding layer 430 and extends toward the display medium layer 300 , to form the concave portion 442 . In other words, the third dielectric layer 440 can pass through the second opening pattern 434 of the second light-shielding layer 430 from a position higher than the second light-shielding layer 430 , and extend to a position lower than the second light-shielding layer 430 to form the concave portion 442 . , the formed recess 442 may contact the second dielectric layer 410 , and the interface between the recess 442 and the second dielectric layer 410 will be located under the second light shielding layer 430 . For example, the minimum vertical distance from the recess 442 to the display medium layer 300 can be marked as distance L1, the minimum vertical distance from the second light shielding layer 430 to the display medium layer 300 can be marked as distance L2, and the distance L1 is smaller than the distance L2 .

The light sensor 450 is arranged on the display medium layer 300, and the vertical projection of the light sensor 450 on the display medium layer 300 is the same as the vertical projection of the second opening pattern 434 of the second light-shielding layer 430 on the display medium layer 300 partially overlap. Specifically, the photosensor 450 is located on the recessed portion 442 of the third dielectric layer 440 and is in contact with the third dielectric layer 440 , wherein the photosensor 450 can be connected to the second dielectric layer 440 through the third dielectric layer 440 . The light shielding layer 430 is separated. By disposing the photosensor 450 on the recessed portion 442 of the third dielectric layer 440, since the recessed portion 442 extends from a position higher than the second light-shielding layer 430 to a position lower than the second light-shielding layer 430, it can Avoid excessive increase in the thickness of the display panel 100A due to the configuration of the light sensor 450 .

In addition, the location of the photosensor 450 is offset from the location of the color filter layer 420, so as to prevent the photosensor 450 from affecting the light output from the color filter layer 420 and affecting the image quality of the display panel 100A. . Specifically, as shown in FIG. 1A , in each pixel region 102 of the display panel 100A, three sub-pixel regions 104A, 104B, and 104C are composed of the red filter layer 422 and the green filter layer of the color filter layer 420 respectively. 424 and blue filter layer 426, and each pixel area 102 will be configured with a photosensor 450, wherein the photosensor 450 will be located in the red filter layer 422, green filter layer 424 and blue The same side of the filter layer 426 , so the light sensor 450 will not affect the light emitted from the color filter layer 420 .

On the other hand, since the light sensor 450 in each pixel area 102 is located on the same side of the red filter layer 422, the green filter layer 424 and the blue filter layer 426 of the color filter layer 420, it can It is considered that the disposition position of the light sensor 450 and the disposition position of the color filter layer 420 are independent of each other. For example, even if the distance between the red filter layer 422, the green filter layer 424, and the blue filter layer 426 of the color filter layer 420 changes or the respective widths increase or decrease, the light sensor 450 can still It is set at its original position without additionally changing the setting position corresponding to the change of the spacing or the change of the width of the filter layer.

In the case where the location of the photosensor 450 is independent from the location of the color filter layer 420, the photosensor 450 in each pixel area 102 can be configured in the same manner, which is beneficial to simplify the process. For example, the mask pattern used to fabricate the photosensor 450 can be simplified. Furthermore, in the case that the photosensors 450 in each pixel region 102 are configured in the same manner, these photosensors 450 can be connected to the circuit layer of the lower substrate 200 (including the gate G and the first source/ The drain contact layer 244) forms multiple overlapping areas (that is, areas that overlap each other in a top view), and these multiple overlapping areas are equal to each other, so as to avoid unexpected differences between different pixel regions 102, In this way, uneven image brightness of the display panel 100A is prevented.

Please return to FIG. 1B and FIG. 1C again. The light sensor 450 includes a metal electrode layer 452, a photo-sensing layer 454 and a light-transmitting electrode layer 456, wherein the metal electrode layer 452 contacts the third dielectric layer 440, and the light-sensing layer 454 and the light-transmitting electrode layer 456 overlap On the metal electrode layer 452 , and the light sensing layer 454 is located between the metal electrode layer 452 and the transparent electrode layer 456 . The material of the photo-sensing layer 454 includes silicon rich oxide, and has the property of generating electron-hole pairs upon receiving light. Through this property, the photo-sensor 450 can achieve the photo-sensing effect.

The metal electrode layer 452 can conform to the third dielectric layer 440 below to present a concave shape, wherein the vertical projection of the metal electrode layer 452 on the display medium layer 300 is the same as the vertical projection of the first thin film transistor 230 on the display medium layer 300 May partially overlap. Since the metal electrode layer 452 has no light transmission, the metal electrode layer 452 can cover the first thin film transistor 230 overlapping it. Therefore, when looking at the display panel 100A from a top view (that is, looking from the top of FIG. 1B and FIG. 1C toward When displaying the panel 100A), the first thin film transistor 230 located under the second opening pattern 434 of the second light-shielding layer 430 cannot be seen. In addition, the vertical projection of the metal electrode layer 452 on the display medium layer 300 may partially overlap with the vertical projection of the second light-shielding layer 430 on the display medium layer 300. Through this configuration, the light beam from the lower substrate 200 can be prevented from passing through the second The gap between the light shielding layer 430 and the metal electrode layer 452 .

The photo-sensing layer 454 has a lower surface S1 and a side surface S2, wherein the lower surface S1 of the photo-sensing layer 454 faces the display medium layer 300 and is connected to the side surface S2 of the photo-sensing layer 454, and the lower surface of the photo-sensing layer 454 S1 and side surface S2 are covered by the metal electrode layer 452, so that the light beam passing through the photo-sensing layer 454 from top to bottom will then travel to the metal electrode layer 452, and the metal electrode layer 452 can prevent it from passing through the photo-sensing layer 452. The light beam of the layer 454 travels to the display medium layer 300 , so as to prevent the elements or layers of the lower substrate 200 from being affected by the light unintendedly. In addition, the photo-sensing layer 454 can conform to the metal electrode layer 452 below it and also present a concave shape, wherein the light-transmitting electrode layer 456 can be correspondingly located in the recess of the photo-sensing layer 454, and the top of the photo-sensing layer 454 The surface is substantially coplanar with the upper surface of the transparent electrode layer 456 . In some embodiments, the material of the light-transmitting electrode layer 456 includes transparent conductive materials, such as indium tin oxide, indium zinc oxide, zinc oxide, carbon nanotubes, indium gallium zinc oxide, or other suitable materials.

The fourth dielectric layer 462, the second source/drain contact layer 464, the second interlayer dielectric layer 466, the second gate insulating layer 468, and the second thin film transistor 470 are arranged on the third dielectric layer 440 and the light over the sensor 450 . The fourth dielectric layer 462 covers the third dielectric layer 440 and the photosensor 450, and has a third contact hole TH3, and a part of the metal electrode layer 452 of the photosensor 450 will be located in the third contact hole TH3 . The second source/drain contact layer 464 is disposed on the fourth dielectric layer 462 and covered by the second interlayer dielectric layer 466 , wherein the second source/drain contact layer 464 may include a metal material. The second source/drain contact layer 464 is located between the fourth dielectric layer 462 and the second interlayer dielectric layer 466 . In addition, the second source/drain contact layer 464 can contact the metal electrode layer 452 located in the third contact hole TH3 to electrically connect the light sensor 450 .

The second gate insulating layer 468 and the second thin film transistor 470 are disposed on the second interlayer dielectric layer 466, wherein the second thin film transistor 470 includes a source region S, a drain region D, a channel region SC and a gate G , wherein the source region S, the drain region D and the channel region SC can be formed from the same layer, and the carrier concentration of the same layer can be adjusted through a diffusion process to define the positions of each region. The second gate insulating layer 468 will cover the gate G, so that the gate G is located between the second interlayer dielectric layer 466 and the second gate insulating layer 468, and the setting position of the gate G will be close to the channel region. SC corresponds. The second gate insulating layer 468 and the second interlayer dielectric layer 466 may jointly have a fourth contact hole TH4, and the second source/drain contact layer 464 may contact the second TFT 470 through the fourth contact hole TH4. The source region S and the drain region D, thereby electrically connecting the second thin film transistor 470 to the light sensor 450 .

The second thin film transistor 470 can be located above the second light shielding layer 430, and the second light shielding layer 430 is located between the display medium layer 300 and the second thin film transistor 470, thereby preventing the radiation from the lower substrate 200 from passing through the display medium. The light beam from the layer 300 will irradiate the second thin film transistor 470 to generate a leakage current. Specifically, the vertical projection of the channel region SC of the second thin film transistor 470 to the display medium layer 300 may overlap with the vertical projection of the second light-shielding layer 430 to the display medium layer 300, thereby preventing the light beam from the display medium layer 300 from irradiating the The channel region SC of the second thin film transistor 470 .

The second buffer layer 480 and the third light shielding layer 482 are arranged on the second gate insulating layer 468 and the second thin film transistor 470, wherein the second buffer layer 480 can facilitate the formation of the second thin film transistor 470, and the third light shielding layer 482 The forming position of the TFT may at least correspond to the channel region SC of the second thin film transistor 470 , so as to prevent the channel region SC of the second thin film transistor 470 from deriving leakage current due to illumination from above.

The second substrate 484 is disposed on the second buffer layer 480 and the third light-shielding layer 482 , and the second polarizer 486 is disposed on the second substrate 484 . The second substrate 484 can be used as a carrier substrate in the process of the upper substrate 400 , which can be, for example, a glass substrate. For example, each layer or element of the upper substrate 400 can be formed on the second substrate 484 first, and after the second light-shielding layer 430 and the color filter layer 420 are formed, the second dielectric layer 410 formed continuously can be used as for the flat layer. After the second dielectric layer 410 is formed, the upper substrate 400 can be turned over so that the second dielectric layer 410 is located on the bottom side, and then the upper substrate 400 is assembled on the lower substrate 200, wherein the dielectric layer 300 is displayed. It is filled between the lower substrate 200 and the upper substrate 400 to complete the structure shown in FIG. 1B and FIG. 1C .

Please see FIG. 1D again. FIG. 1D shows a schematic diagram of a display panel 100A applying the first embodiment. The structure of the left half and the right half of the display panel 100A depicted in FIG. 1D may be the same as the structures of FIG. 1B and FIG. 1C respectively. In order not to make the drawing too complicated, some components in FIG. 1D are not marked with component numbers.

The display panel 100A of the first embodiment can detect the user's fingerprint pattern through the light sensor 450 . For example, when the user's finger 10 covers and touches the display panel 100A, the light 20 emitted by the backlight module 110 can enter and pass through the second light-shielding layer after passing through the lower substrate 200 and the display medium layer 300 430 of the color filter layer 420 within the first opening pattern 432 , and then travels to the finger 10 and is reflected from the finger 10 . The light 20 reflected by the finger 10 can return to the upper substrate 400 and enter the light sensing layer 454 of the light sensor 450 after passing through the layers in the upper substrate 400 . Since there are peaks and valleys in the texture of the finger 10, and the reflection direction of the light 20 on the peaks and valleys will be different, so different light sensors 450 of the display panel 100A will receive reflected light with different intensities. These reflected lights with different intensities can analyze the fingerprint pattern of the user's finger 10 .

In summary, in this embodiment, the color filter layer 420 , the second light-shielding layer 430 and the photosensor 450 can be integrated into the upper substrate 400 of the display panel 100A, so as to avoid the display caused by the configuration of the photosensor 450 A situation where the thickness of the panel 100A is increased excessively. Through this configuration, photosensors 450 can be respectively arranged in the plurality of pixel regions 102 of the display panel 100A, so that each pixel region 102 of the display panel 100A can provide the function of identifying fingerprints, that is, the display panel In addition to providing images, the display surface of 100A can also be used as a fingerprint recognition area for users, thereby increasing the screen ratio of the display panel 100A, so that the display panel 100A is suitable for designing a full-screen display device.

Please refer to FIG. 2A, FIG. 2B and FIG. 2C. FIG. 2A is a top view showing a plurality of pixel regions 106 of a display panel 100B according to a second embodiment of the present disclosure, and FIG. A schematic cross-sectional view, FIG. 2C is a schematic cross-sectional view along line 2C-2C' in FIG. 2A . At least one difference between this embodiment and the first embodiment is that the display panel 100B of this embodiment provides images by emitting light through the light-emitting layer.

As shown in FIG. 2A , the display panel 100B has a plurality of pixel regions 106 , and the pixel regions 106 can be arranged in an array along the horizontal direction DH and the vertical direction DV of FIG. 2A . For each pixel area 106, it can have three sub-pixel areas 108A, 108B, 108C, wherein the sub-pixel areas 108A, 108B, 108C can provide different colors, such as red, green, and blue.

The display panel 100B includes a lower substrate 500 and an upper substrate 600 , wherein the upper substrate 600 is located on the lower substrate 500 , and the upper surface of the upper substrate 600 can be used as a display surface of the display panel 100B. The lower substrate 500 and the upper substrate 600 can be manufactured separately, and assembled together after the respective manufacturing is completed.

For example, please see FIG. 2D first. FIG. 2D shows a schematic diagram of assembling the lower substrate 500 and the upper substrate 600 together. The lower substrate 500 and the upper substrate 600 respectively include a third substrate 510 and a fourth substrate 654 , which may be glass substrates, for example. In order not to make the drawings too complicated, the layer body formed on the third substrate 510 of the lower substrate 500 is represented by layer body 502, and the layer body formed on the fourth substrate 654 of the upper substrate 600 is represented by layer body 602. The third polarizer of the substrate 600 is disposed on the fourth substrate 654 . The display panel 100B may further include a supporting structure 702, wherein the supporting structure 702 may be glass, ceramics or other frames with sufficient supporting strength. The supporting structure 702 is disposed between the lower substrate 500 and the upper substrate 600 so that the upper substrate 600 can be fixed above the lower substrate 500 , and a gap 700 can exist between the lower substrate 500 and the upper substrate 600 . In the embodiment depicted in Figure 2D, gap 700 may be an air gap. In other embodiments, a solid dielectric material may also be filled between the lower substrate 500 and the upper substrate 600 .

Please return to FIG. 2B and FIG. 2C . The lower substrate 500 includes a third substrate 510, a third buffer layer 512, a plurality of third thin film transistors 520, a capacitive element 530, a third gate insulating layer 540, a first conductive layer 542, a fourth gate insulating layer 544, a first The second conductive layer 546, the third interlayer dielectric layer 548, the third source/drain contact layer 550, the fifth dielectric layer 552, the third conductive layer 554, the second passivation layer 556, the pixel definition layer 560 and Light emitting element 570 . In some embodiments, the materials of the buffer layer, insulating layer, dielectric layer and passivation layer of the lower substrate 500 can be organic materials or inorganic materials, such as epoxy resin, silicon oxide (SiOx), silicon nitride ( SiNx), a composite layer composed of silicon oxide and silicon nitride, or other suitable dielectric materials.

The third substrate 510 can be used as a carrier substrate in the process of the lower substrate 500 , such as a glass substrate, so that other elements or layers of the lower substrate 500 can be formed on the third substrate 510 during the process.

The third buffer layer 512, a plurality of third thin film transistors 520, the third gate insulating layer 540 and the fourth gate insulating layer 544 are arranged on the third substrate 510, and the third thin film transistor 520 is positioned on the third buffer layer 512. , wherein the third buffer layer 512 can facilitate the formation of the third thin film transistor 520 . Each third thin film transistor 520 includes a source region S, a drain region D, a channel region SC, and a gate G, wherein the source region S, the drain region D, and the channel region SC can be formed from the same layer, and can be formed by diffusion The process adjusts the carrier concentration of this same layer to define the positions of the regions. The third gate insulating layer 540 will cover the source region S, the drain region D and the channel region SC, and the gate G is disposed on the third gate insulating layer 540, and the position of the gate G is to be in the same position as the channel region. SC corresponds. The fourth gate insulating layer 544 is disposed on the third gate insulating layer 540 and covers the gate G.

The capacitive element 530 and the first conductive layer 542 are disposed on the third buffer layer 512 . The capacitive element 530 and the source region S, drain region D, and channel region SC of the third thin film transistor 520 can be formed in the same layer, and then the carrier concentration of each region can be adjusted through a diffusion process, wherein the layer can be crystalline silicon Material. The first conductive layer 542 is disposed on the third gate insulating layer 540, and the first conductive layer 542 and the gate G of the third thin film transistor 520 can be formed in the same layer, for example, by patterning the same metal layer. . The capacitive element 530 and the first conductive layer 542 can provide electrical communication in the lower substrate 500 .

The second conductive layer 546, the third interlayer dielectric layer 548, and the third source/drain contact layer 550 are disposed on the fourth gate insulating layer 544, wherein the third source/drain contact layer 550 may contain metal Material. The third interlayer dielectric layer 548 covers the fourth gate insulating layer 544 and the second conductive layer 546 . The third gate insulating layer 540, the fourth gate insulating layer 544 and the third interlayer dielectric layer 548 may have a fifth contact hole TH5 in common, and the fourth gate insulating layer 544 and the third interlayer dielectric layer 548 may Commonly have a sixth contact hole TH6, and the third interlayer dielectric layer 548 may have a seventh contact hole TH7. The third source/drain contact layer 550 is disposed on the third interlayer dielectric layer 548 and can be electrically connected to corresponding layer bodies through different contact holes. Specifically, the third source/drain contact layer 550 can extend to the source region S or the drain region D of the third thin film transistor 520 through the fifth contact hole TH5, so as to be in contact with the source region of the third thin film transistor 520 S or the drain region D is electrically connected, in addition, the third source/drain contact layer 550 can also extend to the capacitor element 530 through the fifth contact hole TH5, thereby being electrically connected with the capacitor element 530; The drain contact layer 550 can extend to the gate G of the third thin film transistor 520 through the sixth contact hole TH6, so as to be electrically connected to the gate G of the third thin film transistor 520. In addition, the third source/drain contact layer 550 can also extend to the first conductive layer 542 through the sixth contact hole TH6, so as to be electrically connected with the first conductive layer 542; the third source/drain contact layer 550 can extend to the second conductive layer through the seventh contact hole TH7. layer 546 to be electrically connected to the second conductive layer 546 .

The fifth dielectric layer 552, the third conductive layer 554 and the second passivation layer 556 are disposed on the third interlayer dielectric layer 548, wherein the fifth dielectric layer 552 covers the third source/drain contact layer 550, And has the eighth contact hole TH8. The third conductive layer 554 and the second passivation layer 556 are disposed on the fifth dielectric layer 552, wherein the second passivation layer 556 covers the third conductive layer 554, so that the third conductive layer 554 is positioned on the fifth dielectric layer 552 and the second passivation layer 556, and the third conductive layer 554 can extend to the third source/drain contact layer 550 through the eighth contact hole TH8, so as to be electrically connected to the third source/drain contact layer 550 sexual connection.

In the structure of the lower substrate 500, the gate G of the third thin film transistor 520, the first conductive layer 542, the second conductive layer 546, the third source/drain contact layer 550 and the third conductive layer 554 can be used as the lower The wiring layer of the substrate 500 provides electrical communication.

The pixel definition layer 560 and the light emitting element 570 are disposed on the second passivation layer 556 , wherein the light emitting element 570 includes a lower electrode 572 , a light emitting layer 574 and an upper electrode 576 . The lower electrode 572 of the light emitting element 570 is disposed on the second passivation layer 556 and covered by the pixel definition layer 560, wherein the second passivation layer 556 may have a ninth contact hole TH9, and the lower electrode 572 may pass through the ninth contact hole TH9 extends to the third conductive layer 554 to be electrically connected to the third thin film transistor 520 . The lower electrode 572 may be formed by performing a patterning process on the conductive layer body. In some embodiments, in the process of forming the lower electrode 572, the patterning process can also form the fourth conductive layer 558 on the conductive layer after the patterning process, wherein the fourth conductive layer 558 is positioned on the second passivation layer. layer 556 and extend to the third conductive layer 554 through the ninth contact hole TH9 . In addition, the fourth conductive layer 558 can also be used as a circuit layer of the lower substrate 500 .

The light emitting layer 574 of the light emitting element 570 is disposed in the pixel definition layer 560 and electrically connected to the lower electrode 572 . Here, the term "disposed in the pixel definition layer 560" means that after the pixel definition layer 560 is formed, an opening 567 can be formed in the pixel definition layer 560 by removing part of the pixel definition layer 560, and the opening 567 The lower electrode 572 will be exposed, and then, the light emitting layer 574 is formed in the opening 567 , so that the light emitting layer 574 can be disposed in the pixel definition layer 560 . The upper electrode 576 of the light-emitting element 570 is disposed on the pixel definition layer 560 and the light-emitting layer 574 , and is electrically connected to the light-emitting layer 574 . In addition, the upper electrode 576 of the light emitting element 570 can extend to the fourth conductive layer 558 through the tenth contact hole TH10 of the pixel definition layer 560 , so as to be electrically connected to the circuit layer of the lower substrate 500 . When a bias voltage is applied to the light-emitting layer 574 through the lower electrode 572 and the upper electrode 576 of the light-emitting element 570, the light-emitting layer 574 can be made to emit light.

The material of the light-emitting layer 574 of the light-emitting element 570 can include organic materials. In other words, the light-emitting element 570 can be an organic light-emitting diode, wherein the wavelength of the colored light provided by the light-emitting element 570 can be determined according to the organic material of the light-emitting layer 574 . For example, the light emitting element 570 can provide red light, green light or blue light by selecting different organic materials of the light emitting layer 574 . The material of the lower electrode 572 and the upper electrode 576 of the light-emitting element 570 may include transparent conductive materials, such as indium tin oxide, indium zinc oxide, zinc oxide, carbon nanotubes, indium gallium zinc oxide, or other suitable materials, or, also Non-transparent conductive materials such as metals, alloys, or other suitable materials may be included. In addition, the materials of the lower electrode 572 and the upper electrode 576 of the light emitting element 570 can be different, for example, the lower electrode 572 is made of a non-transparent conductive material, while the upper electrode 576 is made of a transparent conductive material.

The structure of the upper substrate 600 of this embodiment is substantially the same as that of the upper substrate 400 of the first embodiment, but the upper substrate 600 of this embodiment omits the color filter layer and the light shielding layer at the same horizontal position as the color filter layer. layers (such as the color filter layer and the second light-shielding layer of the first embodiment). Specifically, the upper substrate 600 of this embodiment includes a sixth dielectric layer 610, a photosensor 620, a seventh dielectric layer 630, a fourth source/drain contact layer 632, a fourth interlayer dielectric layer 634, a fifth gate insulating layer 636, a fourth thin film transistor 640, a fourth buffer layer 650, a fourth light shielding layer 652, a fourth substrate 654, and a third polarizer 656, wherein the photosensor 620 includes a photometal electrode layer 622 , a light-sensing layer 624 and a light-transmitting electrode layer 626 , and the fourth thin film transistor 640 includes a source region S, a drain region D, a channel region SC and a gate G. Since the detailed description of these layers or elements has been described in the first embodiment, it will not be repeated here.

Similar to the first embodiment, the location of the light sensor 620 and the light emitting element 570 in this embodiment can be offset from each other, so as to prevent the light sensor 620 from affecting the output of the light emitting element 570 and the display on the display panel 100B. image quality. Specifically, as shown in FIG. 2A , in each pixel area 106 of the display panel, three sub-pixel areas 108A, 108B, and 108C are respectively composed of three light-emitting elements that provide different color lights (such as red, green, and blue). 570A, 570, 570B, and each pixel area 106 will be configured with a light sensor 620, wherein the light sensor 620 will be located on the same side of the three light emitting elements 570A, 570, 570B, so the light sensing The device 620 will not affect the output light of the light emitting elements 570A, 570, 570B.

On the other hand, since the light sensor 620 in each pixel area 106 is located on the same side of the light emitting elements 570A, 570, 570B, it can be considered that the position of the light sensor 620 is the same as that of the light emitting elements 570A, 570, 570B. The locations of the 570B are independent of each other, and therefore, the photosensors 620 of each pixel area 106 can be configured in the same manner, which is beneficial to simplify the process.

Furthermore, in the case that the photosensors 620 in each pixel area 106 are configured in the same manner, these photosensors 620 and the circuit layer below them can form multiple overlapping areas, and the overlapping areas of the multiple blocks are equal to each other. . The circuit layer can be, for example, the gate G, the first conductive layer 542 , the second conductive layer 546 , the third source/drain contact layer 550 and the third conductive layer 554 of the lower substrate 500 in FIG. 2B and FIG. 2C . In FIG. 2A , the area shown with the mesh bottom in the pixel area 106 and outside the light sensor 620 and the light-emitting elements 570A, 570, 570B can be regarded as the circuit layer under the light sensor 620, and each pixel The circuit layer shown in the region 106 forms an overlapping area with the corresponding light sensor 620 . For two different pixel regions 106, the two overlapping areas formed by the two photosensors 620 and the underlying circuit layer will be equal to each other, so unexpected occurrences between different pixel regions 106 can be avoided. , so as to prevent uneven brightness of the image on the display panel 100B.

Please see FIG. 2E again. FIG. 2E shows a schematic diagram of a display panel 100B applying the second embodiment. The left half structure and the right half structure of the display panel 100B depicted in FIG. 2E may be the same as those in FIG. 2B and FIG. 2C respectively. In order not to make the drawing too complicated, some components in FIG. 2E are not marked with component symbols.

The display panel 100B of the second embodiment can detect the user's fingerprint pattern through the light sensor 620 . For example, when the user's finger 10 covers and touches the display panel 100B, the light 20 emitted by the light emitting layer 574 of the light emitting element 570 may be reflected from the finger 10 after passing through the upper substrate 600 . The light 20 reflected by the finger 10 can return to the upper substrate 600 , and enter the light sensing layer 624 of the light sensor 620 after passing through the layers in the upper substrate 400 , thereby analyzing the user's fingerprint pattern. Similarly, since the photosensors 620 are respectively disposed in the pixel regions 106 of the display panel 100B, each pixel region 106 of the display panel 100B can provide the function of identifying fingerprints, thereby increasing the screen ratio of the display panel 100B. Furthermore, the display panel 100B can be adapted to be designed as a full-screen display device.

To sum up, the display panel of the present disclosure includes a lower substrate and an upper substrate, wherein the upper substrate includes a light sensor for recognizing a user's fingerprint pattern. The display panel assembled by the lower substrate and the upper substrate may be a liquid crystal display panel, or may also be an organic light emitting body display panel.

In the case that the display panel assembled by the lower substrate and the upper substrate is a liquid crystal display panel, the photosensor can be integrated with the light-shielding layer and the color filter layer in the upper substrate, so as to avoid the display caused by the configuration of the photosensor. A situation where the thickness of the panel increases excessively. In the case where the display panel assembled by the lower substrate and the upper substrate is an organic light-emitting type display panel, the installation position of the photosensor and the installation position of the light-emitting element are independent of each other, thereby simplifying the process and avoiding the gap between different pixel regions. There are unexpected differences.

Through the above configuration, in addition to integrating the light sensor into the display panel to provide the function of identifying fingerprint patterns, since each pixel area of the display panel can provide the function of identifying fingerprints, it can be used to improve the performance of the display panel. The screen-to-body ratio also makes the display panel suitable for a full-screen display device.

Although the present invention has been disclosed above in various embodiments, it is not intended to limit the present invention. Any person skilled in the art may make various changes and modifications without departing from the concept and scope of the present invention. Therefore, the present invention The scope of protection of the invention should be defined by the claims.

Claims (10)

1. A display panel, comprising: at least one first thin film transistor; a circuit layer electrically connected to the first thin film transistor; A pixel definition layer, set on the line layer; A plurality of light-emitting elements are arranged on the wiring layer and electrically connected to the first thin film transistor through the wiring layer, wherein the light-emitting elements respectively include a plurality of light-emitting layers and are located in the pixel definition layer; and A plurality of photosensors are arranged on the pixel definition layer, wherein the display panel has a plurality of pixel regions, and the photosensors are respectively located in the pixel regions and form a plurality of circuits with the circuit layer. Block overlapping areas, and the areas of these overlapping areas in each pixel are equal to each other, The light sensor provides the function of identifying fingerprints. 2. The display panel as claimed in claim 1, wherein in each of the pixel regions, the number of the light emitting elements is three and are respectively used to provide colored lights of different wavelengths, and the number of the light sensor is one, And the one light sensor is located on the same side of the three light emitting elements. 3. The display panel as claimed in claim 1, wherein the first thin film transistor, the circuit layer, the pixel definition layer and the light emitting elements are formed on a first substrate, and the light sensors are formed on a first substrate On the second substrate, the first thin film transistor, the wiring layer, the pixel definition layer, the light emitting elements and the photosensors are located between the first substrate and the second substrate, and the display panel also includes At least one dielectric layer is disposed between the pixel definition layer and the light sensors. 4. The display panel of claim 1, further comprising: A second thin film transistor is electrically connected to the light sensor. 5. The display panel as claimed in claim 3, wherein the first substrate comprises a capacitive element. 6. The display panel as claimed in claim 1, wherein the light sensor comprises a metal electrode layer, the vertical projection of the metal electrode layer on the pixel definition layer and the vertical projection of the capacitive element on the pixel definition layer overlapping. 7. The display panel as claimed in claim 6, wherein the light sensor further comprises a light sensing layer, the light sensing layer has a lower surface and at least one side surface, the lower surface faces the pixel definition layer and is connected to The side surface, and the lower surface and the side surface are covered by the metal electrode layer. 8. The display panel as claimed in claim 3, wherein a gap exists between the first substrate and the second substrate. 9. The display panel as claimed in claim 3, wherein the dielectric layer extends toward the pixel definition layer to form a recess, wherein the light sensor is located in the recess. 10. The display panel as claimed in claim 1, wherein the circuit layer is a gate electrode, a conductive layer, and a source/drain contact layer of the first substrate.

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