CN114578610A - Display panel - Google Patents

Abstract

A display panel, comprising: at least one thin film transistor; a circuit layer electrically connected to the thin film transistor; a pixel definition layer disposed on the circuit layer; a plurality of light-emitting elements disposed on the circuit layer and passing through the circuit The layers are electrically connected to the thin film transistor, wherein the light-emitting elements respectively include a plurality of light-emitting layers, located in the pixel definition layer; and a plurality of light sensors, arranged on the pixel definition layer, wherein the display panel has A plurality of pixel areas, the photo sensors are located in the pixel areas respectively, and form a plurality of overlapping areas with the circuit layer, and the overlapping areas are equal to each other, and the photo sensors provide the function of identifying fingerprints .

Description

display panel

This application is a divisional application for an invention patent application with the applicant being AUO Optoelectronics Co., Ltd., the application date is January 28, 2019, the application number is 201910079389.6, and the invention name is "display panel".

technical field

The present invention relates to a display panel.

Background technique

With the development of technology, various portable electronic devices have gradually become mainstream products in the consumer market, such as smart phones, smart watches, tablet computers or notebook computers. The functions of these portable electronic devices are gradually becoming more and more abundant along with the market trend. For example, the user's private information, photos, and mobile payment authorization can be recorded therein. Therefore, such portable electronic devices are also equipped with identity authentication to ensure the privacy and security of users.

In this regard, due to the uniqueness of fingerprints, they have been used in identity authentication, so that portable electronic devices equipped with fingerprint authentication have also been developed. However, fingerprint authentication requires an additional sensor, which also leads to the issue of how to integrate the sensor with the original electronic device.

SUMMARY OF THE INVENTION

An embodiment of the present invention provides a display panel including a first thin film transistor, a pixel electrode, a display medium layer, a light shielding layer, a color filter layer, and a photo sensor. The pixel electrode is electrically connected to the first thin film transistor. The display medium layer is arranged on the pixel electrode. The light shielding layer is disposed on the display medium layer and includes a first opening pattern and a second opening pattern. The color filter layer is disposed on the display medium layer, wherein the vertical projection of the color filter layer on the display medium layer partially overlaps with the vertical projection of the first opening pattern of the light shielding layer on the display medium layer. The light sensor is disposed on the display medium layer, wherein the vertical projection of the light sensor on the display medium layer partially overlaps with the vertical projection of the second opening pattern of the light shielding layer on the display medium layer.

In some embodiments, the display panel further includes a second thin film transistor. The second thin film transistor is electrically connected to the light sensor, wherein the light shielding layer is located between the display medium layer and the second thin film transistor.

In some embodiments, the photo sensor includes a metal electrode layer, and the vertical projection of the metal electrode layer on the display medium layer partially overlaps with the vertical projection of the first thin film transistor on the display medium layer.

In some embodiments, the light sensor further includes a light sensing layer, the light sensing layer has a lower surface and a side surface, the lower surface faces the array substrate and is connected to the side surface, and the lower surface and the side surface are covered by a metal electrode layer .

In some embodiments, the display panel further includes an insulating layer. The insulating layer is disposed on the light-shielding layer and extends toward the display medium layer through the second opening pattern to form a recessed portion, wherein the photo sensor is located in the recessed portion and is separated from the light-shielding layer by the insulating layer.

In some embodiments, the vertical projection of the light sensor on the display medium layer partially overlaps with the vertical projection of the light shielding layer on the display medium layer.

In some embodiments, the photosensors are respectively located in the pixel regions of the display panel, and the display panel further includes a circuit layer between the first thin film transistor and the pixel electrode, wherein the photosensors and the light shielding layer are formed in multiple pieces. overlapping area, and these multiple overlapping areas are equal to each other.

An embodiment of the present invention provides a display panel including a thin film transistor, a circuit layer, a light emitting layer and a photo sensor. The thin film transistor is electrically connected to the circuit layer. The light-emitting layer is arranged on the circuit layer and is electrically connected to the circuit layer. The photo sensors are arranged on the circuit layer, wherein the display panel has a pixel area, and the photo sensors are respectively located in the pixel areas and form multiple overlapping areas with the circuit layer, and the overlapping areas are equal to each other.

In some embodiments, in each pixel area, the number of light-emitting elements is three and they are respectively used to provide color light of different wavelengths, the number of photo-sensors is one, and the photo-sensors are located in three light-emitting areas. the same side of the element.

In some embodiments, the thin film transistor, the circuit layer, the pixel definition layer and the light emitting element are formed on the first substrate, the photo sensor is formed on the second substrate, the thin film transistor, the circuit layer, the pixel definition layer, the light emitting element and the light emitting element are formed on the second substrate. The sensor is located between the first substrate and the second substrate, and the display panel further includes a dielectric layer disposed between the pixel definition layer and the light sensor.

Through the above configuration, in addition to integrating the light sensor into the display panel to provide the function of recognizing fingerprint patterns, since each pixel area of the display panel can provide the function of recognizing fingerprints, it can improve the performance of the display panel. screen ratio, and also makes the display panel suitable for a display device designed as a full-screen type.

Description of drawings

1A is a top view illustrating a plurality of pixel regions of a display panel according to a first embodiment of the present disclosure.

Fig. 1B is a schematic cross-sectional view along line 1B-1B' of Fig. 1A.

Fig. 1C is a schematic cross-sectional view along line 1C-1C' of Fig. 1A.

1D shows a schematic diagram of a display panel to which the first embodiment is applied.

2A is a top view illustrating a plurality of pixel regions of a display panel according to a second embodiment of the present disclosure.

Fig. 2B is a schematic cross-sectional view along line 2B-2B' of Fig. 2A.

Fig. 2C is a schematic cross-sectional view along line 2C-2C' of Fig. 2A.

FIG. 2D shows a schematic diagram of the lower substrate and the upper substrate being assembled together.

FIG. 2E shows a schematic diagram of a display panel to which the second embodiment is applied.

Description of reference numbers:

10 fingers

20 rays

100A, 100B display panel

102, 106 pixel area

104A, 104B, 104C, 108A, 108B, 108C sub-pixel area

110 backlight module

200, 500 lower substrate

210 first polarizer

220 first substrate

222 first shading layer

224 first buffer layer

230 first thin film transistor

240 first gate insulating layer

242 first interlayer dielectric layer

244 first source/drain contact layer

246 first passivation layer

248 common electrodes

250 first dielectric layer

252 pixel electrodes

300 display medium layers

400, 600 upper substrate

410 second dielectric layer

420 color filter layer

422 red filter layer

424 green filter layer

426 blue filter layer

430 second shading layer

432 first opening pattern

434 second opening pattern

440 third dielectric layer

442 depression

450, 620 light sensor

452, 622 metal electrode layer

454, 624 light sensing layer

456, 626 light-transmitting electrode layer

462 fourth dielectric layer

464 second source/drain contact layer

466 second interlayer dielectric layer

468 second gate insulating layer

470 second thin film transistor

480 second buffer layer

482 third shading layer

484 second substrate

486 second polarizer

502, 602 layers

510 third substrate

512 third buffer layer

520 third thin film transistor

530 capacitive element

540 third gate insulating layer

542 first conductive layer

544 fourth gate insulating layer

546 second conductive layer

548 third interlayer dielectric layer

550 third source/drain contact layer

552 fifth dielectric layer

554 third conductive layer

556 second passivation layer

560px definition layer

567 opening

570, 570A, 570B light-emitting element

572 lower electrode

574 light-emitting layer

576 upper electrode

610 sixth dielectric layer

630 seventh dielectric layer

632 Fourth source/drain contact layer

634 fourth interlayer dielectric layer

636 fifth gate insulating layer

640 fourth thin film transistor

650 fourth buffer layer

652 fourth shading layer

654 fourth substrate

656 third polarizer

700 Clearance

702 Support Structure

1B-1B', 1C-1C', 2B-2B', 2C-2C' line segments

D drain region

G gate

DH lateral direction

DV portrait orientation

L1 distance

L2 distance

S source region

S1 lower surface

S2 side surface

SC channel area

TH1 first contact hole

TH2 second contact hole

TH3 third contact hole

TH4 fourth contact hole

TH5 fifth contact hole

TH6 sixth contact hole

TH7 seventh contact hole

TH8 eighth contact hole

TH9 ninth contact hole

TH10 tenth contact hole

Detailed ways

Various embodiments of the present invention will be disclosed below with accompanying drawings, and for the sake of clarity, many practical details will be described together in the following description. It should be understood, however, that these practical details should not be used to limit the invention. That is, in some embodiments of the invention, these practical details are unnecessary. Furthermore, for the purpose of simplifying the drawings, some conventional structures and elements will be shown in a simplified and schematic manner in the drawings.

In this document, the terms first, second, and third, etc., are used to describe various elements, components, regions, layers, and it will be understood. However, these elements, components, regions, layers should not be limited by these terms. These terms are limited to identifying a single element, component, region, or layer. Thus, a first element, component, region or layer hereinafter could be termed a second element, component, region or layer without departing from the scope of the invention.

Please refer to FIGS. 1A , 1B and 1C. FIG. 1A is a top view of a plurality of pixel regions 102 of a display panel 100A according to a first embodiment of the present disclosure, and FIG. 1B is a schematic cross-sectional view along line 1B- 1B′ of FIG. 1A 1C is a schematic cross-sectional view along the line 1C-1C' of FIG. 1A.

As shown in FIG. 1A , the display panel 100A has a plurality of pixel regions 102 , and these pixel regions 102 may be arranged in an array form along the horizontal direction DH and the vertical direction DV of FIG. 1A . For each pixel area 102, it can have three sub-pixel areas 104A, 104B, 104C, wherein the sub-pixel areas 104A, 104B, 104C can be used to provide different colors, such as three colors of red, green, and blue.

1B and FIG. 1C , the display panel 100A includes a backlight module 110 , a lower substrate 200 , a display medium layer 300 and an upper substrate 400 , wherein the backlight module 110 is connected to the lower substrate 200 , and the display medium layer 300 is located between the lower substrate 200 and the upper substrate 400 . between the substrates 400 . The backlight module 110 is used for emitting light beams toward the lower substrate 200 , the display medium layer 300 and the upper substrate 400 , and the upper surface of the upper substrate 400 can be used as the display surface of the display panel 100A.

The lower substrate 200 includes a first polarizer 210, a first substrate 220, a first light shielding layer 222, a first buffer layer 224, a plurality of first thin film transistors 230, a first gate insulating layer 240, and a first interlayer dielectric layer 242, the first source/drain contact layer 244, the first passivation layer 246, the common electrode 248, the first dielectric layer 250 and the pixel electrode 252, wherein the first polarizer 210 is disposed on the backlight module 110 and the first between the substrates 220 . In some embodiments, the materials of the buffer layer, insulating layer, dielectric layer and passivation layer of the lower substrate 200 may be organic materials or inorganic materials, such as epoxy resin, silicon oxide (SiOx), silicon nitride ( SiNx), a composite layer composed of silicon oxide and silicon nitride, or other suitable dielectric materials.

The first substrate 220 is disposed on the first polarizer 210, wherein the first substrate 220 can be used as a carrier substrate of the lower substrate 200 in the process, for example, it can be a glass substrate, so that other components or layers of the lower substrate 200 can be formed on the first substrate 220 .

The first light shielding layer 222 , the first buffer layer 224 , the plurality of first thin film transistors 230 and the first gate insulating layer 240 are disposed on the first substrate 220 . The first buffer layer 224 is disposed on the first light shielding layer 222 , which can facilitate the formation of the first thin film transistor 230 . The first thin film transistor 230 is formed at a position corresponding to the first light shielding layer 222, wherein the first light shielding layer 222 has light shielding properties, such as metal, organic or inorganic materials, to shield the light traveling toward the first thin film transistor 230 from below, Therefore, the leakage current of the first thin film transistor 230 due to exposure to light is prevented.

Each of the first thin film transistors 230 includes a source region S, a drain region D, a channel region SC and a gate G, wherein the source region S, the drain region D and the channel region SC can be formed from the same layer and can be formed by diffusion The process adjusts the carrier concentration of the same layer to define the location of each region, wherein the layer may be a crystalline silicon material. The first gate insulating layer 240 covers the source region S, the drain region D and the channel region SC, and the gate G is disposed on the first gate insulating layer 240, and the setting position of the gate G is the same as that of the channel region. corresponding to SC.

The first interlayer dielectric layer 242 is disposed on the first gate insulating layer 240 and covers the gate G, wherein the first gate insulating layer 240 and the first interlayer dielectric layer 242 have a first contact hole TH1 in common. The first source/drain contact layer 244 is disposed on the first interlayer dielectric layer 242, wherein the first source/drain contact layer 244 may include a metal material. The first source/drain contact layer 244 can contact the source region S and the drain region D of the first thin film transistor 230 through the first contact hole TH1 , so as to be electrically connected to the first thin film transistor 230 . The gate G of the first thin film transistor 230 and the first source/drain contact layer 244 can be regarded as a circuit layer of the lower substrate 200 .

The first passivation layer 246 is disposed on the first interlayer dielectric layer 242 and covers at least part of the first source/drain contact layer 244 . The common electrode 248 and the first dielectric layer 250 are disposed on the first passivation layer 246, wherein the first dielectric layer 250 covers the common electrode 248, and the first dielectric layer 250 and the first passivation layer 246 may have a first Two contact holes TH2. The pixel electrode 252 is disposed on the first dielectric layer 250, and the pixel electrode 252 can contact the first source/drain contact layer 244 through the first dielectric layer 250 and the second contact hole TH2 of the first passivation layer 246, Therefore, it is electrically connected to the drain region D of the first thin film transistor 230 through the first source/drain contact layer 244 . In some embodiments, the materials of the common electrode 248 and the pixel electrode 252 include transparent conductive materials, such as indium tin oxide, indium zinc oxide, zinc oxide, carbon nanotubes, indium gallium zinc oxide or other suitable materials.

The display medium layer 300 is disposed on the common electrode 248 and the pixel electrode 252, and may have a display medium. For example, the display medium layer 300 can be a liquid crystal layer and has liquid crystal molecules. When the first thin film transistor 230 is driven so that the common electrode 248 and the pixel electrode 252 have different potentials, the common electrode 248 and the pixel electrode 252 can be coupled out of an electric field, so as to control the display medium of the display medium layer 300 to control the display medium from the lower substrate 200 Polarization of light traveling toward the upper substrate 400 .

The upper substrate 400 includes a second dielectric layer 410, a color filter layer 420, a second light shielding layer 430, a third dielectric layer 440, a photo sensor 450, a fourth dielectric layer 462, and a second source/drain electrode The contact layer 464 , the second interlayer dielectric layer 466 , the second gate insulating layer 468 , the second thin film transistor 470 , the second buffer layer 480 , the third light shielding layer 482 , the second substrate 484 and the second polarizer 486 . In some embodiments, the materials of the buffer layer, insulating layer, dielectric layer and passivation layer of the upper substrate 400 may be organic materials or inorganic materials, such as epoxy resin, silicon oxide (SiOx), silicon nitride ( SiNx), a composite layer composed of silicon oxide and silicon nitride, or other suitable dielectric materials.

The second dielectric layer 410 is disposed on the display medium layer 300 . The color filter layer 420 and the second light shielding layer 430 are disposed on the second dielectric layer 410 . The second light shielding layer 430 has a first opening pattern 432 and a second opening pattern 434. The first opening pattern 432 and the second opening pattern 434 can be formed by a patterning process. For example, a light shielding material can be used to form a layer, and then The light-shielding material is subjected to a patterning process to form a second light-shielding layer 430 having a first opening pattern 432 and a second opening pattern 434 . The vertical projection of the color filter layer 420 on the display medium layer 300 partially overlaps with the vertical projection of the first opening pattern 432 of the second light shielding layer 430 on the display medium layer 300 . Specifically, the color filter layer 420 includes a red filter layer 422, a green filter layer 424 and a blue filter layer 426, wherein the bottom of the red filter layer 422 is located on the second light shielding layer 430 and the second dielectric layer 410, and the top of the red filter layer 422 is located in the first opening pattern 432, so the vertical projection of the red filter layer 422 located in the first opening pattern 432 on the display medium layer 300 will be different from the second light shielding The vertical projections of the first opening patterns 432 of the layer 430 on the display medium layer 300 overlap. The configuration of the green filter layer 424 and the blue filter layer 426 may be similar to that of the red filter layer 422 , and details are not described herein again. Through this configuration, the light traveling from the display medium layer 300 to the upper substrate 400 can pass through the first opening pattern 432 of the second light shielding layer 430 and the color filter layer 420 located therein, so as to have a corresponding color, and Thereby, the display panel 100A displays an image.

The third dielectric layer 440 is disposed on the color filter layer 420 and the second light shielding layer 430 , wherein a part of the third dielectric layer 440 passes through the second opening pattern 434 of the second light shielding layer 430 and extends toward the display medium layer 300 , to form the recessed portion 442 . In other words, the third dielectric layer 440 can pass through the second opening pattern 434 of the second light shielding layer 430 from a position higher than the second light shielding layer 430 and extend to a position lower than the second light shielding layer 430 to form the recessed portion 442 , the recessed portion 442 formed therein can contact the second dielectric layer 410 , and the interface between the recessed portion 442 and the second dielectric layer 410 is located under the second light shielding layer 430 . For example, the minimum vertical distance from the recessed portion 442 to the display medium layer 300 can be marked as the distance L1, the minimum vertical distance from the second light shielding layer 430 to the display medium layer 300 can be marked as the distance L2, and the distance L1 is smaller than the distance L2 .

The light sensor 450 is disposed on the display medium layer 300 , and the vertical projection of the light sensor 450 on the display medium layer 300 and the vertical projection of the second opening pattern 434 of the second light shielding layer 430 on the display medium layer 300 Partially overlapping. Specifically, the photo sensor 450 is located on the recessed portion 442 of the third dielectric layer 440 and is in contact with the third dielectric layer 440 , wherein the photo sensor 450 can be connected to the second dielectric layer 440 through the third dielectric layer 440 . The light shielding layer 430 is spaced apart. By arranging the photo sensor 450 on the recessed portion 442 of the third dielectric layer 440 , since the recessed portion 442 extends from a position higher than the second light shielding layer 430 to a position lower than the second light shielding layer 430 , it can be It is avoided that the thickness of the display panel 100A is excessively increased due to the configuration of the light sensor 450 .

In addition, the installation position of the photo sensor 450 is staggered from the installation position of the color filter layer 420, so as to prevent the photo sensor 450 from affecting the light output of the color filter layer 420 and affecting the image quality of the display panel 100A . Specifically, as shown in FIG. 1A , in each pixel area 102 of the display panel 100A, the three sub-pixel areas 104A, 104B and 104C are composed of the red filter layer 422 and the green filter layer of the color filter layer 420 respectively. 424 and the blue filter layer 426, and each pixel area 102 is configured with a photo sensor 450, wherein the photo sensor 450 is located in the red filter layer 422, the green filter layer 424 and the blue Since the light sensor 450 is on the same side of the color filter layer 426 , the light output of the color filter layer 420 will not be affected by the light sensor 450 .

On the other hand, since the light sensor 450 in each pixel area 102 is located on the same side of the red filter layer 422 , the green filter layer 424 and the blue filter layer 426 of the color filter layer 420 , it can be It is considered that the installation position of the light sensor 450 and the installation position of the color filter layer 420 are independent of each other. For example, even if the spacing between the red filter layer 422, the green filter layer 424 and the blue filter layer 426 of the color filter layer 420 is changed or the respective widths are increased or decreased, the light sensor 450 can still be used. Set in its original position without additionally changing the setting position corresponding to the spacing change or width change of the filter layer.

In the case where the arrangement position of the light sensor 450 is independent of the arrangement position of the color filter layer 420, the light sensor 450 of each pixel area 102 can be configured in the same way, which is beneficial to simplify the process. For example, the mask pattern used to fabricate the light sensor 450 can be simplified. Furthermore, in the case where the photosensors 450 in each pixel area 102 are configured in the same manner, these photosensors 450 can be connected with the circuit layers of the lower substrate 200 (including the gate G and the first source/ The drain contact layer 244) forms a plurality of overlapping areas (that is, areas that overlap each other in a top view), and these overlapping areas are equal to each other, so as to avoid unexpected differences between different pixel regions 102, Therefore, the phenomenon of uneven brightness of the image of the display panel 100A is prevented.

Please return to FIG. 1B and FIG. 1C again. The light sensor 450 includes a metal electrode layer 452 , a light sensing layer 454 and a light-transmitting electrode layer 456 , wherein the metal electrode layer 452 contacts the third dielectric layer 440 , and the light-sensing layer 454 and the light-transmitting electrode layer 456 are stacked On the metal electrode layer 452 , the light sensing layer 454 is located between the metal electrode layer 452 and the light-transmitting electrode layer 456 . The material of the photo-sensing layer 454 includes silicon rich oxide, and has the characteristic of generating electron-hole pairs when exposed to light. With this characteristic, the photo-sensor 450 can achieve a photo-sensing effect.

The metal electrode layer 452 can be conformal to the third dielectric layer 440 thereunder to form a concave shape, wherein the vertical projection of the metal electrode layer 452 on the display medium layer 300 is the same as the vertical projection of the first thin film transistor 230 on the display medium layer 300 Can partially overlap. Since the metal electrode layer 452 is not light-transmitting, the metal electrode layer 452 can shield the first thin film transistor 230 overlapping the metal electrode layer 452. Therefore, when the display panel 100A is viewed from a top view (ie, viewed from the top of FIGS. 1B and 1C , the When displaying the panel 100A), the first thin film transistor 230 located under the second opening pattern 434 of the second light shielding layer 430 cannot be seen. In addition, the vertical projection of the metal electrode layer 452 on the display medium layer 300 may also partially overlap with the vertical projection of the second light shielding layer 430 on the display medium layer 300 . A gap between the light shielding layer 430 and the metal electrode layer 452 .

The photo-sensing layer 454 has a lower surface S1 and a side surface S2, wherein the lower surface S1 of the photo-sensing layer 454 faces the display medium layer 300 and is connected to the side surface S2 of the photo-sensing layer 454, and the lower surface of the photo-sensing layer 454 S1 and the side surface S2 are covered by the metal electrode layer 452, so that the light beam passing through the photo-sensing layer 454 from top to bottom will then proceed to the metal electrode layer 452, and the metal electrode layer 452 can prevent this from passing through the photo-sensing layer The light beam of the layer 454 travels to the display medium layer 300 , so as to avoid unintended effects on the elements or layers of the lower substrate 200 due to illumination. In addition, the photo-sensing layer 454 can be conformal to the metal electrode layer 452 below it and also present a concave shape, wherein the light-transmitting electrode layer 456 can be located in the depression of the photo-sensing layer 454 correspondingly, and the upper part of the photo-sensing layer 454 The surface is substantially coplanar with the upper surface of the light-transmitting electrode layer 456 . In some embodiments, the material of the light-transmitting electrode layer 456 includes a transparent conductive material, such as indium tin oxide, indium zinc oxide, zinc oxide, carbon nanotubes, indium gallium zinc oxide or other suitable materials.

The fourth dielectric layer 462, the second source/drain contact layer 464, the second interlayer dielectric layer 466, the second gate insulating layer 468, and the second thin film transistor 470 are disposed on the third dielectric layer 440 and the light above sensor 450 . The fourth dielectric layer 462 covers the third dielectric layer 440 and the photo sensor 450, and has a third contact hole TH3, and a part of the metal electrode layer 452 of the photo sensor 450 is located in the third contact hole TH3 . The second source/drain contact layer 464 is disposed on the fourth dielectric layer 462 and covered by the second interlayer dielectric layer 466, wherein the second source/drain contact layer 464 may include a metal material. The second source/drain contact layer 464 is located between the fourth dielectric layer 462 and the second interlayer dielectric layer 466 . In addition, the second source/drain contact layer 464 can contact the metal electrode layer 452 located in the third contact hole TH3 so as to be electrically connected to the photo sensor 450 .

The second gate insulating layer 468 and the second thin film transistor 470 are disposed on the second interlayer dielectric layer 466 , wherein the second thin film transistor 470 includes a source region S, a drain region D, a channel region SC and a gate G , in which the source region S, the drain region D and the channel region SC can be formed by the same layer, and the positions of the regions can be defined by adjusting the carrier concentration of the same layer through a diffusion process. The second gate insulating layer 468 covers the gate G, so that the gate G is located between the second interlayer dielectric layer 466 and the second gate insulating layer 468, and the setting position of the gate G is close to the channel region corresponding to SC. The second gate insulating layer 468 and the second interlayer dielectric layer 466 may have a fourth contact hole TH4 in common, and the second source/drain contact layer 464 may contact the second thin film transistor 470 through the fourth contact hole TH4 The source region S and the drain region D, thereby electrically connecting the second thin film transistor 470 to the photo sensor 450 .

The second thin film transistor 470 may be located above the second light shielding layer 430, and the second light shielding layer 430 is located between the display medium layer 300 and the second thin film transistor 470, so as to prevent the lower substrate 200 from radiating toward and passing through the display medium The light beam of the layer 300 will be irradiated to the second thin film transistor 470 to generate a leakage current. Specifically, the vertical projection of the channel region SC of the second thin film transistor 470 to the display medium layer 300 may overlap with the vertical projection of the second light shielding layer 430 to the display medium layer 300, thereby preventing the light beam from the display medium layer 300 from being irradiated to the display medium layer 300. The channel region SC of the second thin film transistor 470 .

The second buffer layer 480 and the third light shielding layer 482 are disposed on the second gate insulating layer 468 and the second thin film transistor 470, wherein the second buffer layer 480 can facilitate the formation of the second thin film transistor 470, and the third light shielding layer 482 The formation position of , at least corresponds to the channel region SC of the second thin film transistor 470 , so as to prevent the channel region SC of the second thin film transistor 470 from generating leakage current due to light from above.

The second substrate 484 is disposed on the second buffer layer 480 and the third light shielding layer 482 , and the second polarizer 486 is disposed on the second substrate 484 . The second substrate 484 can be used as a carrier substrate in the process of the upper substrate 400, and it can be, for example, a glass substrate. For example, the layers or elements of the upper substrate 400 can be formed on the second substrate 484 first, and after the second light shielding layer 430 and the color filter layer 420 are formed, the second dielectric layer 410 can be formed. is a flat layer. After the second dielectric layer 410 is formed, the upper substrate 400 can be turned over so that the second dielectric layer 410 is located on the bottom side, and the upper substrate 400 can be assembled on the lower substrate 200, wherein the display medium layer 300 It is filled between the lower substrate 200 and the upper substrate 400 to complete the structure shown in FIG. 1B and FIG. 1C .

Please refer to FIG. 1D again. FIG. 1D shows a schematic diagram of the display panel 100A to which the first embodiment is applied. The left and right half structures of the display panel 100A shown in FIG. 1D may be the same as those of FIG. 1B and FIG. 1C respectively. In order not to complicate the drawing, some elements in FIG. 1D are not marked with reference symbols.

The display panel 100A of the first embodiment can detect the fingerprint pattern of the user through the light sensor 450 . For example, when the user's finger 10 covers and touches the display panel 100A, the light 20 emitted by the backlight module 110 can enter and pass through the second light shielding layer after passing through the lower substrate 200 and the display medium layer 300 . The color filter layer 420 in the first opening pattern 432 of 430 , and then travels to and reflects from the finger 10 . The light 20 reflected by the finger 10 can return to the upper substrate 400 and enter the photo-sensing layer 454 of the photo-sensor 450 after passing through the layers in the upper substrate 400 . Since the pattern of the finger 10 has peaks and valleys, and the reflection directions of the light 20 at the peaks and valleys are different, different light sensors 450 of the display panel 100A will receive reflected light with different intensities, These reflected lights with different intensities can analyze the fingerprint pattern of the user's finger 10 .

To sum up the above, in this embodiment, the color filter layer 420 , the second light shielding layer 430 and the photo sensor 450 can be jointly integrated into the upper substrate 400 of the display panel 100A, so as to avoid the display caused by the configuration of the photo sensor 450 A situation in which the thickness of the panel 100A is excessively increased. Through this configuration, the light sensors 450 can be respectively arranged in the plurality of pixel areas 102 of the display panel 100A, so that each pixel area 102 of the display panel 100A can provide the function of recognizing fingerprints, that is, the display panel In addition to providing images, the display surface of 100A can also be used as a user's fingerprint identification area, thereby increasing the screen ratio of the display panel 100A, so that the display panel 100A is suitable for designing a full-screen display device.

Please refer to FIGS. 2A , 2B and 2C. FIG. 2A is a top view illustrating a plurality of pixel regions 106 of the display panel 100B according to the second embodiment of the present disclosure, and FIG. 2B is a view along the line segment 2B-2B' of FIG. 2A . A schematic cross-sectional view, FIG. 2C is a schematic cross-sectional view along the line segment 2C-2C' of FIG. 2A . At least one difference between this embodiment and the first embodiment is that the display panel 100B of this embodiment provides images by emitting light from the light-emitting layer.

As shown in FIG. 2A , the display panel 100B has a plurality of pixel regions 106 , and these pixel regions 106 may be arranged in the form of an array along the horizontal direction DH and the vertical direction DV of FIG. 2A . For each pixel area 106, it can have three sub-pixel areas 108A, 108B, 108C, wherein the sub-pixel areas 108A, 108B, 108C can be used to provide different colors, such as red, green, blue three colors.

The display panel 100B includes a lower substrate 500 and an upper substrate 600 , wherein the upper substrate 600 is located on the lower substrate 500 , and the upper surface of the upper substrate 600 can be used as the display surface of the display panel 100B. The lower substrate 500 and the upper substrate 600 can be independently fabricated and assembled together after they are fabricated separately.

For example, please see FIG. 2D first. FIG. 2D shows a schematic diagram of the lower substrate 500 and the upper substrate 600 being assembled together. The lower substrate 500 and the upper substrate 600 respectively include a third substrate 510 and a fourth substrate 654, which may be, for example, glass substrates. In order not to complicate the drawing too much, the layer formed on the third substrate 510 of the lower substrate 500 is represented by the layer 502 , and the layer formed on the fourth substrate 654 of the upper substrate 600 is represented by the layer 602 , and the upper The third polarizer of the substrate 600 is arranged on the fourth substrate 654 . The display panel 100B may further include a support structure 702, wherein the support structure 702 may be glass, ceramic or other frame with sufficient support strength. The support structure 702 is disposed between the lower substrate 500 and the upper substrate 600 , so that the upper substrate 600 can be fixed above the lower substrate 500 and a gap 700 can exist between the lower substrate 500 and the upper substrate 600 . In the embodiment depicted in Figure 2D, the gap 700 may be an air gap. In other embodiments, a solid dielectric material may also be filled between the lower substrate 500 and the upper substrate 600 .

Please return to FIG. 2B and FIG. 2C. The lower substrate 500 includes a third substrate 510, a third buffer layer 512, a plurality of third thin film transistors 520, a capacitive element 530, a third gate insulating layer 540, a first conductive layer 542, a fourth gate insulating layer 544, a third gate insulating layer 540, and a third gate insulating layer 540. Two conductive layers 546, a third interlayer dielectric layer 548, a third source/drain contact layer 550, a fifth dielectric layer 552, a third conductive layer 554, a second passivation layer 556, a pixel definition layer 560, and Light-emitting element 570. In some embodiments, the materials of the buffer layer, insulating layer, dielectric layer and passivation layer of the lower substrate 500 may be organic materials or inorganic materials, such as epoxy resin, silicon oxide (SiOx), silicon nitride ( SiNx), a composite layer composed of silicon oxide and silicon nitride, or other suitable dielectric materials.

The third substrate 510 can be used as a carrier substrate in the process of the lower substrate 500, for example, it can be a glass substrate, so that other elements or layers of the lower substrate 500 can be formed on the third substrate 510 in the process.

The third buffer layer 512 , the plurality of third thin film transistors 520 , the third gate insulating layer 540 and the fourth gate insulating layer 544 are disposed on the third substrate 510 , and the third thin film transistors 520 are located on the third buffer layer 512 , wherein the third buffer layer 512 can facilitate the formation of the third thin film transistor 520 . Each of the third thin film transistors 520 includes a source region S, a drain region D, a channel region SC and a gate G, wherein the source region S, the drain region D and the channel region SC can be formed from the same layer and can be formed by diffusion The process adjusts the carrier concentration of this same layer to define the location of each region. The third gate insulating layer 540 covers the source region S, the drain region D and the channel region SC, and the gate G is disposed on the third gate insulating layer 540, and the setting position of the gate G is the same as that of the channel region. corresponding to SC. The fourth gate insulating layer 544 is disposed on the third gate insulating layer 540 and covers the gate G.

The capacitive element 530 and the first conductive layer 542 are disposed on the third buffer layer 512 . The source region S, the drain region D and the channel region SC of the capacitive element 530 and the third thin film transistor 520 can be formed through the same layer, and then the carrier concentration of each region is adjusted through a diffusion process, wherein the layer can be crystalline silicon Material. The first conductive layer 542 is disposed on the third gate insulating layer 540, and the first conductive layer 542 and the gate G of the third thin film transistor 520 can be formed by the same layer, for example, by patterning the same metal layer. . The capacitive element 530 and the first conductive layer 542 can provide electrical communication in the lower substrate 500 .

The second conductive layer 546, the third interlayer dielectric layer 548, and the third source/drain contact layer 550 are disposed on the fourth gate insulating layer 544, wherein the third source/drain contact layer 550 may include metal Material. The third interlayer dielectric layer 548 covers the fourth gate insulating layer 544 and the second conductive layer 546 . The third gate insulating layer 540 , the fourth gate insulating layer 544 and the third interlayer dielectric layer 548 may have a fifth contact hole TH5 in common, and the fourth gate insulating layer 544 and the third interlayer dielectric layer 548 may There are sixth contact holes TH6 in common, and the third interlayer dielectric layer 548 may have a seventh contact hole TH7. The third source/drain contact layer 550 is disposed on the third interlayer dielectric layer 548 and can be electrically connected to the corresponding layer body through different contact holes. Specifically, the third source/drain contact layer 550 may extend to the source region S or the drain region D of the third thin film transistor 520 through the fifth contact hole TH5 , so as to be connected with the source region of the third thin film transistor 520 S or the drain region D is electrically connected. In addition, the third source/drain contact layer 550 can also extend to the capacitive element 530 through the fifth contact hole TH5, so as to be electrically connected to the capacitive element 530; The drain contact layer 550 may extend to the gate G of the third thin film transistor 520 through the sixth contact hole TH6, so as to be electrically connected with the gate G of the third thin film transistor 520. In addition, the third source/drain contact layer 550 can also extend to the first conductive layer 542 through the sixth contact hole TH6, so as to be electrically connected to the first conductive layer 542; the third source/drain contact layer 550 can extend to the second conductive layer through the seventh contact hole TH7 layer 546 , so as to be electrically connected to the second conductive layer 546 .

The fifth dielectric layer 552, the third conductive layer 554 and the second passivation layer 556 are disposed on the third interlayer dielectric layer 548, wherein the fifth dielectric layer 552 covers the third source/drain contact layer 550, and has an eighth contact hole TH8. The third conductive layer 554 and the second passivation layer 556 are disposed on the fifth dielectric layer 552, wherein the second passivation layer 556 covers the third conductive layer 554, so that the third conductive layer 554 is located on the fifth dielectric layer 552 and the second passivation layer 556, and the third conductive layer 554 can extend to the third source/drain contact layer 550 through the eighth contact hole TH8, so as to be electrically connected to the third source/drain contact layer 550. sexual connection.

In the structure of the lower substrate 500 , the gate G, the first conductive layer 542 , the second conductive layer 546 , the third source/drain contact layer 550 and the third conductive layer 554 of the third thin film transistor 520 can be used together as the lower The circuit layer of the substrate 500 is used for electrical communication.

The pixel definition layer 560 and the light-emitting element 570 are disposed on the second passivation layer 556 , wherein the light-emitting element 570 includes a lower electrode 572 , a light-emitting layer 574 and an upper electrode 576 . The lower electrode 572 of the light-emitting element 570 is disposed on the second passivation layer 556 and covered by the pixel definition layer 560, wherein the second passivation layer 556 may have a ninth contact hole TH9, and the lower electrode 572 may pass through the ninth contact hole TH9 extends to the third conductive layer 554 to be electrically connected to the third thin film transistor 520 . The lower electrode 572 may be formed by performing a patterning process on the conductive layer body. In some embodiments, in the process of forming the lower electrode 572, the patterning process may further form the conductive layer after the patterning process to form the fourth conductive layer 558, wherein the fourth conductive layer 558 is located in the second passivation layer. It extends to the third conductive layer 554 through the ninth contact hole TH9 . In addition, the fourth conductive layer 558 can also be used as a circuit layer of the lower substrate 500 .

The light-emitting layer 574 of the light-emitting element 570 is disposed in the pixel definition layer 560 and is electrically connected to the lower electrode 572 . Here, the term "disposed in the pixel definition layer 560" means that after the pixel definition layer 560 is formed, a part of the pixel definition layer 560 can be removed to form an opening 567 in the pixel definition layer 560, and the opening 567 The lower electrode 572 is exposed, and then, the light-emitting layer 574 is formed in the opening 567 , and the light-emitting layer 574 can be disposed in the pixel definition layer 560 . The upper electrode 576 of the light-emitting element 570 is disposed on the pixel definition layer 560 and the light-emitting layer 574 and is electrically connected to the light-emitting layer 574 . In addition, the upper electrode 576 of the light emitting element 570 may extend to the fourth conductive layer 558 through the tenth contact hole TH10 of the pixel definition layer 560 , so as to be electrically connected to the circuit layer of the lower substrate 500 . When a bias voltage is applied to the pre-light-emitting layer 574 through the lower electrode 572 and the upper electrode 576 of the light-emitting element 570, the light-emitting layer 574 can emit light.

The material of the light emitting layer 574 of the light emitting element 570 may include organic materials, in other words, the light emitting element 570 may be an organic light emitting diode, wherein the wavelength of the color light provided by the light emitting element 570 may depend on the organic material of the light emitting layer 574 . For example, the light-emitting element 570 can provide red light, green light or blue light by selecting different organic materials of the light-emitting layer 574 . The material of the lower electrode 572 and the upper electrode 576 of the light-emitting element 570 may include transparent conductive materials, such as indium tin oxide, indium zinc oxide, zinc oxide, carbon nanotubes, indium gallium zinc oxide, or other suitable materials, or, Non-transparent conductive materials may be included, such as metals, alloys, or other suitable materials. In addition, the materials of the lower electrode 572 and the upper electrode 576 of the light-emitting element 570 may be different, for example, the lower electrode 572 is made of a non-transparent conductive material, and the upper electrode 576 is made of a transparent conductive material.

The structure of the upper substrate 600 of this embodiment is substantially the same as that of the upper substrate 400 of the first embodiment, however, the upper substrate 600 of this embodiment omits the color filter layer and the light shielding layer at the same horizontal position as the color filter layer layers (such as the color filter layer and the second light shielding layer of the first embodiment). Specifically, the upper substrate 600 of this embodiment includes a sixth dielectric layer 610 , a photo sensor 620 , a seventh dielectric layer 630 , a fourth source/drain contact layer 632 , and a fourth interlayer dielectric layer 634, fifth gate insulating layer 636, fourth thin film transistor 640, fourth buffer layer 650, fourth light shielding layer 652, fourth substrate 654, and third polarizer 656, wherein the photo sensor 620 includes a photo metal electrode The layer 622 , the photo-sensing layer 624 and the light-transmitting electrode layer 626 , and the fourth thin film transistor 640 includes a source region S, a drain region D, a channel region SC and a gate G. Since the detailed descriptions of these layers or elements have been described in the first embodiment, they will not be repeated here.

Similar to the first embodiment, the installation position of the photo sensor 620 and the installation position of the light emitting element 570 in this embodiment can be staggered, so as to prevent the photo sensor 620 from affecting the light output of the light emitting element 570 and the display on the display panel 100B. image quality. Specifically, as shown in FIG. 2A , in each pixel area 106 of the display panel, the three sub-pixel areas 108A, 108B, and 108C are respectively composed of three light-emitting elements that provide light of different colors (eg, red, green, and blue). 570A, 570, 570B are defined, and each pixel area 106 is configured with a light sensor 620, wherein the light sensor 620 is located on the same side of the three light-emitting elements 570A, 570, 570B, so the light sensing The device 620 will not affect the light output of the light emitting elements 570A, 570 and 570B.

On the other hand, since the photosensors 620 in each pixel area 106 are located on the same side of the light-emitting elements 570A, 570, and 570B, it can be considered that the placement position of the photosensors 620 is the same as that of the light-emitting elements 570A, 570, 570B, and 570A. The arrangement positions of 570B are independent of each other, and therefore, the light sensors 620 of each pixel area 106 can be configured in the same manner, which is beneficial to simplify the process.

Furthermore, when the photo sensors 620 in each pixel area 106 are configured in the same manner, these photo sensors 620 can form multiple overlapping areas with the circuit layers below them, and the overlapping areas are equal to each other. . The circuit layer may be, for example, the gate G, the first conductive layer 542 , the second conductive layer 546 , the third source/drain contact layer 550 and the third conductive layer 554 of the lower substrate 500 in FIGS. 2B and 2C . In FIG. 2A , the area in the pixel area 106 and outside the light sensor 620 and the light-emitting elements 570A, 570, and 570B showing the mesh bottom can be regarded as the circuit layer under the light sensor 620, and each pixel The wiring layers shown in the region 106 will form an overlapping area with the corresponding photosensors 620 . For two different pixel areas 106 , the two overlapping areas formed by the two photosensors 620 and the underlying circuit layer will be equal to each other, so that unexpected occurrences between different pixel areas 106 can be avoided. , thereby preventing uneven brightness of the image of the display panel 100B.

Please refer to FIG. 2E again. FIG. 2E shows a schematic diagram of the display panel 100B to which the second embodiment is applied. The left and right half structures of the display panel 100B shown in FIG. 2E may be the same as those of FIG. 2B and FIG. 2C respectively. In order not to complicate the drawing, some elements in FIG. 2E are not marked with reference symbols.

The display panel 100B of the second embodiment can detect the fingerprint pattern of the user through the light sensor 620 . For example, when the user's finger 10 covers and touches the display panel 100B, the light 20 emitted by the light-emitting layer 574 of the light-emitting element 570 can be reflected from the finger 10 after passing through the upper substrate 600 . The light 20 reflected by the finger 10 can return to the upper substrate 600 and enter the photo-sensing layer 624 of the photo-sensor 620 after passing through the layers in the upper substrate 400 , thereby analyzing the user's fingerprint pattern. Similarly, since the light sensors 620 are respectively disposed in the pixel areas 106 of the display panel 100B, each pixel area 106 of the display panel 100B can provide the function of identifying fingerprints, thereby increasing the screen ratio of the display panel 100B Also, the display panel 100B can be suitably designed as a full-screen display device.

To sum up, the display panel of the present disclosure includes a lower substrate and an upper substrate, wherein the upper substrate includes a photo sensor to provide a function of identifying a user's fingerprint pattern. The display panel assembled from the lower substrate and the upper substrate may be a liquid crystal display panel, or may also be an organic light emitting body type display panel.

In the case where the display panel assembled from the lower substrate and the upper substrate is a liquid crystal display panel, the photo sensor can be integrated with the light shielding layer and the color filter layer in the upper substrate, so as to avoid the display caused by disposing the photo sensor. A condition in which the thickness of the panel is excessively increased. In the case where the display panel assembled from the lower substrate and the upper substrate is an organic light emitting body type display panel, the installation position of the light sensor and the installation position of the light emitting element are independent of each other, thereby simplifying the process and avoiding the need for different pixel areas. There are unexpected differences.

Through the above configuration, in addition to integrating the light sensor into the display panel to provide the function of recognizing fingerprint patterns, since each pixel area of the display panel can provide the function of recognizing fingerprints, it can improve the performance of the display panel. The screen-to-body ratio also makes the display panel suitable for a display device designed as a full screen.

Although the present invention has been disclosed above in various embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The protection scope of the invention shall be determined by the claims.

Claims (10)

1. A display panel, comprising:

at least one first thin film transistor;

a circuit layer electrically connected to the first thin film transistor;

a pixel defining layer disposed on the circuit layer;

a plurality of light emitting elements disposed on the circuit layer and electrically connected to the first thin film transistor through the circuit layer, wherein the light emitting elements respectively comprise a plurality of light emitting layers disposed in the pixel defining layer; and

a plurality of photo-sensors disposed on the pixel defining layer, wherein the display panel has a plurality of pixel regions, the photo-sensors are respectively disposed in the pixel regions and form a plurality of overlapping areas with the circuit layer, and the overlapping areas are equal to each other,

the light sensor provides the function of identifying the fingerprint.

2. The display panel of claim 1, wherein in each of the pixel regions, the number of the light emitting elements is three and the light sensors are respectively configured to provide color lights with different wavelengths, the number of the light sensors is one, and the one light sensor is located on the same side of the three light emitting elements.

3. The display panel of claim 1, wherein the first thin film transistor, the circuit layer, the pixel defining layer, and the light emitting elements are formed on a first substrate, the light sensors are formed on a second substrate, the first thin film transistor, the circuit layer, the pixel defining layer, the light emitting elements, and the light sensors are located between the first substrate and the second substrate, and the display panel further comprises at least one dielectric layer disposed between the pixel defining layer and the light sensors.

4. The display panel of claim 1, further comprising:

a second thin film transistor electrically connected to the photo sensor.

5. The display panel of claim 3, wherein the first substrate comprises a capacitor.

6. The display panel of claim 1, wherein the photo sensor comprises a metal electrode layer, and a vertical projection of the metal electrode layer on the pixel defining layer partially overlaps a vertical projection of the capacitor on the pixel defining layer.

7. The display panel of claim 6, wherein the photo sensor further comprises a photo sensing layer having a lower surface and at least one side surface, the lower surface facing the pixel defining layer and connected to the side surface, and the lower surface and the side surface being covered by the metal electrode layer.

8. The display panel of claim 3, wherein a gap exists between the first substrate and the second substrate.

9. The display panel of claim 3, wherein the dielectric layer extends toward the pixel defining layer to form a recess, wherein the photo sensor is located in the recess.

10. The display panel of claim 1, wherein the circuit layer is a gate electrode, a conductive layer, a source/drain contact layer of the first substrate.

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