CN114548025B - Automated script writing and usage to solve long-line timing delays in physical design - Google Patents

Abstract

The invention discloses an automatic script writing and using method for solving the problem of physical design long line time sequence delay, which is characterized by comprising the following steps: setting a logic connection script; setting a main script; finding out a timing violation path to be optimized in a floorplan stage; setting parameters of a starting point, a terminal point and an inflection point according to the information of the timing violation path to be optimized; based on the logic connection script and the main script, according to different design processes, changing the setting of standard unit parameters of the buffer BUF and the inverter INV, changing the setting of the transverse and longitudinal distances of the buffer BUF and the inverter INV, and selecting required parameters; before placement, optimization is done in place and route PR tools. The invention is applied to the chip digital physical design layout and wiring stage to solve the influence caused by larger and larger line delay under advanced technology, and aims at a long path on a physical layer to minimize the line delay.

Description

Automated script writing and usage to solve long-line timing delays in physical design

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to an automatic script writing and using method for solving long-line timing delay in physical design.

Background Art

As semiconductor processes advance to 40nm, 28nm and below, physical timing in chip design becomes a design difficulty. Practice has found that after physical design and routing, the impact of line delay is far greater than the impact of standard cells contained in the logic design itself. Although automatic layout and routing tools can achieve optimization, physical design engineers are required to manually optimize paths with special requirements or tight timing one by one. If there are many paths, it will cause a lot of workload and extend the design cycle.

Summary of the invention

In order to solve the above technical problems, the present invention provides an automated script writing and using method for solving long-line timing delay in physical design with a short design cycle and high optimization efficiency.

The technical solution of the present invention to solve the above problem is: an automated script writing and using method for solving long-line timing delay in physical design, comprising the following steps:

Step S1: Setting a logic connection script, for the timing violation path, by setting the starting point, the end point, and the turning point, determining the adding location and connection of the buffer BUF standard unit, and the adding location and connection of the inverter INV standard unit, to ensure logic consistency;

Step S2: Setting the main script and setting the global variables of the timing violation path;

Step S3: Find the timing violation path to be optimized in the floorplan stage;

Step S4: according to the information of the timing violation path to be optimized and the layout plan of the design, set the parameters of the starting point, the end point, and the inflection point, and set the line name of the timing violation path to be optimized and the name of the connected end point standard cell port;

Step S5: Based on the logic connection script and the main script, according to different design processes, the standard unit types of the buffer BUF and the inverter INV are changed, the horizontal and vertical spacings between the inserted buffer BUF and the inverter INV are changed, and the required parameters are selected;

Step S6: Before layout and routing, complete optimization in the layout and routing PR tool.

In the above-mentioned automated script writing and using method for solving the long-line timing delay of physical design, in step S1, the optimization logic of the logic connection script for the line path to be optimized is to find the coordinates of the starting point and the end point of the line, and calculate according to the coordinate values; give priority to judging the routing direction of up, down, left, and right, and then calculate the path length according to the coordinates of the starting point and the end point, and insert the standard unit of the optimized timing in combination with the set spacing; therefore, first set the coordinates of the starting point and the end point of the timing violation path; set the variables as follows: the x coordinate of the path starting point x_begin, the y coordinate of the path starting point y_begin, the x coordinate of the path end point x_end, and the y coordinate of the path end point y_end;

In order to adapt to the specific situation of FloorPlan, set the inflection point in the middle. If branching is required, it can also be achieved through the inflection point. It should be noted that because it is an inflection point, the starting and ending points of the line between every two points must be horizontal and vertical. The inflection point variables are set to: inflection point x coordinate x_trunk*, inflection point y coordinate y_trunk*; the above * is an arbitrary serial number, which is used to distinguish different variables when multiple inflection points are used.

In the above-mentioned automated script writing and using method for solving long-line timing delays in physical design, in step S1, in the back-end physical design, if the starting point and end point coordinates of the timing violation path are fixed after floorplanning, then the specific values are set directly. If they cannot be determined, the corresponding coordinates are found through dbget to provide a feasible solution for the customized path.

In the above-mentioned method for writing and using an automated script to solve the long-line timing delay in physical design, in step S1, the process of determining the addition location and connection of the buffer BUF standard unit and the addition location and connection of the inverter INV standard unit is as follows:

(1) Calculate the number of inverters that need to be inserted based on the length of the line segment:

First, the coordinates of the starting point and the end point are used to determine the four directions of up, down, left, and right. Then, the inverter pair number a is calculated based on the distance and the set spacing. Inverters must be added in pairs to ensure logical consistency. However, it cannot be guaranteed that the path length will not exceed the specified length after the inverters are inserted in pairs at a fixed spacing. Therefore, a is rounded and set to b(int(a)). The number of INV pairs to be inserted subsequently is b. b is determined. If (a-b) is greater than the specified length, a buffer BUF is inserted. If (a-b) is less than the specified length, no buffer is inserted.

(2) Set loop logic:

The logic of the loop is that when the loop condition is met, a set of inverters INV and their connecting lines net are added, the inverter INV corresponding to the current variable is connected to the inverter of the previous variable, and the coordinate position of the pair of inverters is calculated according to the variables. The position is calculated by accumulating the required distance of the corresponding number on the starting coordinates, so a set of inverters INV and their connecting lines net are added in advance outside the loop;

Considering the effect of reducing the conversion time on the delay, a buffer BUF is added at the starting position, and then the first pair of inverters INV is added; the starting position is set to the edge of the starting unit; after the three standard units of the buffer BUF and the first pair of inverters INV are connected to the starting unit, the output end of the last standard unit, that is, the second inverter, is not connected, and is connected in the subsequent judgment;

The coordinates of the buffer BUF are calculated, when added horizontally and from left to right:

The x coordinate of the first BUF is x1, and the y coordinate is y1;

The x coordinate of the first INV is x1+distance_x, and the y coordinate is y1;

The x coordinate of the second INV is x1+2*distance_x, and the y coordinate is y1;

distance_x is the set horizontal distance; the same applies to other directions;

And set a special character target abbreviation tar to name the added standard unit and line, using the character composed of the endpoint standard unit name and its port name;

Because the added standard cells and lines need unique names, this ensures that there will be no duplicate names that will cause the script to fail to execute;

The naming is as follows:

First BUF name: [expr$trunk_num]_BUF_0_$tar

First INV name: [expr$trunk_num]_INV0_0_$tar

Second INV name: [expr$trunk_num]_INV1_0_$tar

trunk_num refers to the line segment number, INV0_0 refers to the 0th INV of the 0th pair of INVs, and INV1_0 refers to the first INV of the 0th pair of INVs;

After adding a set of inverters INV, there are three cases to be judged. In these three cases, the termination lines are set to the same name to ensure consistency and facilitate subsequent execution;

All the calculations for the following unit positions are obtained by adding horizontally from left to right. The same is true for other directions by changing to addition and subtraction or by changing from calculating x to calculating y.

1) a-1<0.5

In this case, it ends directly after the first set of INVs and adds a termination line;

2) 0.5 <= a-1 < 1

In this case, add a buffer and end directly, adding a termination line;

The x coordinate of buffer BUF is x1+2*distance_x+distance_x, and the y coordinate is y1;

3) 1 <= a-1

In this case, the number of inverters INV added is determined through a loop;

The judgment condition of the loop is

for{set i 0}{i<($a-2)}{incr i}{…………}

That is, the initial value of i is set to 0. When i<a-2 is satisfied, i is increased by 1, that is, it changes from 0 to 1, and the command in the curly brackets is executed. After execution, it is re-determined whether i is less than a-2. If it is still satisfied, it continues to increase by 1, that is, it changes from 1 to 2, until it is judged that it is not satisfied;

The commands executed within the curly braces include:

1) Set variable num=i+1;

2) Set last_cell: [expr$trunk_num]_INV1_[expr$i]_$tar;

3) Set postfix[expr$i+1]_$tar;

That is, the name of the first INV added in pair is: [expr$trunk_num]_INV0_postfix, and the name of the second INV is [expr$trunk_num]_INV1_postfix. It is found that the last_cell set above is the INV with the last connection relationship among the three standard cells added at the beginning; the connection relationship between the INV added in the loop and the previously added INV can be realized; and the x coordinate of the first INV is $x1+(2*($num+1)-1)*$distance_x, and the y coordinate is y1; the x coordinate of the second INV is $x1+2*($num+1)*$distance_x, and the y coordinate is y1;

Whether BUF needs to be added at the end depends on two situations:

I)a-b<0.5

In this case, end directly after the loop and add a termination line;

II) 0.5 <= a-b

In this case, add a buffer and end directly, adding a termination line;

The x coordinate of the buffer BUF is the x coordinate of the last INV in the loop plus distance_x, and the y coordinate is y1; the naming suggestion of the added buffer BUF is the same as the buffer added in case 2); the name of the end line set under all conditions is the same, so that it can be used as the initial line when the second line segment is needed;

(3) Set the connection method between line segments:

Each line segment is executed using the single-segment logic of (1) and (2) above. Except for the different lines connected at the beginning, the rest are the same. Therefore, the end line of the first segment is set as the start line of the second segment to achieve the connection between the line segments, thereby realizing the turning of the optimized path; the second, third, and so on.

When a line segment is less than twice the spacing, there are two solutions:

The first method: do not add the line segment, but manually add a BUF and a net, and connect the manually added BUF and net to the previous and next line segments of the line segment;

The second method: directly connect the previous line segment and the next line segment of the line segment, ignore the line segment, and ensure that the current line segment is horizontal or vertical.

In the above-mentioned automated script writing and using method for solving the timing delay of long lines in physical design, in step S2, the main script conducts experiments by setting a single variable for the types of BUF and INV selected, the specific sizes of the horizontal and vertical spacings, and the properties of the connection, and selects the best solution;

All global variables required by the commands in the logic connection script include the line name begin_net that needs to be optimized; the standard cell tar_cell at the output end of the optimized line logic connection; the port name tar_term at which the output end standard cell is connected to the line; the set horizontal spacing distance_x; the set vertical spacing distance_y; the set buffer type BUF_cell; the set inverter type INV_cell; all are set as variables and moved to the main script for setting together, so as to achieve unified modification of these variables, ensuring that they will not be missed, and solidifying the logic connection script so that it will not be modified again, avoiding the modification causing the logic connection script to be unable to execute.

In the above-mentioned automated script writing and using method for solving long-line timing delay in physical design, in step S2, the logic connection script is calculated in line segment mode, so the main script is also divided into line segments to call the logic connection script multiple times, and the starting and ending points of the line segments are set as follows: the x coordinate of the starting point of the line segment is x1; the y coordinate of the starting point of the line segment is y1; the x coordinate of the end point of the line segment is x2; the y coordinate of the end point of the line segment is y2.

In the above-mentioned automated script writing and using method for solving long-line timing delay in physical design, in step S2, in order to better reduce line delay, the winding attributes are adjusted in the back-end physical design, and therefore the winding attributes are also set in the main script, and the winding attributes are: NDR is a parameter setting for multiple line widths and multiple spacings; NDR rule execution strength is set NDR_effort; the highest winding layer is set to top_route_layer; the lowest winding layer is set to bottom_route_layer; pre_layer_effort is the strength to meet the highest and lowest winding layer settings when the tool automatically winds; and weight parameter net_weight.

In the above-mentioned automated script writing and using method for solving long-line timing delay in physical design, in step S3, timing optimization is performed according to the layout plan before layout and routing, that is, in the floorplan stage, to replace the automatic optimization of subsequent tools and achieve the best timing optimization.

In the above-mentioned automated script writing and using method for solving long-line timing delay in physical design, in step S5, the added standard cells are named with the relevant information of the optimized timing violation path, which is unique and will not cause script failure due to repeated naming.

The beneficial effects of the present invention are:

1. The present invention is specifically applied to the layout and wiring stage of chip digital physical design to solve the impact of increasing line delay under advanced technology, and to minimize line delay for long paths on the physical level. The script of the present invention is divided into two layers: one layer is the main script, which sets global variables about the optimization object, such as line name, line width, unit type, etc.; the other layer is the logic connection script, which realizes the addition and positioning of standard units and the connection of standard units to ensure logical consistency, and no modification is required during use.

2. The script of the present invention can specifically achieve the effect of reducing line delay by setting the spacing between the buffer Buffer and the inverter Inverter, the line width of the wiring, the line spacing of the same-layer line, and the unit type of the buffer inverter. Because it is in the form of a script, and the variables required to be set in the script are pre-set as global environment variables, when modifying the relevant variables of the script, only a few changes need to be made. Therefore, in the process of finding the optimal solution, the relevant variables can be adjusted by the control variable method to achieve rapid iteration. And in the later specific layout and wiring stage, because the variables are clear and unambiguous, and because there may be multiple uses of different variables, the fixed script can be combined with the relevant commands of the layout and wiring tools, such as INNOVUS's dbget, etc., and the loop statement in the TCL syntax, to achieve the fixation of the back-end layout and wiring process, so that subsequent iterations are faster and less prone to errors.

3. The present invention can also be used to customize the key clock tree, manually make the clock tree, reduce the delay on the clock path, and easily meet the establishment time requirements. Or balance multiple modules or storage bodies that need to be balanced, including address, data, and clock balance, so as to meet the read and write requirements.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart of the present invention.

DETAILED DESCRIPTION

The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

As shown in FIG1 , an automated script writing and using method for solving long-line timing delay in physical design includes the following steps:

Step S1: Set up a logic connection script, and for the timing violation path, determine the addition location and connection of the buffer BUF standard unit and the addition location and connection of the inverter INV standard unit by setting the starting point, end point, and inflection point to ensure logic consistency.

The optimization logic of the logic connection script for the line path that needs to be optimized is to find the coordinates of the starting point and the end point of this line, and calculate according to the coordinate values; first determine the routing direction of up, down, left, and right, and then calculate the path length according to the coordinates of the starting point and the end point, and insert the standard unit of the optimized timing in combination with the set spacing; therefore, first set the coordinates of the starting point and the end point of the timing violation path; the variables set are as follows: the x coordinate of the path starting point x_begin, the y coordinate of the path starting point y_begin, the x coordinate of the path end point x_end, and the y coordinate of the path end point y_end;

In order to adapt to the specific situation of FloorPlan, set the inflection point in the middle. If branching is required, it can also be achieved through the inflection point. It should be noted that because it is an inflection point, the starting and ending points of the line between every two points must be horizontal and vertical. The inflection point variables are set to: inflection point x coordinate x_trunk*, inflection point y coordinate y_trunk*; the above * is an arbitrary serial number, which is used to distinguish different variables when multiple inflection points are used.

In the back-end physical design, if the starting and ending coordinates of the timing violation path are fixed after floorplanning, then the specific values are set directly. If they cannot be determined, the corresponding coordinates are found through dbget to provide a feasible solution for the customized path.

The process of determining the addition location and connection of the buffer BUF standard cell and the addition location and connection of the inverter INV standard cell is as follows:

(1) Calculate the number of inverters that need to be inserted based on the length of the line segment:

First, the coordinates of the starting point and the end point are used to determine the four directions of up, down, left, and right. Then, the inverter pair number a is calculated based on the distance and the set spacing. Inverters must be added in pairs to ensure logical consistency. However, it cannot be guaranteed that the path length will not exceed the specified length after the inverters are inserted in pairs at a fixed spacing. Therefore, a is rounded and set to b(int(a)). The number of INV pairs to be inserted subsequently is b. b is determined. If (a-b) is greater than the specified length, a buffer BUF is inserted. If (a-b) is less than the specified length, no buffer is inserted.

(2) Set loop logic:

The logic of the loop is that when the loop condition is met, a set of inverters INV and their connecting lines net are added, the inverter INV corresponding to the current variable is connected to the inverter of the previous variable, and the coordinate position of the pair of inverters is calculated according to the variables. The position is calculated by accumulating the required distance of the corresponding number on the starting coordinates, so a set of inverters INV and their connecting lines net are added in advance outside the loop;

Considering the effect of reducing the conversion time on the delay, a buffer BUF is added at the starting position, and then the first pair of inverters INV is added; the starting position is set to the edge of the starting unit; after the buffer BUF and the first pair of inverters INV are connected to the starting unit, the output end of the last unit, that is, the second inverter, is not connected and is connected in the subsequent judgment;

The coordinates of the buffer BUF are calculated, when added horizontally and from left to right:

The x coordinate of the first BUF is x1, and the y coordinate is y1;

The x coordinate of the first INV is x1+distance_x, and the y coordinate is y1;

The x coordinate of the second INV is x1+2*distance_x, and the y coordinate is y1;

distance_x is the set horizontal distance; the same applies to other directions;

And set a special character target abbreviation tar to name the added standard unit and line, using the character composed of the endpoint standard unit name and its port name;

Because the added standard cells and lines need unique names, this ensures that there will be no duplicate names that will cause the script to fail to execute;

The naming is as follows:

First BUF name: [expr$trunk_num]_BUF_0_$tar

First INV name: [expr$trunk_num]_INV0_0_$tar

Second INV name: [expr$trunk_num]_INV1_0_$tar

trunk_num refers to the line segment number, INV0_0 refers to the 0th INV of the 0th pair of INVs, and INV1_0 refers to the first INV of the 0th pair of INVs;

After adding a group of inverters INV, there are three cases for judgment. In these three cases, the termination lines are set to the same name to ensure consistency and facilitate subsequent execution.

All the calculations for the following unit positions are obtained by adding horizontally from left to right. The same is true for other directions by changing to addition and subtraction or by changing from calculating x to calculating y.

1) a-1<0.5

In this case, it ends directly after the first set of INVs and adds a termination line;

2) 0.5 <= a-1 < 1

In this case, add a buffer and end directly, adding a termination line;

The x coordinate of buffer BUF is x1+2*distance_x+distance_x, and the y coordinate is y1;

3) 1 <= a-1

In this case, the number of inverters INV added is determined through a loop;

The judgment condition of the loop is

for{set i 0}{i<($a-2)}{incr i}{…………}

That is, the initial value of i is set to 0. When i<a-2 is satisfied, i is increased by 1, that is, it changes from 0 to 1, and the command in the curly brackets is executed. After execution, it is re-determined whether i is less than a-2. If it is still satisfied, it continues to increase by 1, that is, it changes from 1 to 2, until it is judged that it is not satisfied;

The commands executed within the curly braces include:

1) Set variable num=i+1;

2) Set last_cell: [expr$trunk_num]_INV1_[expr$i]_$tar;

3) Set postfix[expr$i+1]_$tar;

That is, the name of the first INV added in pair is: [expr$trunk_num]_INV0_postfix, and the name of the second INV is [expr$trunk_num]_INV1_postfix. It is found that the last_cell set above is the INV with the last connection relationship among the three standard cells added at the beginning; the connection relationship between the INV added in the loop and the previously added INV can be realized; and the x coordinate of the first INV is $x1+(2*($num+1)-1)*$distance_x, and the y coordinate is y1; the x coordinate of the second INV is $x1+2*($num+1)*$distance_x, and the y coordinate is y1;

Whether BUF needs to be added at the end depends on two situations:

I)a-b<0.5

In this case, end directly after the loop and add a termination line;

II) 0.5 <= a-b

In this case, add a buffer and end directly, adding a termination line;

The x coordinate of the buffer BUF is the x coordinate of the last INV in the loop plus distance_x, and the y coordinate is y1; the naming suggestion of the added buffer BUF is consistent with the buffer added in case 2); the name of the end line set under all conditions is consistent, so that it can be used as the initial line when the second line segment is needed.

(3) Set the connection method between line segments:

Each line segment is executed using the single-segment logic of (1) and (2) above. Except for the different lines connected at the beginning, the rest are the same. Therefore, the end line of the first segment is set as the start line of the second segment to achieve the connection between the line segments, thereby realizing the turning of the optimized path; the second, third, and so on.

When a line segment is less than twice the spacing, there are two solutions:

The first method: do not add the line segment, but manually add a BUF and a net, and connect the manually added BUF and net to the previous and next line segments of the line segment;

The second method: directly connect the previous line segment and the next line segment of the line segment, ignore the line segment, and ensure that the current line segment is horizontal or vertical.

Step S2: Set up the main script and set the global variables of the timing violation path.

The main script tests the selected BUF and INV types, the specific sizes of the horizontal and vertical spacing, and the properties of the connection by setting a single variable to select the best solution;

For the TCL script environment, a brief explanation is given. Pre-set the value of a specific string, such as set a1, and then use $a to directly read the value 1. The advantage of this method is that when modifying, you only need to modify the value of the initial set. No matter how many times a is used in the script, this modification will make corresponding changes to all subsequent a, without having to modify them one by one;

All global variables required by commands in the logic connection script, such as the line name begin_net that needs to be optimized, the standard cell tar_cell at the output end of the optimization line logic connection, the port name tar_term that the output end standard cell connects to the line, the set horizontal spacing distance_x, the set vertical spacing distance_y, the set buffer type BUF_cell, and the set inverter type INV_cell, are all set as variables to move them to the main script and set them together, so as to achieve unified modification of these variables, ensure that they will not be missed, and solidify the logic connection script so that it will not be modified again, avoiding the modification causing the logic connection script to fail to execute. For example, to set the horizontal spacing distance_x, set set distance_x200 in the main script, and in all places in the logic connection script where this specific horizontal spacing 200 is needed, the value $distance_x can be called to replace the specific value 200.

The logical connection script is calculated in line segment mode, so the main script is also divided into line segments to call the logical connection script multiple times. The starting and ending points of the line segments are set as follows: the x coordinate of the starting point of the line segment is x1; the y coordinate of the starting point of the line segment is y1; the x coordinate of the end point of the line segment is x2; the y coordinate of the end point of the line segment is y2.

In order to better reduce line delay, the routing attributes are adjusted in the back-end physical design, so the routing attributes are also set in the main script, and the logic of use is also very simple. The layout and routing tool referenced by the example is INNOVUS, in which the command for setting the line attributes is setNetattribute, so the routing attributes are: NDR is set for parameters related to multiple line widths and multiple spacings; NDR rule execution strength is set to NDR_effort; the highest routing layer is set to top_route_layer; the lowest routing layer is set to bottom_route_layer; the strength pre_layer_effort that meets the highest and lowest routing layer settings when the tool automatically routes; and the weight parameter net_weight.

Step S3: Find the timing violation path to be optimized in the floorplan stage.

Before layout and routing, that is, in the floorplan stage, timing optimization is performed according to the layout plan, replacing the automatic optimization of subsequent tools to achieve the best timing optimization.

Step S4: according to the information of the timing violation path to be optimized and the layout plan of the design, set the parameters of the starting point, end point and inflection point, set the line name of the timing violation path to be optimized and the name of the connected end point standard cell port.

Step S5: Based on the logic connection script and the main script, according to different design processes, the standard unit types of the buffer BUF and the inverter INV are changed, the settings of the horizontal and vertical distances between the inserted buffer BUF and the inverter INV are changed, and the required parameters are selected.

The added standard cells are named with the relevant information of the optimized timing violation path, which is unique and will not cause the script to fail due to repeated naming.

Step S6: Before layout and routing, complete optimization in the layout and routing PR tool.

The present invention can also be further applied, for example:

1. The coordinates of the starting point and the end point can be obtained through the dbget command, such as [dbget[dbgettop.insts.name cell1–p1].pt_x] to obtain the x coordinate of the cell named cell1, and the y coordinate is pt_y instead of pt_x. In this way, the key logic unit can be located without manually determining the coordinates, thus reducing the manual workload. Furthermore, the name of the net to which it is connected can be obtained through the Pin of the IP or the Port of the IO, and the coordinates of another connected unit of the net can be found. There are many ways to obtain coordinates, which can also achieve smarter results.

2. Wrap a layer of related scripts outside this script to obtain the coordinates of the starting point and the end point, the starting line (begin_net), and the target cell and term. You can use dbget to obtain the key cells of the path that needs to be optimized.

3. You can increase the number of the second segment to achieve path branching while ensuring the connection relationship. Specific settings are required for specific problems. It can be applied to clock trees or bus branches, etc.

The present invention can also be used to customize key clock trees, manually build clock trees, reduce delays on clock paths, and easily meet setup time requirements; or balance multiple modules or storage bodies that need to be balanced, including address, data, and clock balance, so as to meet read and write requirements.

Claims (9)

1. An automated script writing and using method for solving long-line timing delay in physical design, characterized in that it includes the following steps: Step S1: Setting a logic connection script, for the timing violation path, by setting the starting point, the end point, and the turning point, determining the adding location and connection of the buffer BUF standard unit, and the adding location and connection of the inverter INV standard unit, to ensure logic consistency; Step S2: Setting the main script and setting the global variables of the timing violation path; Step S3: Find the timing violation path to be optimized in the floorplan stage; Step S4: according to the information of the timing violation path to be optimized and the layout plan of the design, set the parameters of the starting point, the end point, and the inflection point, and set the line name of the timing violation path to be optimized and the name of the connected end point standard cell port; Step S5: Based on the logic connection script and the main script, according to different design processes, the standard unit types of the buffer BUF and the inverter INV are changed, the horizontal and vertical spacings between the inserted buffer BUF and the inverter INV are changed, and the required parameters are selected; Step S6: Before layout and routing, complete optimization in the layout and routing PR tool. 2. According to the method for writing and using an automated script to solve the long-line timing delay of physical design as described in claim 1, it is characterized in that in step S1, the optimization logic of the logic connection script for the line path to be optimized is to find the coordinates of the starting point and the end point of the line, and calculate according to the coordinate values; give priority to judging the routing direction of up, down, left, and right, and then calculate the path length according to the coordinates of the starting point and the end point, and insert the standard unit of the optimized timing in combination with the set spacing; therefore, first set the coordinates of the starting point and the end point of the timing violation path; set the variables as follows: the x coordinate of the path starting point x_begin, the y coordinate of the path starting point y_begin, the x coordinate of the path end point x_end, and the y coordinate of the path end point y_end; In order to adapt to the specific situation of FloorPlan, set the inflection point in the middle. If branching is required, it can also be achieved through the inflection point. It should be noted that because it is an inflection point, the starting and ending points of the line between every two points must be horizontal and vertical. The inflection point variables are set to: inflection point x coordinate x_trunk*, inflection point y coordinate y_trunk*; the above * is an arbitrary serial number, which is used to distinguish different variables when multiple inflection points are used. 3. According to claim 2, the method for writing and using an automated script to solve long-line timing delays in physical design is characterized in that in step S1, in the back-end physical design, if the starting point and end point coordinates of the timing violation path are fixed after floorplanning, then the specific values are set directly. If they cannot be determined, the corresponding coordinates are found through dbget to provide a feasible solution for the customized path. 4. The method for writing and using an automated script to solve the long-line timing delay in physical design according to claim 2, characterized in that in step S1, the process of determining the addition location and connection of the buffer BUF standard unit and the addition location and connection of the inverter INV standard unit is: (1) Calculate the number of inverters that need to be inserted based on the length of the line segment: First, the coordinates of the starting point and the end point are used to determine the four directions of up, down, left, and right. Then, the inverter pair number a is calculated based on the distance and the set spacing. Inverters must be added in pairs to ensure logical consistency. However, it cannot be guaranteed that the path length will not exceed the specified length after the inverters are inserted in pairs at a fixed spacing. Therefore, a is rounded and set to b(int(a)). The number of INV pairs to be inserted subsequently is b. b is determined. If (a-b) is greater than the specified length, a buffer BUF is inserted. If (a-b) is less than the specified length, no buffer is inserted. (2) Set loop logic: The logic of the loop is that when the loop condition is met, a set of inverters INV and their connecting lines net are added, the inverter INV corresponding to the current variable is connected to the inverter of the previous variable, and the coordinate position of the pair of inverters is calculated according to the variables. The position is calculated by accumulating the required distance of the corresponding number on the starting coordinates, so a set of inverters INV and their connecting lines net are added in advance outside the loop; Considering the effect of reducing the conversion time on the delay, a buffer BUF is added at the starting position, and then the first pair of inverters INV is added; the starting position is set to the edge of the starting unit; after the three standard units of the buffer BUF and the first pair of inverters INV are connected to the starting unit, the output end of the last standard unit, that is, the second inverter, is not connected, and is connected in the subsequent judgment; The coordinates of the buffer BUF are calculated, when added horizontally and from left to right: The x coordinate of the first BUF is x1, and the y coordinate is y1; The x coordinate of the first INV is x1+distance_x, and the y coordinate is y1; The x coordinate of the second INV is x1+2*distance_x, and the y coordinate is y1; distance_x is the set horizontal distance; the same applies to other directions; And set a special character target abbreviation tar to name the added standard unit and line, using the character composed of the endpoint standard unit name and its port name; Because the added standard cells and lines need unique names, this ensures that there will be no duplicate names that will cause the script to fail to execute; The naming is as follows: First BUF name: [expr$trunk_num]_BUF_0_$tar First INV name: [expr$trunk_num]_INV0_0_$tar Second INV name: [expr$trunk_num]_INV1_0_$tar trunk_num refers to the line segment number, INV0_0 refers to the 0th INV of the 0th pair of INVs, and INV1_0 refers to the first INV of the 0th pair of INVs; After adding a set of inverters INV, there are three cases to be judged. In these three cases, the termination lines are set to the same name to ensure consistency and facilitate subsequent execution; All the calculations for the following unit positions are obtained by adding horizontally from left to right. The same is true for other directions by changing to addition and subtraction or by changing from calculating x to calculating y. 1) a-1<0.5 In this case, it ends directly after the first set of INVs and adds a termination line; 2) 0.5 <= a-1 < 1 In this case, add a buffer and end directly, adding a termination line; The x coordinate of buffer BUF is x1+2*distance_x+distance_x, and the y coordinate is y1; 3) 1 <= a-1 In this case, the number of inverters INV added is determined through a loop; The judgment condition of the loop is for{set i 0}{i<($a-2)}{incr i}{…………} That is, the initial value of i is set to 0. When i<a-2 is satisfied, i is increased by 1, that is, it changes from 0 to 1, and the command in the curly brackets is executed. After execution, it is re-determined whether i is less than a-2. If it is still satisfied, it continues to increase by 1, that is, it changes from 1 to 2, until it is judged that it is not satisfied; The commands executed within the curly braces include: 1) Set variable num=i+1; 2) Set last_cell: [expr$trunk_num]_INV1_[expr$i]_$tar; 3) Set postfix[expr$i+1]_$tar; That is, the name of the first INV added in pair is: [expr$trunk_num]_INV0_postfix, and the name of the second INV is [expr$trunk_num]_INV1_postfix. It is found that the last_cell set above is the INV with the last connection relationship among the three standard cells added at the beginning; the connection relationship between the INV added in the loop and the previously added INV can be realized; and the x coordinate of the first INV is $x1+(2*($num+1)-1)*$distance_x, and the y coordinate is y1; the x coordinate of the second INV is $x1+2*($num+1)*$distance_x, and the y coordinate is y1; Whether BUF needs to be added at the end depends on two situations: I)a-b<0.5 In this case, end directly after the loop and add a termination line; II) 0.5 <= a-b In this case, add a buffer and end directly, adding a termination line; The x coordinate of the buffer BUF is the x coordinate of the last INV in the loop plus distance_x, and the y coordinate is y1; the naming suggestion of the added buffer BUF is the same as the buffer added in case 2); the name of the end line set under all conditions is the same, so that it can be used as the initial line when the second line segment is needed; (3) Set the connection method between line segments: Each line segment is executed using the single-segment logic of (1) and (2) above. Except for the different lines connected at the beginning, the rest are the same. Therefore, the end line of the first segment is set as the start line of the second segment to achieve the connection between the line segments, thereby realizing the turning of the optimized path; the second, third, and so on. When a line segment is less than twice the spacing, there are two solutions: The first method: do not add the line segment, but manually add a BUF and a net, and connect the manually added BUF and net to the previous and next line segments of the line segment; The second method: directly connect the previous line segment and the next line segment of the line segment, ignore the line segment, and ensure that the current line segment is horizontal or vertical. 5. The method for writing and using an automated script to solve the long-line timing delay in physical design according to claim 4 is characterized in that, in step S2, the main script conducts experiments by setting a single variable for the types of BUF and INV selected, the specific sizes of the horizontal and vertical spacing, and the properties of the connection, and selects the optimal solution; All global variables required by the commands in the logic connection script include the line name begin_net that needs to be optimized; the standard cell tar_cell at the output end of the optimized line logic connection; the port name tar_term at which the output end standard cell is connected to the line; the set horizontal spacing distance_x; the set vertical spacing distance_y; the set buffer type BUF_cell; the set inverter type INV_cell; all are set as variables and moved to the main script for setting together, so as to achieve unified modification of these variables, ensuring that they will not be missed, and solidifying the logic connection script so that it will not be modified again, avoiding the modification causing the logic connection script to be unable to execute. 6. According to the method for writing and using an automated script to solve long-line timing delays in physical design as described in claim 5, it is characterized in that in step S2, the logic connection script is calculated in a line segment mode, so the main script is also divided into line segments to call the logic connection script multiple times, and the starting and ending points of the line segments are set as follows: the x coordinate of the starting point of the line segment is x1; the y coordinate of the starting point of the line segment is y1; the x coordinate of the end point of the line segment is x2; the y coordinate of the end point of the line segment is y2. 7. According to the method for writing and using an automated script to solve long-line timing delays in physical design as described in claim 5, it is characterized in that, in step S2, in order to better reduce line delays, the winding attributes are adjusted in the back-end physical design, and therefore the winding attributes are also set in the main script, and the winding attributes are: the parameter setting NDR for multiple line widths and multiple spacings; the NDR rule execution strength setting NDR_effort; the highest winding layer setting top_route_layer; the lowest winding layer setting bottom_route_layer; the strength pre_layer_effort that meets the highest and lowest winding layer settings when the tool automatically winds; and the weight parameter net_weight. 8. The method for writing and using an automated script to solve long-line timing delays in physical design according to claim 7 is characterized in that, in step S3, timing optimization is performed according to the layout plan before layout and routing, i.e., in the floorplan stage, to replace the automatic optimization of subsequent tools, thereby achieving optimal timing optimization. 9. The method for writing and using an automated script to solve long-line timing delays in physical design according to claim 7 is characterized in that, in step S5, the added standard cells are named with the relevant information of the optimized timing violation path, which is unique and will not result in script failure due to repeated naming.