CN113743044B - Timing path correction method, device, medium and chip structure - Google Patents
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Abstract
The embodiment of the invention provides a time sequence path correction method, a time sequence path correction device, a time sequence path correction medium and a chip structure, and belongs to the technical field of chips. The time sequence path correction method comprises the following steps: aiming at the customization module blocking the time sequence path, judging whether the customization module meets the expansion requirement of the wiring channel; and modifying the physical information of the custom module to extend a routing channel within the custom module such that a corresponding timing path traverses the custom module via the routing channel, if it is determined that the custom module meets the routing channel extension requirement. The invention leads the time sequence path to penetrate through the customized module by establishing the wiring channel, effectively shortens the length of the time sequence path, reduces the time sequence violation caused by the parasitic phenomenon and is beneficial to realizing the low-power consumption mixed signal design.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a time sequence path correction method, a time sequence path correction device, a time sequence path correction medium and a chip structure.
Background
With the integration of chip design becoming higher and higher, more designs adopt a top-down design method, which divides the chip into different sub-modules, so that the original one timing path is distributed in different sub-modules. When the space span of the two sub-modules in the chip is large, a wiring channel penetrating through signals needs to be defined, so that the requirements of time sequence and wiring are met; when the signal penetrates through the submodules with different power supply attributes, extra power supply wiring resources are also needed to be considered for supplying power to the driving unit; when the trace distance through the signal is too long, timing violation issues also need to be considered, i.e., in this case, the generated parasitic parameters exceed the noise margin of the signal frequency, so that timing violations occur on the signal path.
In order to meet the requirements of the wiring and the time sequence, a plurality of difficulties exist in the physical design of the chip aiming at the mixed signal. Mixed signal physical designs typically include many custom modules, and when a large number of custom modules are run through a signal span, a back-end design tool typically bypasses the module edges to route wires due to the presence of a routing barrier layer on the custom modules, and adds a certain number of drive units to correct timing violations due to too long wires. However, in the low power consumption design, the introduction of more driving units is liable to be unfavorable for the optimization of the chip power consumption.
Disclosure of Invention
An object of the embodiments of the present invention is to provide a timing path correction method, apparatus, medium and chip structure, which are used to at least partially solve the above technical problems.
In order to achieve the above object, an embodiment of the present invention provides a timing path correction method, including: aiming at the customization module blocking the time sequence path, judging whether the customization module meets the expansion requirement of the wiring channel; and modifying the physical information of the custom module to extend a routing channel within the custom module such that a corresponding timing path traverses the custom module via the routing channel, if it is determined that the custom module meets the routing channel extension requirement.
Optionally, before the determining whether the customized module meets the requirement for expanding the routing channel, the method for correcting the timing path further includes: judging whether a time sequence violation exists at present; if the time sequence violation is determined to exist, judging whether a time sequence path corresponding to the time sequence violation is blocked by the customizing module or not; and if the time sequence path is determined to be blocked by the customizing module, executing the step of judging whether the customizing module meets the expansion requirement of the wiring channel.
Optionally, after the determining whether the timing path corresponding to the timing violation is blocked by the customization module, the timing path correction method further includes: if the timing path is determined not to be blocked by the custom module, adding a driving unit to the chip component module or enlarging the size of the chip component module to correct the timing violation for the chip component module causing the timing violation.
Optionally, the determining whether the timing path corresponding to the timing violation is blocked by the customization module includes: when the chip design enters a back-end automatic layout wiring process, executing a back-end trial run process under the condition that the layout of all chip composition modules is determined so as to generate a time sequence report; and determining a timing violation based on the timing report.
Optionally, the routing channel expansion requirement comprises: requirements regarding space and routing resources inside the custom module; and performance requirements with respect to the customized module with increased interference parameters.
Optionally, the determining whether the customized module meets the routing channel extension requirement includes: detecting physical information of the customized module to determine whether enough space and wiring resources exist in the customized module to expand a wiring channel; and performing post-simulation on the customized module under the condition of adding interference parameters to judge whether the performance of the customized module is influenced by the expansion of a wiring channel in the customized module, wherein the interference parameters are associated with the wiring channel.
Optionally, the modifying the physical information of the customization module includes: modifying physical layer blocking information in a library exchange file of the custom module according to the available space of the custom module and the actual size of the wiring resource; updating the initial design data based on the modified library exchange file; re-partitioning the barrier layer region of the custom module based on the updated design data to obtain at least one routing channel; and rerouting the line by using the routing channel so that the corresponding timing path passes through the custom module through the routing channel.
Optionally, the repartitioning of the barrier region of the custom module comprises: the size and number of barrier regions is determined.
Optionally, after the causing the corresponding timing path to penetrate through the customized module via the routing channel, the timing path correction method further includes: and executing a back-end automatic layout and wiring flow to generate a corresponding timing report, and determining a timing violation correction condition based on the timing report.
Embodiments of the present invention also provide a machine-readable storage medium, where the machine-readable storage medium has instructions stored thereon, where the instructions are used to enable a machine to execute any of the above timing path correction methods.
The embodiment of the invention also provides a chip structure which comprises a plurality of component modules, wherein at least one of the component modules is a customized module, and the internal extension of the customized module is provided with a wiring channel, so that a timing path blocked by the customized module can penetrate through the customized module through the wiring channel.
The embodiment of the invention also provides a timing path correction device for a chip structure, wherein the chip structure comprises at least one customized module, the timing path correction device comprises a memory and a processor, the memory is stored with a program, and the processor is used for running the program to execute any timing path correction method.
Through the technical scheme, the time sequence path is guided to penetrate through the customized module by establishing the wiring channel on the customized module which is penetrated through the time sequence path and is to be crossed, so that the internal space of the customized module can be fully utilized, the length of the time sequence path is effectively shortened, the parasitic influence is reduced, the time sequence violation caused by the parasitic phenomenon is reduced, the number of the inserted driving units is reduced, favorable conditions are provided for optimizing the area and the power consumption of a chip, and the low-power consumption mixed signal design is facilitated.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
FIG. 1 is a flow chart illustrating a timing path correction method according to an embodiment of the invention;
FIG. 2 is a schematic flow chart illustrating the preferred embodiment of determining whether a custom module meets the requirement of routing channel expansion;
FIG. 3 is a schematic flow diagram of the modification of the physical information of the custom module to extend the routing channel in the preferred embodiment;
FIG. 4 is a flow chart illustrating timing path modification in an exemplary application of a method according to an embodiment of the invention;
fig. 5(a) and 5(b) are layout diagrams respectively showing before and after the corresponding time-series path correction method is implemented in the application example of fig. 4.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Some terms appearing in the embodiments of the present invention will be described below:
1. mixed signal design: refers to circuit designs involving both digital and analog signals, where custom modules are often considered.
2. A customization module: also known as a custom IP core, is a portable electronic unit with specific functionality.
3. A time sequence path: refers to the logic path traversed by the data signal during propagation in the design.
4. The back end automatic layout and wiring process: the method is to complete the chip layout drawing process through automatic layout and automatic wiring, and tools for realizing automatic layout and wiring, such as ICC2 of Synopsys, Innovus of Cadence and the like, are used. For convenience of description, the PR Flow is also described in the following and in the drawings of the present application as a backend automatic place-and-route Flow.
5. Back-end run-on flow: also denoted as try run flow, refers to performing a test run on the chip after the back-end layout scheme of the chip is completed to obtain an initial timing report.
6. And (3) timing report: also referred to as timing path reports or path timing reports, which indicate which constituent modules a chip is composed of and the timing relationships between the constituent modules.
7. Post simulation: refers to simulations performed taking into account the disturbance parameters.
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
Fig. 1 is a flowchart illustrating a timing path correction method according to an embodiment of the invention. As shown in fig. 1, the timing path correction method includes the following steps:
step S100, for the customized module blocking the timing path, determine whether the customized module meets the requirement of the routing channel expansion.
Step S200, under the condition that the customized module is determined to meet the wiring channel expansion requirement, modifying the physical information of the customized module to expand the wiring channel in the customized module, so that the corresponding timing sequence path penetrates through the customized module through the wiring channel.
Through step S100 and step S200, the embodiment of the present invention extends the wiring channel inside the custom module, so that the corresponding timing path passes through the custom module via the wiring channel, thereby changing the traditional wiring manner of bypassing the module edge and adding the driving unit.
Further, it is easy to know that the precondition for performing steps S100 and S200 is that there is a timing violation and the custom module complies with the routing channel extension requirement. Therefore, in a preferred embodiment, before performing step S100, the timing path correction method of the embodiment of the present invention may further include the following steps S10 and S20 (not shown in the figure):
step S10, determining whether there is a timing violation currently, and if yes, determining whether the timing path corresponding to the timing violation is blocked by the customization module.
In step S20, if it is determined that the timing path is blocked by the custom module, step S100 is performed.
More preferably, for step 10, the step S101 and step S102 (not shown in the figure) of determining whether the timing path corresponding to the timing violation is blocked by the customization module may include the following steps:
step S101, when the chip design enters the back-end automatic layout and wiring process, under the condition that the layout of all the chip composition modules is determined, the back-end test run process is executed to generate a time sequence report.
And step S102, determining a timing violation condition according to the timing report.
Wherein the timing violation comprises: whether a timing violation exists; and if the timing violation exists, whether the timing path corresponding to the timing violation is blocked by the customization module or not.
Here, by analyzing the timing relationship between the respective component blocks shown in the timing report, the cause of the occurrence of the timing violation can be acquired. This is conventional to those skilled in the art and will not be described in further detail herein.
It should be noted that, if it is determined that the timing violation exists currently, but a timing path corresponding to the timing violation is not blocked by the customized module but is blocked by another module, the timing violation problem is solved by using a conventional method for a chip component module causing the timing violation, that is: the driving unit is added or the size of the chip component block is enlarged to correct the timing violation.
Therefore, before step S100 is executed, it is required to determine whether there is a timing violation problem and whether the corresponding timing path is blocked by the custom module by using the timing report, and if there is no such problem, the back-end automatic layout and routing process may be continued. In the back-end automatic layout and wiring process, timing violations caused by other chip composition modules except the customized module can be automatically corrected by adding a driving unit or enlarging the size of the corresponding module.
Further, for step S100, wherein the routing channel expansion requirement may include: requirements regarding space and routing resources inside the custom module; and performance requirements with respect to the customized module with increased interference parameters. The interference parameter may be selected according to actual conditions, but in the embodiment of the present invention, the interference parameter is mainly set for the added wiring channel.
Based on the determined routing channel expansion requirement, FIG. 2 is a flow diagram illustrating a preferred embodiment for determining whether the custom module meets the routing channel expansion requirement. That is, as shown in fig. 2, the step of determining whether the customized module meets the routing channel expansion requirement in step S100 may include the following steps:
step S110, detecting physical information of the customized module to determine whether there is enough space and wiring resources inside the customized module to perform expansion of the wiring channel.
Wherein the physical information comprises complete layout data of the custom module showing space and routing resources in the custom module. In addition, the size of the routing channel can be determined according to the size of the standard cell, and is generally required to be used for placing and routing the standard cell. Here, the layout dimensions of the standard cells are determined by a library of standard cells of a corresponding back-end design tool.
Step S120, performing post-simulation on the customized module under the condition of adding the interference parameter to determine whether the performance of the customized module is affected by the expansion of the wiring channel inside the customized module.
In step S120, the interference parameter is associated with the routing channel, i.e. the increased interference parameter is the relevant interference parameter resulting from the addition of the routing channel.
For step S120, for example, the interference parameters are set for the wiring channel, and then the simulation environment of the custom module is entered, and the post-simulation for adding the interference parameters is performed on the interference parameters, and it is confirmed through the actual simulation result whether the function and performance of the module itself are substantially affected by placing the standard cell and the wiring in the custom module. If the influence is determined to be insufficient or slightly negligible to influence the performance of the module through post-simulation, the next design step can be carried out.
Further, with respect to the above step S200, fig. 3 is a schematic flow chart illustrating the modification of the physical information of the customization module in the preferred embodiment. As shown in fig. 3, the following steps may be included:
step S210, according to the available space of the customization module and the actual size of the wiring resource, modifying the physical layer blocking information in the library exchange file of the customization module.
The physical information comprises a library exchange file, the library exchange file records physical layer blocking information about the customization module, and the blocking layer area of the customization module can be changed by modifying the physical layer blocking information.
Step S220, updating the initial design data based on the modified library exchange file.
Step S230, based on the updated design data, repartitioning the barrier region of the customized module to obtain at least one routing channel.
Wherein the repartitioning of the barrier region of the custom module comprises: the size and number of barrier regions is determined. For example, the area of each barrier region to be subdivided is reduced and the corresponding number of regions is reduced so as to cooperate to produce a desired routing channel.
Step S240, rewiring is performed by using the wiring channel, so that the corresponding timing path passes through the custom module through the wiring channel.
That is, the rewiring enables timing paths that would otherwise be blocked by the custom module to pass through the custom module, thereby both ensuring that no timing violations occur and avoiding the need for excessive routing that bypasses the module.
In a preferred embodiment, after the steps S100 and S200 are performed, the following steps may be further included:
in step S300 (not shown), a back-end automatic layout and routing process is performed to generate a corresponding timing report, and a timing violation correction condition is determined based on the timing report.
For example, if it is determined that the timing violation has not been completely corrected, steps S100-S200 may be iterated to continue correcting the timing violation.
To sum up, the method according to the embodiment of the present invention guides the timing path to pass through the customized module by creating the wiring channel on the customized module to be crossed through the timing path, so as to fully utilize the internal space of the customized module, effectively shorten the length of the timing path, reduce the parasitic influence, and reduce the timing violation caused by the parasitic phenomenon, thereby simplifying the number of inserted driving units, providing favorable conditions for optimizing the chip area and power consumption, and contributing to the implementation of low-power consumption mixed signal design.
The application of the timing path correction method according to the embodiment of the present invention to chip design is specifically described below with reference to an application example. This application example is directed to a Micro Control Unit (MCU) project chip back end that implements the timing path correction method described above when the timing path is blocked by an analog-to-digital converter (ADC) custom module. Fig. 4 is a schematic flow chart of the application example for performing timing path correction. As shown in fig. 4, the following steps may be included:
step S401, checking the current timing report, and determining whether there is a custom module blocking the timing path and a timing violation occurs, if yes, performing step S401, otherwise, continuing the back-end automatic layout and routing Flow (PR Flow).
For example, after a chip design enters a back-end automatic layout and routing Flow (PR Flow), when the layouts of all modules (including custom modules) are determined, a timing report may be generated through a back-end run Flow (including arranging standard cells, performing clock tree analysis, and the like), and then the generated timing report may be read to check a specific timing problem. If the time sequence violation of the path exists at the moment and the path with the time sequence violation crosses the customization module, the next judgment can be carried out, otherwise, the normal back-end automatic layout and wiring process is continued to continue the subsequent back-end design. In a normal back-end automatic layout and routing process, if a timing violation is caused by a chip component module, the timing violation is corrected by adding a driving unit or enlarging the original unit size.
Step S402, checking the physical information of the customization module blocking the time sequence path, judging whether to excavate the wiring channel, if so, executing step S403, otherwise, continuing the rear-end automatic layout wiring process.
For example, the complete layout data of the custom module is checked to determine whether there is currently space for standard cell placement and routing within the custom module. If the available space and wiring resources are determined to exist at the moment, the next step of judgment can be carried out; if no available space and wiring resources exist, the back-end automatic layout and wiring process is continued, and the timing violation is corrected by adding a driving unit or enlarging the size of the original unit.
Step S403, performing post-simulation for adding interference parameters to the custom module, and determining whether the insertion of the timing path substantially affects the custom module, if so, searching for a channel space with the smallest influence, and if not, continuing to step S404.
For example, the simulation environment of the custom module is entered, post simulation of adding interference parameters is performed on the simulation environment, and whether the function and performance of the custom module are substantially affected by placing standard cells and wiring in the custom module is confirmed through an actual simulation result. If the influence is not enough to influence the performance of the module or is slightly negligible, the next design step can be carried out, and otherwise, the channel space with the smallest influence is searched to enter the next design step.
Step S404, the physical information of the customization module is modified.
For example, after all the foregoing pre-determination is completed, the modification of the physical information of the customization module is required, which may include: in the library exchange file of the custom module, the physical layer blocking information of the module is modified according to the available space and the actual size of the routing resources.
Step S405, updating the back-end design data based on the modified physical information.
For example, the modified library file may be imported into a back-end design tool (e.g., ICC2 from Synopsys) and the initial design data may be updated to repartition the routing barrier size and number of regions near the custom module during the placement phase.
Step S406, re-perform the back-end automatic layout and routing process, and check the timing report.
For example, by checking the timing report, it is determined whether the timing violation is actually corrected, and if not, the related steps can be repeated, or the correction can be performed by means of a back-end automatic layout/routing process.
Through the above steps S401 to S406, the application example completes the problem of correcting the timing violation caused by the adc module in the back end of the mcu item chip. Fig. 5(a) and 5(b) show layout diagrams before and after the corresponding time-series path correction method is implemented in this application example, respectively. As can be seen from the comparison between fig. 5(a) and fig. 5(b), by using the timing path correction method according to the embodiment of the present invention, fig. 5(b) guides the timing path to penetrate through the customized module, which effectively shortens the routing length of the penetrated signal and avoids the timing violation caused by too long routing compared with the conventional approach of routing around the module edge in fig. 5(a), thereby optimizing the routing resources and the chip area, and facilitating the implementation of the low-power consumption mixed signal design.
Another embodiment of the present invention further provides a machine-readable storage medium, which stores instructions for causing a machine to execute the timing path correction method described in the above embodiment.
Another embodiment of the present invention further provides a chip structure, which includes a plurality of constituent modules, and at least one of the constituent modules is a customized module. Also, referring to fig. 5(b), the internal extension of the custom module has a routing channel so that timing paths blocked by the custom module can traverse the custom module via the routing channel. For example, the chip structure may be a micro control unit having an analog-to-digital converter custom module as shown in fig. 5 (b). In addition, the chip structure is designed based on the timing path correction method described in the above embodiment.
Another embodiment of the present invention further provides a timing path modification apparatus for a chip structure, where the chip structure includes at least one customized module, and the timing path modification apparatus includes a memory and a processor, where the memory stores a program thereon, and the processor is configured to run the program to perform the timing path modification method according to the above embodiment.
The processor comprises a kernel, and the kernel calls a corresponding program unit from the memory. One or more cores can be set, and the timing path correction method described in the above embodiments is performed by adjusting the core parameters.
The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.
The embodiment of the invention provides a processor, which is used for running a program, wherein the program executes the timing path correction method according to any embodiment of the invention when running.
An embodiment of the present invention provides an electronic device, where the device includes a processor, a memory, and a program stored in the memory and capable of running on the processor, and when the processor executes the program, the processor implements the method for correcting a timing path according to any embodiment of the present invention. The electronic device herein may be a server, a PC, a PAD, a mobile phone, etc.
Embodiments of the present invention further provide a computer program product adapted to execute a program for initializing steps of a timing path correction method according to any of the embodiments of the present invention when executed on a data processing device.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The memory may include forms of volatile memory in a computer readable medium, Random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in the process, method, article, or apparatus that comprises the element.
The above are merely examples of the present application and are not intended to limit the present application. Various modifications and changes may occur to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.
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| US7926011B1 (en) * | 2007-01-10 | 2011-04-12 | Cadence Design Systems, Inc. | System and method of generating hierarchical block-level timing constraints from chip-level timing constraints |
| CN102467582B (en) * | 2010-10-29 | 2014-08-13 | 国际商业机器公司 | Method and system for optimizing wiring constraint in integrated circuit design |
| CN111611762A (en) * | 2020-05-26 | 2020-09-01 | 国微集团(深圳)有限公司 | Method, system and storage medium for optimizing integrated circuit with hierarchical structure |
| CN112651208A (en) * | 2020-12-30 | 2021-04-13 | 杭州加速科技有限公司 | Wiring congestion optimization method among modules in FPGA chip |
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