CN114546019B - Temperature coefficient adjustable reference voltage source - Google Patents

Abstract

The invention discloses a reference voltage source circuit with an adjustable temperature coefficient. The reference voltage source circuit comprises a first current generation circuit and a second voltage regulation circuit, wherein the first current generation circuit mainly comprises four NPN (negative-positive-negative) tubes, a PMOS (P-channel metal oxide semiconductor) tube, two resistors and two variable resistors; the second circuit of voltage regulating circuit mainly comprises two NPN tubes, five PMOS tubes, three resistors and a variable resistor. The invention has the characteristic of adjustable temperature coefficient, and can well meet the use requirements of different temperature coefficient bias voltages of various analog radio frequency circuits.

Description

A reference voltage source with adjustable temperature coefficient

technical field

The invention belongs to the technical field of reference voltage source circuit design, and relates to a reference voltage source with adjustable temperature coefficient for analog radio frequency circuits.

Background technique

Reference voltage source and reference current source are important components of analog RF circuits, providing bias for the entire circuit. The purpose of generating a reference is to obtain a DC voltage or current that is independent of temperature and power. The performance of many analog RF circuits is affected by the reference. For example, the bias current of the differential pair is generated by the reference, which affects key indicators such as noise and voltage gain of the differential pair; a stable reference is also required in the AD/DA system to determine The full range of its input or output.

For most analog RF circuits, the traditional benchmarks for determining temperature characteristics are usually selected from the following three forms: (1) benchmarks that are independent of temperature; (2) benchmarks where the Gm of some transistors remains constant, that is, benchmarks with constant Gm characteristics ; (3) The proportional to absolute temperature (PTAT) benchmark. The temperature characteristics of these three references are single, and the application range is limited. For example, in high-speed frequency divider circuits, the operating frequency is extremely sensitive to temperature and bias current. Over a wide frequency range, frequency dividers require more current to operate at high frequencies and high temperatures, so temperature-independent references cannot meet the usage requirements. If the PTAT reference is used, the lower the temperature, the smaller the current, which will cause the current to decrease too much at low temperature, and make the DC operating point of the frequency divider deviate from the normal operating area. Therefore, the traditional reference is difficult to meet the requirements of high-speed circuits, and the form is single and the versatility is poor.

Contents of the invention

The technical problem solved by the present invention is: to overcome the deficiencies of the prior art, to propose a reference voltage source with adjustable temperature coefficient, which can realize positive temperature coefficient, negative temperature coefficient and a reference that does not change with temperature, so as to meet the needs of different analog radio frequency circuits. Usage requirements. The circuit structure is simple and the versatility is strong.

Technical solution of the present invention is:

A reference voltage source with adjustable temperature coefficient, including a first current generation circuit and a second voltage regulation circuit;

The first current generation circuit includes NPN tube Q1, NPN tube Q2, NPN tube Q3, NPN tube Q4, PMOS tube M1, resistor R1, variable resistor R2, variable resistor R3, and resistor R4; the second voltage regulation circuit includes NPN tube Q5, NPN tube Q6, PMOS tube M2, PMOS tube M3, PMOS tube M4, PMOS tube M5, PMOS tube M6, resistor R5, resistor R6, variable resistor R7, variable resistor R8;

The base and collector of the NPN transistor Q1 are connected together with the base of the NPN transistor Q2, and at the same time connected to the power supply V _DD through the resistor R1, and the emitter of the NPN transistor Q1 is simultaneously connected to the collector of the NPN transistor Q3 and the terminal of the NPN transistor Q4 Base; the collector of the NPN transistor Q2 is connected to the drain of the PMOS transistor M1, the gate of the PMOS transistor M1, the gate of the PMOS transistor M2, and the drain of the PMOS transistor M3, and the emitter of the NPN transistor Q2 is simultaneously connected to the NPN The base of the tube Q3 and the collector of the NPN tube Q4 are connected to the ground GND through the variable resistor R3; the emitter of the NPN tube Q3 is connected to the ground GND; the emitter of the NPN tube Q4 is connected to the ground GND through the variable resistor R2 ; The source of the PMOS transistor M1 is connected to the power supply V _DD through the resistor R4;

The collector of the NPN transistor Q5 is simultaneously connected to the drain of the PMOS transistor M2, the drain of the PMOS transistor M5 and the gate of the PMOS transistor M6, the base of the NPN transistor Q5 is connected to the base of the NPN transistor Q6, and the collector of the NPN transistor Q6 The electrode and the drain of the PMOS transistor M6 are simultaneously used as the voltage output terminal V _BG of the entire circuit; the emitter of the NPN transistor Q5 is connected to the ground GND through the variable resistor R7; the emitter of the NPN transistor Q6 is connected to the ground through the variable resistor R8 GND; the source of the PMOS transistor M2 is connected to the power supply V _DD through the resistor R5; the gate of the PMOS transistor M3 is connected to the input terminal of the control signal S, and the source of the PMOS transistor M3 is connected to the drain of the PMOS transistor M4 and the PMOS transistor M5 The gate of the PMOS transistor M4 is connected to the input terminal of the control signal SN, the source of the PMOS transistor M4 is connected to the power supply V _DD ; the source of the PMOS transistor M5 is connected to the power supply V _DD through the resistor R6; the PMOS transistor M6’s The source is connected to the power supply V _DD .

Further, the unit NPN tube parameters of the NPN tube Q1, NPN tube Q2, NPN tube Q3, and NPN tube Q4 are exactly the same, and the number of unit NPN tubes connected in parallel between the NPN tube Q1 and the NPN tube Q4 is equal to that of the NPN tube Q2 and the NPN tube Q3. 8 times.

Further, the resistance values of the resistor R4, the resistor R5 and the resistor R6 are equal, and the parameters of the PMOS transistor M1, the PMOS transistor M2 and the PMOS transistor M5 are exactly the same.

Further, the resistance value of the variable resistor R8 needs to be changed together with the variable resistor R7 to keep the same resistance value, and the parameters of the NPN transistor Q5 and the NPN transistor Q6 are completely consistent.

Compared with the traditional design scheme, the reference voltage source with adjustable temperature coefficient of the present invention has the following advantages:

A reference voltage source with adjustable temperature coefficient is realized by using a special structure. By changing the variable resistance, a positive temperature coefficient, a negative temperature coefficient and a voltage reference that does not change with temperature can be obtained. It has strong versatility and can meet the requirements of most high-speed circuits on the reference voltage.

Through S and SN, it is convenient to switch between the two gears and expand the adjustable range of temperature coefficient. At the same time, according to the needs, multiple switchable branches can be connected in parallel to realize the adjustment of multiple gears.

The variable resistor can be realized in various ways such as combination of resistor string and switching MOS tube, and has a simple structure and is easy to control. The overall circuit area of the voltage source is small, and its special structure makes it highly scalable. While providing multi-mode optional stable voltage, it occupies a small chip area and reduces costs.

Description of drawings

FIG. 1 is a schematic diagram of a broadband monolithic integrated low noise amplifier circuit of the present invention. In the figure: 100: the first current generation circuit, 200: the second voltage regulation circuit.

Figure 2-Figure 4 shows the positive temperature coefficient, negative temperature coefficient and non-variant Schematic diagram of varying reference voltage simulation.

detailed description

The present invention will be described in detail below in conjunction with the accompanying drawings.

As shown in FIG. 1 , the bias reference voltage source with adjustable temperature coefficient proposed by the present invention includes two parts, a first current generation circuit 100 and a second voltage regulation circuit 200 , and the specific circuit structure and connection relationship are described as follows.

The first current generating circuit 100 includes NPN transistor Q1, NPN transistor Q2, NPN transistor Q3, NPN transistor Q4, PMOS transistor M1, resistor R1, variable resistor R2, variable resistor R3, and resistor R4. The base and collector of the NPN transistor Q1 are connected together with the base of the NPN transistor Q2, and at the same time connected to the power supply V _DD through the resistor R1, and the emitter of the NPN transistor Q1 is simultaneously connected to the collector of the NPN transistor Q3 and the terminal of the NPN transistor Q4 Base; the collector of the NPN transistor Q2 is connected to the drain of the PMOS transistor M1, the gate of the PMOS transistor M1, the gate of the PMOS transistor M2, and the drain of the PMOS transistor M3, and the emitter of the NPN transistor Q2 is simultaneously connected to the NPN The base of the tube Q3 and the collector of the NPN tube Q4 are connected to the ground GND through the variable resistor R3; the emitter of the NPN tube Q3 is connected to the ground GND; the emitter of the NPN tube Q4 is connected to the ground GND through the variable resistor R2 ; The source of the PMOS transistor M1 is connected to the power supply V _DD through the resistor R4 .

The second voltage regulation circuit 200 includes NPN transistor Q5, NPN transistor Q6, PMOS transistor M2, PMOS transistor M3, PMOS transistor M4, PMOS transistor M5, PMOS transistor M6, resistor R5, resistor R6, variable resistor R7, variable resistor R8. The collector of the NPN transistor Q5 is connected to the drain of the PMOS transistor M2, the drain of the PMOS transistor M5 and the gate of the PMOS transistor M6, the base of the NPN transistor Q5 is connected to the base of the NPN transistor Q6, and the collector of the NPN transistor Q6 The electrode and the drain of the PMOS transistor M6 are simultaneously used as the voltage output terminal V _BG of the entire circuit; the emitter of the NPN transistor Q5 is connected to the ground GND through the variable resistor R7; the emitter of the NPN transistor Q6 is connected to the ground through the variable resistor R8 GND; the source of the PMOS transistor M2 is connected to the power supply V _DD through the resistor R5; the gate of the PMOS transistor M3 is connected to the input terminal of the control signal S, and the source of the PMOS transistor M3 is connected to the drain of the PMOS transistor M4 and the PMOS transistor M5 The gate of the PMOS transistor M4 is connected to the input terminal of the control signal SN, the source of the PMOS transistor M4 is connected to the power supply V _DD ; the source of the PMOS transistor M5 is connected to the power supply V _DD through the resistor R6; the PMOS transistor M6’s The source is connected to the power supply V _DD .

In the present invention, the unit NPN tube parameters of NPN tube Q1, NPN tube Q2, NPN tube Q3 and NPN tube Q4 are exactly the same, and the number of unit NPN tubes connected in parallel between NPN tube Q1 and NPN tube Q4 is 8 times that of NPN tube Q2 and NPN tube Q3 . The resistance values of the resistor R4, the resistor R5 and the resistor R6 are equal; the parameters of the PMOS transistor M1, the PMOS transistor M2 and the PMOS transistor M5 are exactly the same. The resistance value of the variable resistor R8 needs to be changed together with the variable resistor R7 to keep the resistance value consistent; the parameters of the NPN transistor Q5 and the NPN transistor Q6 are exactly the same.

The variable resistors R2, R3, R7 and R8 can be realized by various methods such as resistor series and multiple switches. The supply voltage V _DD is 3.3V.

Let the currents flowing through the NPN tubes Q1 and Q2 be I1 and I respectively; the currents flowing through the variable resistors R2, R3 and R7 are respectively I2, I3 and I7; the bases of the NPN tubes Q1, Q2, Q3, Q4 and Q5 - The emitter voltages are V _be 1, V _be 2, V _be 3, V _be 4, V _be 5; the number of unit tubes connected in parallel with NPN transistors Q2 and Q3 is m; the number of unit tubes connected in parallel with NPN transistors Q1 and Q4 is 8m; the base voltage of the NPN transistor Q1 is V _ref .

The expression of the base voltage V _ref of the NPN transistor Q1 can be written as follows:

（1）

(1)

Another expression of the base voltage V _ref of the NPN transistor Q1 is as follows:

（2）

(2)

According to formulas (1) and (2), we can get:

（3）

(3)

、

、

、

。因此（3）式可写为：The unit tube parameters of the NPN tubes Q1, Q2, Q3, and Q4 are all the same, so the saturation currents are equal I _S =I _S1 =I _S2 =I _S3 =I _S4 . The currents flowing through the unit tubes of NPN tubes Q1, Q2, Q3, and Q4 are respectively

,

,

,

. So formula (3) can be written as:

（4）

(4)

According to formula

（5）

(5)

The expression for the current I can be written as follows:

（6）

(6)

S and SN are a pair of anti-phase control signals. When S is "1" and SN is "0", PMOS transistor M3 is turned off, PMOS transistor M4 is turned on, and the gate of PMOS transistor M5 is connected to V _DD and is turned off. When S is "0" and SN is "1", PMOS transistor M3 is turned on, PMOS transistor M4 is turned off, and the gate of PMOS transistor M5 is connected to the gate of PMOS transistor M1.

The current I7 is the mirror current of I. Since the parameters of the PMOS transistors M1, M2, and M5 are consistent, when S is "1" and SN is "0": I7=I; when S is "0" and SN is "1" : I7=2I.

The expression for the final bandgap voltage V _BG can be written as follows:

（7）

(7)

Putting it into (5) can get:

（8）

(8)

When S is "1", k=1; when S is "0", k=2. The temperature coefficients of resistance and current in formula (7) have canceled each other, only V _T , V _be 3, and V _be 5 include temperature coefficients, and the partial derivative of V _BG with respect to temperature can be obtained as:

（9）

(9)

，E_g为硅的带隙能量。当V_be=750mV，T=300°K时可算得：

，

。可知式（8）第一项为正温度系数，后两项为负温度系数，带入式中可得：In the formula, k is Boltzmann's constant, q is the electronic charge, and V _T is the voltage equivalent of temperature:

, E _g is the band gap energy of silicon. When V _be =750mV, T=300°K, it can be calculated as:

,

. It can be seen that the first term of formula (8) is a positive temperature coefficient, and the last two terms are negative temperature coefficients, which can be brought into the formula to get:

It can be known from the above formula that the positive and negative temperature coefficient of V _BG can be adjusted by changing the control signal S\SN and adjusting the resistance values of variable resistors R2, R3 and R7. At the same time, it can be seen from the formula (5) that the magnitude of the current I3 can be changed by adjusting the resistance value of the variable resistor R3.

In the present invention, the gate indices of PMOS transistors M2 and M5 can be changed to different multiples of PMOS transistor M1 respectively to meet design requirements. When changing PMOS transistors M2 and M5, resistance R5 and resistance R6 need to be changed to corresponding values of resistance R4 at the same time. multiples to ensure the stability of the mirror current.

In the present invention, all resistors, NPN tubes and PMOS tubes are of the same type to eliminate the temperature coefficient deviation caused by the process.

By changing the control signal S\SN and adjusting the resistance values of the variable resistors R2, R3, and R7, the positive temperature coefficient, negative temperature coefficient, and reference voltage that do not change with temperature can be realized in the temperature range of -55°C~125°C. As shown in Fig. 2, Fig. 3 and Fig. 4, the horizontal axis is temperature, and the unit is Celsius °C, and the vertical axis is voltage, and the unit is volt (V).

Figure 2 to Figure 4 are just the simulation schematic diagrams of the circuit functions, and the control signal S\SN and the resistance values of the variable resistors R2, R3, and R7 can be adjusted according to actual needs, and realized in the temperature range of -55°C~125°C Reference voltages with different temperature coefficients.

The content that is not described in detail in the description of the present invention belongs to the well-known technology of those skilled in the art. Although the embodiments of the present invention have been described with reference to the accompanying drawings, various variations or modifications may be made by those skilled in the art within the scope of the appended claims.

Claims (4)

1. A reference voltage source with adjustable temperature coefficient, characterized in that it includes a first current generation circuit (100) and a second voltage regulation circuit (200); The first current generating circuit (100) includes NPN transistor Q1, NPN transistor Q2, NPN transistor Q3, NPN transistor Q4, PMOS transistor M1, resistor R1, variable resistor R2, variable resistor R3, and resistor R4; the second voltage The regulating circuit (200) includes NPN tube Q5, NPN tube Q6, PMOS tube M2, PMOS tube M3, PMOS tube M4, PMOS tube M5, PMOS tube M6, resistor R5, resistor R6, variable resistor R7, and variable resistor R8; The base and collector of the NPN transistor Q1 are connected together with the base of the NPN transistor Q2, and at the same time connected to the power supply V _DD through the resistor R1, and the emitter of the NPN transistor Q1 is simultaneously connected to the collector of the NPN transistor Q3 and the terminal of the NPN transistor Q4 Base; the collector of the NPN transistor Q2 is connected to the drain of the PMOS transistor M1, the gate of the PMOS transistor M1, the gate of the PMOS transistor M2, and the drain of the PMOS transistor M3, and the emitter of the NPN transistor Q2 is simultaneously connected to the NPN The base of the tube Q3 and the collector of the NPN tube Q4 are connected to the ground GND through the variable resistor R3; the emitter of the NPN tube Q3 is connected to the ground GND; the emitter of the NPN tube Q4 is connected to the ground GND through the variable resistor R2 ; The source of the PMOS transistor M1 is connected to the power supply V _DD through the resistor R4; The collector of the NPN transistor Q5 is simultaneously connected to the drain of the PMOS transistor M2, the drain of the PMOS transistor M5 and the gate of the PMOS transistor M6, the base of the NPN transistor Q5 is connected to the base of the NPN transistor Q6, and the collector of the NPN transistor Q6 The electrode and the drain of the PMOS transistor M6 are simultaneously used as the voltage output terminal V _BG of the entire circuit; the emitter of the NPN transistor Q5 is connected to the ground GND through the variable resistor R7; the emitter of the NPN transistor Q6 is connected to the ground through the variable resistor R8 GND; the source of the PMOS transistor M2 is connected to the power supply V _DD through the resistor R5; the gate of the PMOS transistor M3 is connected to the input terminal of the control signal S, and the source of the PMOS transistor M3 is connected to the drain of the PMOS transistor M4 and the PMOS transistor M5 The gate of the PMOS transistor M4 is connected to the input terminal of the control signal SN, the source of the PMOS transistor M4 is connected to the power supply V _DD ; the source of the PMOS transistor M5 is connected to the power supply V _DD through the resistor R6; the PMOS transistor M6’s The source is connected to the power supply V _DD ; The port S/SN is set as required: S is connected to the power supply V _DD , and SN is connected to the ground GND; or S is connected to the ground GND, and SN is connected to the power supply V _DD . 2. A reference voltage source with adjustable temperature coefficient according to claim 1, characterized in that: the unit NPN tube parameters of the NPN tube Q1, NPN tube Q2, NPN tube Q3 and NPN tube Q4 are exactly the same, and the NPN tube parameters are exactly the same. The number of NPN tubes in the unit in which the tube Q1 and the NPN tube Q4 are connected in parallel is 8 times that of the NPN tube Q2 and the NPN tube Q3. 3. A reference voltage source with adjustable temperature coefficient according to claim 1, characterized in that: the resistance values of the resistor R4, the resistor R5 and the resistor R6 are equal, and the PMOS transistor M1, the PMOS transistor M2 and the PMOS transistor M5 parameters are exactly the same. 4. A reference voltage source with adjustable temperature coefficient according to claim 1, characterized in that: the resistance value of the variable resistor R8 needs to change together with the variable resistor R7 to keep the resistance value consistent, and the NPN tube The parameters of Q5 and NPN tube Q6 are exactly the same.

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