CN114510106B - An ultra-low static power leakage compensation circuit applied to high temperature LDO - Google Patents

Abstract

The invention belongs to the technical field of analog circuit power management, and in particular relates to an ultra-low static power consumption leakage compensation circuit applied to a high temperature LDO. In the present invention, the leakage current of the power tube is sampled in equal proportion by a sampling tube of the same type as the power tube, and then a current sink is generated through the current proportional amplifier, and the leakage current of the power tube is discharged by the current sink. In the non-high temperature working state, the sampling tube is normally turned off, but if there is leakage current in the power tube under high temperature working conditions, then the sampling tube will sample the leakage current; at the same time, the leakage current compensation circuit should ensure that as long as there is an input voltage , the leakage current compensation circuit can work. Solve the problem of chip failure caused by the leakage current of the power tube in the LDO under high temperature conditions.

Description

An Ultra-low Static Power Leakage Compensation Circuit Applied to High Temperature LDO

technical field

The invention belongs to the technical field of analog circuit power management, and in particular relates to an ultra-low static power leakage compensation circuit applied to a high-temperature LDO.

Background technique

In recent years, concepts such as new energy, autonomous driving, and smart transportation have continued to develop, and a large number of electronic systems have assumed different roles in automobiles. Power management chips are the heart of energy conversion for electronic systems. The increasing number of on-board electronic devices and complex usage scenarios have put forward more stringent standards for power management chips and brought strong market demand. LDO is a common type of power management chip. Compared with other types of power management chips, it has the advantages of low output voltage ripple, low quiescent current and high loop bandwidth. Therefore, for the reliability, low power consumption and fast transient response requirements in automotive electronics, LDO has considerable market value.

LDOs can be divided into NMOS LDOs and PMOS LDOs according to whether the power transistors used are NMOS power transistors or PMOS power transistors. In order to ensure that the power tube still has a certain gate-source voltage when the input-output voltage difference is small, the NMOS LDO needs to add an additional charge pump circuit to increase the gate voltage of the NMOS power tube, which will introduce additional power consumption. The gate-source voltage of the PMOS LDO power transistor can be adjusted between the input voltage and the ground potential, so relatively speaking, the PMOS LDO will have higher working efficiency.

Since the technology of domestic automotive chips is not perfect at present, chips used in automobiles will have leakage current at high temperatures. In general, an LDO must maintain a stable output voltage DC value under no-load conditions. For LDOs that require low static power consumption, the resistance value of the output voltage divider resistor network is generally very high, and because the power tube itself has a large area, the leakage current of the power tube itself is considerable under high temperature conditions, so it is very It is easy to cause the output voltage to deviate from the normal working state under high temperature conditions. Under normal working conditions, due to the small current, these leakage currents will not affect the working state of the chip, but under extreme conditions, these leakage currents will affect the working state of the chip and cause the chip to fail. Therefore, how to solve the problem of chip leakage at high temperature? The effect of current is very critical.

Contents of the invention

Aiming at the problem that the traditional dynamic LDO circuit causes chip failure due to leakage at high temperature, the present invention proposes an ultra-low static power consumption leakage compensation circuit applied to a high temperature LDO. The design idea is to sample the leakage current of the power tube in equal proportion through a sampling tube of the same type as the power tube, and then generate a current sink through the current proportional amplifier, and use the current sink to discharge the leakage current of the power tube. In the non-high temperature working state, the sampling tube is normally turned off, and in the high temperature working condition, if there is a leakage current in the power tube, the sampling tube will sample the leakage current; at the same time, the leakage current compensation circuit must ensure that as long as there is input voltage , the leakage current compensation circuit can work.

To achieve the above object, the technical solution of the present invention is:

An ultra-low static power leakage compensation circuit applied to a high-temperature LDO, including a sampling circuit, a current amplification circuit and a voltage-to-current circuit; the voltage-to-current circuit also includes an enabling control part; the sampling circuit utilizes a gate-source short circuit The sampling tube is connected, so that it can not only ensure that the sampling circuit can accurately sample the current of the power tube when the power tube leaks, but also ensure that the sampling circuit is turned off when the power tube is working normally, reducing the loss of static power consumption; because the sampling tube The size ratio of the power tube is very small, so the sampled current is also relatively small. In order to ensure that the leakage current compensation circuit can completely absorb the leakage current, and at the same time meet the requirements of the input range of the subsequent voltage-to-current circuit, the sampled current needs to be amplified. This is the function of the current amplification circuit; and the final voltage-to-current circuit is to re-amplify the amplified sampling current to ensure that the amplified current sink can completely compensate the leakage current of the power tube;

The sampling circuit includes a first sampling tube MS1, a second sampling tube MS2, a first NMOS tube MN1, a second NMOS tube MN2, a first NMOS withstand voltage tube MNH1, a first PMOS tube MP1, a second PMOS tube MP2, a first A zener diode D1; wherein, the source and gate of the first sampling tube MS1 are connected to the input voltage, and the drain is connected to the cathode of the first zener diode D1, the gate-drain of the first NMOS transistor MN1 and the second NMOS transistor The gate of MN2; the anode of the first Zener diode D1, the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are grounded; the drain of the second NMOS transistor MN2 is connected to the first NMOS withstand voltage transistor MNH1 source, the gate of the first NMOS withstand voltage transistor MNH1 is connected to the first bias voltage VB, the drain of the first NMOS withstand voltage transistor MNH1 is connected to the drain of the first PMOS transistor MP1; the source of the first PMOS transistor MP1 is connected to The output terminal, its gate and drain are interconnected; the source and gate of the second sampling tube MS2 are connected to the input voltage, and its drain is connected to the source of the second PMOS transistor MP2; the gate of the second PMOS transistor MP2 is connected to the first A gate of the PMOS transistor MP1;

The current amplifying circuit includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a second NMOS withstand voltage transistor MNH2, a first resistor R1, and a second Zener diode D2; Wherein, the cathode of the second Zener diode D2, the gate drain of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4 are connected to the drain of the second PMOS transistor MP2; the anode of the second Zener diode D2, the third The source of the NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are grounded; the source of the third PMOS transistor MP3 is connected to the input voltage, and its gate and drain are interconnected; the drain of the second NMOS withstand voltage transistor MNH2 is connected to the first The drain of the third PMOS transistor MP3, the gate of the second NMOS withstand voltage transistor MNH2 is connected to the bias voltage, the source of the second NMOS withstand voltage transistor MNH2 is connected to the drain of the fourth NMOS transistor MN4; the source of the fourth PMOS transistor MP4 The pole is connected to the input voltage, its gate is connected to the drain of the third PMOS transistor MP3, the drain of the fourth PMOS transistor MP4 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded;

The voltage-to-current circuit includes a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, and a sixth PMOS transistor MP7. Eight PMOS transistors MP8, the second resistor R2, and the third zener diode D3; wherein, the source of the seventh PMOS transistor MP7 is connected to the input voltage, its gate is connected to the drain of the third PMOS transistor MP3, and the gate of the seventh PMOS transistor MP7 is connected to the input voltage. The drain is connected to the source of the fifth PMOS transistor MP5, the cathode of the third Zener diode D3, the source of the seventh NMOS transistor MN7 and the source of the sixth PMOS transistor MP6; the gate of the fifth NMOS transistor MN5 is connected to the fourth The drain of the PMOS transistor MP4, the drain of the fifth NMOS transistor MN5 are connected to the gate drain of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor MN6, the source of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 The source is grounded; the source of the eighth PMOS transistor MP8 is connected to the internal power supply voltage VDD1, its gate is connected to the second bias voltage VBP, and its drain is connected to the drain of the seventh NMOS transistor MN7; the gate of the seventh NMOS transistor MN7 connected to the enabling signal; the gate of the sixth PMOS transistor MP6 is connected to the source of the eighth NMOS transistor MN8, the drain of the sixth PMOS transistor MP6 is connected to the drain of the sixth NMOS transistor; the gate of the eighth NMOS transistor NM8 is connected to the first The drain of the sixth PMOS transistor MP6 and the drain of the eighth NMOS transistor MN8 are connected to one end of the second resistor R2 as an output end, and the other end of the second resistor R2 is grounded.

The beneficial effect of the invention is that the problem of chip failure caused by the leakage current of the power tube under the high temperature condition of the LDO is solved. The circuit of the invention can ensure that the internal leakage current compensation circuit of the chip can perform self-adaptive compensation according to the leakage current of the power tube under extreme conditions, thereby ensuring the stability of the output voltage within a normal load range. At the same time, within the normal operating range, the leakage compensation can maintain a small static power consumption, and improve the overall working efficiency of the circuit.

Description of drawings

Fig. 1 is the overall frame diagram of the ultra-low static power leakage compensation circuit applied to the high-temperature LDO proposed by the present invention;

Fig. 2 is a kind of specific circuit realization diagram in the embodiment of the ultra-low static power leakage compensation circuit applied to the high-temperature LDO proposed by the present invention;

Note: Transistors whose names start with MP are PMOS (P-Metal-Oxide-Semiconductor) tubes; transistors whose names start with MN are NMOS (N-Metal-Oxide-Semiconductor) tubes; devices whose names start with R are resistors; A device starting with D is a diode; VIN is an input voltage; VB is a first bias voltage; VBP is a second bias voltage; VDD is an internally generated supply voltage.

Detailed ways

Below in conjunction with accompanying drawing, technical solution of the present invention is described in detail:

As shown in Fig. 1, the general structure diagram of the ultra-low static power leakage compensation circuit applied to high-temperature LDO proposed by the present invention, the power tube adopts PMOS power tube, mainly includes sampling circuit, voltage-to-current circuit, and PMOS power tube.

The sampling circuit samples the leakage current of the power tube. When the power tube has no leakage current, the sampling tube will not have current. At this time, the two input terminals of the op amp are at ground potential, and the leakage compensation circuit does not output current and keeps it at The state of ultra-low static power consumption; when the power tube leaks, the sampling tube will sample the leakage current in equal proportions and convert the leakage current into a voltage. Then, the sampling current is amplified proportionally by the method of converting voltage to current. As long as the appropriate sampling ratio and current amplification ratio are set, the compensation for the leakage current of the power tube can be realized by means of a circuit.

As shown in FIG. 2 , it is a specific implementation circuit of the ultra-low static power leakage compensation circuit applied to high-temperature LDO proposed by the present invention.

The sampling circuit includes a clamping circuit and the main sampling tube MS2. When the power tube has no leakage current, the main sampling tube and the clamping circuit do not work; but when the main power tube has a leakage current, both sampling tubes MS1 and MS2 flow When the sampling current of the same size is passed, the clamping circuit will clamp the leakage potential of the sampling tube MS2 to the VOUT potential at this time, so as to ensure the sampling accuracy of the main sampling tube MS2. At the same time, there is also a voltage-resistant tube MNH1 in the circuit, which is used to avoid the risk of breakdown of the MN2 tube when the output voltage is too high.

The current amplification circuit amplifies the sampled leakage current in an appropriate proportion. Since the ratio of the sampling tube to the power tube is relatively small, the sampled current is very small. In order to reduce the influence of the leakage current of other tubes, the sampled leakage current must be amplified. At the same time, due to the limitation of the input range of the voltage-to-current circuit, the gate voltage of the MP5 tube cannot be too low, so amplifying the sampling current can also prevent R1 from being too large and occupying too much area.

The voltage-to-current circuit uses the principle of op amp clamping to amplify the current flowing through the resistor R1 to the resistor R2 in equal proportions. The ratio of the current flowing through R2 to the current flowing through R1 is

The error amplifier in the voltage-to-current circuit is a modified five-tube operational amplifier. Its tail current consists of two parts, one part is the amplified sampling current, which is provided by the MP7 tube. Under the condition of enabling, that is, under the condition of no reference current, the error amplifier can still work normally under the condition that the power tube has a leakage current; the other part is the reference current, which is provided by the MP8 tube. The function of this part of the current is to ensure that the chip During normal operation, the error amplifier remains in a stable working state, avoiding the turn-on process of the error amplifier.

In order to ensure that the chip is supplied with input voltage, but the leakage compensation circuit can still work when it is not enabled, the circuit also adds a MN7 tube in addition to the MP7 tube. The function of the MN7 tube is to switch the MP8 tube from the error amplifier when the chip is not enabled. The disconnection prevents the current of the MP7 tube from flowing to VDD1 through the MP8 tube, thus causing the problem that the error amplifier does not work.

In this design, assuming that the size ratio of MS2 to the power tube is α, and the amplification factor of the current amplifier circuit is β, then as long as the

Then the current generated by the leakage compensation circuit is exactly equal to the leakage current of the power tube, so that the leakage compensation circuit can ensure the stability of the output voltage of the chip under high temperature and no-load conditions. Moreover, the circuit can also adaptively adjust the magnitude of the compensation current following the magnitude of the leakage current of the power tube.

Claims (1)

1. An ultra-low static power leakage compensation circuit applied to a high-temperature LDO, characterized in that it comprises a sampling circuit, a current amplification circuit and a voltage-to-current circuit; The sampling circuit includes a first sampling tube MS1, a second sampling tube MS2, a first NMOS tube MN1, a second NMOS tube MN2, a first NMOS withstand voltage tube MNH1, a first PMOS tube MP1, a second PMOS tube MP2, a first A zener diode D1; wherein, the source and gate of the first sampling tube MS1 are connected to the input voltage, and the drain is connected to the cathode of the first zener diode D1, the gate-drain of the first NMOS transistor MN1 and the second NMOS transistor The gate of MN2; the anode of the first Zener diode D1, the source of the first NMOS transistor MN1 and the source of the second NMOS transistor MN2 are grounded; the drain of the second NMOS transistor MN2 is connected to the first NMOS withstand voltage transistor MNH1 source, the gate of the first NMOS withstand voltage transistor MNH1 is connected to the first bias voltage VB, the drain of the first NMOS withstand voltage transistor MNH1 is connected to the drain of the first PMOS transistor MP1; the source of the first PMOS transistor MP1 is connected to The output terminal, its gate and drain are interconnected; the source and gate of the second sampling tube MS2 are connected to the input voltage, and its drain is connected to the source of the second PMOS transistor MP2; the gate of the second PMOS transistor MP2 is connected to the first A gate of the PMOS transistor MP1; The current amplifying circuit includes a third NMOS transistor MN3, a fourth NMOS transistor MN4, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a second NMOS withstand voltage transistor MNH2, a first resistor R1, and a second Zener diode D2; Wherein, the cathode of the second Zener diode D2, the gate drain of the third NMOS transistor MN3, the gate of the fourth NMOS transistor MN4 are connected to the drain of the second PMOS transistor MP2; the anode of the second Zener diode D2, the third The source of the NMOS transistor MN3 and the source of the fourth NMOS transistor MN4 are grounded; the source of the third PMOS transistor MP3 is connected to the input voltage, and its gate and drain are interconnected; the drain of the second NMOS withstand voltage transistor MNH2 is connected to the first The drain of the third PMOS transistor MP3, the gate of the second NMOS withstand voltage transistor MNH2 is connected to the bias voltage, the source of the second NMOS withstand voltage transistor MNH2 is connected to the drain of the fourth NMOS transistor MN4; the source of the fourth PMOS transistor MP4 The pole is connected to the input voltage, its gate is connected to the drain of the third PMOS transistor MP3, the drain of the fourth PMOS transistor MP4 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is grounded; The voltage-to-current circuit includes a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, an eighth NMOS transistor MN8, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a seventh PMOS transistor MP7, and a sixth PMOS transistor MP7. Eight PMOS transistors MP8, the second resistor R2, and the third zener diode D3; wherein, the source of the seventh PMOS transistor MP7 is connected to the input voltage, its gate is connected to the drain of the third PMOS transistor MP3, and the gate of the seventh PMOS transistor MP7 is connected to the input voltage. The drain is connected to the source of the fifth PMOS transistor MP5, the cathode of the third Zener diode D3, the source of the seventh NMOS transistor MN7 and the source of the sixth PMOS transistor MP6; the gate of the fifth NMOS transistor MN5 is connected to the fourth The drain of the PMOS transistor MP4, the drain of the fifth NMOS transistor MN5 are connected to the gate drain of the fifth NMOS transistor MN5 and the gate of the sixth NMOS transistor MN6, the source of the fifth NMOS transistor MN5 and the sixth NMOS transistor MN6 The source is grounded; the source of the eighth PMOS transistor MP8 is connected to the internal power supply voltage VDD1, its gate is connected to the second bias voltage VBP, and its drain is connected to the drain of the seventh NMOS transistor MN7; the gate of the seventh NMOS transistor MN7 connected to the enabling signal; the gate of the sixth PMOS transistor MP6 is connected to the source of the eighth NMOS transistor MN8, the drain of the sixth PMOS transistor MP6 is connected to the drain of the sixth NMOS transistor; the gate of the eighth NMOS transistor NM8 is connected to the first The drain of the sixth PMOS transistor MP6 and the drain of the eighth NMOS transistor MN8 are connected to one end of the second resistor R2 as an output end, and the other end of the second resistor R2 is grounded.

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