CN110247645A - A kind of voltage comparator - Google Patents
A kind of voltage comparator Download PDFInfo
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- CN110247645A CN110247645A CN201910438624.4A CN201910438624A CN110247645A CN 110247645 A CN110247645 A CN 110247645A CN 201910438624 A CN201910438624 A CN 201910438624A CN 110247645 A CN110247645 A CN 110247645A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
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Abstract
The invention discloses a kind of voltage comparators, including the PTAT current source, differential gain stage and the output stage that sequentially electrically connect and voltage positive input, voltage negative input, power end, ground terminal and output end；PTAT current source, the reference current directlyed proportional to the ratio between resistance generation to temperature using the difference of the gate source voltage difference of two metal-oxide-semiconductors provide current offset for differential gain stage, inhibit influence of the high temperature to comparator performance；Differential gain stage, including Folded-cascode amplifier and biasing circuit with negative resistance load；Gain can be improved using Foldable cascade structure in Folded-cascode amplifier with negative resistance load, is conducive to further increase gain using negative resistance load, biasing circuit provides DC offset voltage for differential gain stage；Output stage can increase the speed of comparator using the common source circuit for having cross-coupled positive feedback.The present invention has the characteristics that precision is high, speed is fast and height temperate zone is inhibited to carry out penalty.
Description
Technical field
The present invention relates to IC design fields, and in particular to a kind of High speed and high precision voltage comparator.
Background technique
With the fast development of semiconductor integrated circuit technology, system on chip, which has been obtained, to be widely applied.Voltage ratio
Can have in most systems on chip by analog voltage signal by comparing positive and negative terminal voltage output digital signal compared with device
The figure of voltage comparator；The indexs such as speed, precision, delay time and the power consumption of voltage comparator are all for whole system
Vital, the superiority and inferiority of voltage comparator directly decides the performance of whole system.
Voltage comparator can be divided into static comparison device and dynamic comparer, and dynamic comparer needs clock, and can introduce and make an uproar
Sound；Static comparison device realizes that required power consumption is larger using operational amplifier, and is not suitable for High Speed System.Fig. 1 show one
The conventional voltage comparator constituted using two-stage calculation amplifier, IB is bias current inputs, and P1 is offset, and the first order is put
Big device is made of NMOS tube N1~N4 and PMOS tube P2, and second level amplifier is made of NMOS tube N5 and PMOS tube P3.Shown in Fig. 2
To input 33MHz frequency in 60 DEG C of temperature, when input difference is 70mV, the precision simulation figure of the voltage comparator of traditional structure；?
Under this condition, comparator works normally, dynamic power consumption 190uA.Fig. 3 is shown in 60 DEG C of temperature, inputs 33MHz frequency, defeated
Enter difference be 50mV when, the precision simulation figure of the voltage comparator of traditional structure, under this condition, comparator cannot normal works
Make；Fig. 4 is shown in 150 DEG C of temperature, inputs 33MHz frequency, when input difference is 50mV, the essence of the voltage comparator of traditional structure
Analogous diagram is spent, under this condition, comparator cisco unity malfunction.The bandwidth of operational amplifier decides the speed of comparator,
The gain of operational amplifier decides the precision of comparator, and the static comparison device of this traditional structure is by op-amp gain
The limitation of bandwidth product, speed and precision are limited；It needs to consume very big power consumption in addition, improving gain bandwidth product.In addition in high temperature
Under, the gain bandwidth product of the operational amplifier of structure shown in Fig. 1 can be obviously reduced, therefore at high temperature, the performance of comparator
It will receive obvious deterioration.
Summary of the invention
In view of this, a voltage comparator is proposed present invention solves the technical problem that be to overcome the shortcomings of existing methods,
Speed and precision will not be limited because of the raising of op-amp gain bandwidth product by limitation, while can not also be by high temperature
It influences.
To solve the above problems, the present invention is realized by following technological means:
A kind of voltage comparator, it is characterised in that: including the PTAT current source, differential gain stage and output sequentially electrically connected
Grade and voltage positive input VIP, voltage negative input VIN, power end VCC, ground terminal VSS and output end vo ut；
The positive feeder ear of PTAT current source, the positive feeder ear of differential gain stage, output stage positive feeder ear be connected to electricity
Source VCC；The negative feeder ear of PTAT current source, the negative feeder ear of differential gain stage, output stage negative feeder ear be connected to ground
Hold VSS；The positive input terminal of voltage positive input VIP connection differential gain stage, voltage negative input VIN connection differential gain
The negative input end of grade, the bias current inputs of the output end connection differential gain stage of PTAT current source, differential gain stage is just
Output end connects the positive input terminal of output stage, and the negative output terminal of differential gain stage connects the negative input end of output stage, output stage
Output end connects output end vo ut；
PTAT current source, the base directlyed proportional to the ratio between resistance generation to temperature using the difference of two metal-oxide-semiconductor gate source voltage differences
Quasi- electric current inhibits influence of the high temperature to comparator performance for providing current offset for differential gain stage；
Differential gain stage, including Folded-cascode amplifier and biasing circuit with negative resistance load；Band negative resistance load
Folded-cascode amplifier, Foldable cascade structure is for improving gain, and negative resistance load is for further increasing
Gain, biasing circuit are used to provide DC offset voltage for differential gain stage；
Output stage, using the common source circuit for having cross-coupled positive feedback, for increasing the speed of comparator.
A kind of specific embodiment as PTAT current source, it is characterised in that: the PTAT current source includes
NMOS tube N1~N4, PMOS tube P1~P3 and resistance R1；The source electrode of PMOS tube P1~P3 is electrically coupled to power end VCC；PMOS tube
The grid of P1~P3 electrically connects, and is electrically coupled to the drain electrode of PMOS tube P2 and NMOS tube N2 simultaneously；The drain electrode of PMOS tube P1, NMOS
The grid of the N1 of pipe and the anode of resistance R1 electrically connect；The drain electrode of the cathode, NMOS tube N1 of resistance R1 and the grid of NMOS tube N2
It electrically connects；The drain electrode of PMOS tube P3, the drain electrode of the grid and N4 of NMOS tube N4 electrically connect；Grid, the NMOS tube N3 of NMOS tube N3
Drain electrode and the source electrode of NMOS tube N4 electrically connect, tie point is the output end of PTAT current source；The source electrode electricity of NMOS tube N1~N3
It is connected to ground terminal VSS.
A kind of specific embodiment as differential gain stage, it is characterised in that: the differential gain stage includes
NMOS tube N5~N13, PMOS tube P4~P6, resistance R2~R4 and capacitor C1~C2；Wherein, NMOS tube N5~N12, PMOS tube P4
~P5, resistance R2~R3 and capacitor C1 constitute the Folded-cascode amplifier with negative resistance load, NMOS tube N13, PMOS tube
P6, resistance R4 and capacitor C2 constitute biasing circuit；The anode of resistance R2~R4 and the top crown of capacitor C2 are electrically coupled to power end
VCC；The cathode of resistance R2, the drain electrode of NMOS tube N6, the drain electrode of N9, the grid of N10 and PMOS tube P4 source electrode electrically connect；Resistance
The cathode of R3, the drain electrode of NMOS tube N7, the drain electrode of N10, the grid of N9 and PMOS tube P5 source electrode electrically connect；The grid of NMOS tube N6
Pole is electrically coupled to voltage negative input VIN；The grid and voltage positive input VIP of NMOS tube N7 electrically connects；NMOS tube N6
The drain electrode of the source electrode and NMOS tube N5 of~N7 electrically connects；The grid of NMOS tube N5, the grid of N8, N11~13 grid and capacitor
The top crown of C1 electrically connects, and tie point is the bias current inputs of differential gain stage；The source electrode and NMOS of NMOS tube N9~N10
The drain electrode of pipe N8 electrically connects；The grid of PMOS tube P4~P5, the grid of P6, the drain electrode of P6, the drain electrode of NMOS tube N13 and capacitor C2
Bottom crown electrically connect；The cathode of resistance R4 and the source electrode of PMOS tube P6 electrically connect；The drain electrode of PMOS tube P4 and NMOS tube N11's
Drain electrode electrically connects, and tie point is the negative output terminal of differential gain stage；The drain electrode of PMOS tube P5 and the drain electrode Electricity Federation of NOMS pipe N12
It connects, tie point is the positive output end of differential gain stage；The source electrode of NMOS tube N5, the source electrode of N8, N11~N13 source electrode and capacitor
The bottom crown of C1 is electrically coupled to ground terminal VSS.
A kind of specific embodiment as output stage, it is characterised in that: the output stage include NMOS tube N14~
N15, PMOS tube P7~P8 and resistance R5~R6；Wherein NMOS tube N14~N15, PMOS tube P7~P8 and resistance R5~R6 are constituted
The output circuit of positive feedback structure；The source electrode of PMOS tube P7~P8 and the anode of resistance R5~R6 are electrically coupled to power end VCC；
The grid of PMOS tube P7, the drain electrode of PMOS tube P8, the drain electrode of NMOS tube N14 and resistance R5 cathode electrically connect；NMOS tube N14's
Grid is the positive input terminal of output stage；The drain electrode of PMOS tube P7, the grid of PMOS tube P8, the drain electrode of NMOS tube N15 and resistance R6
Cathode electrically connect, and be electrically coupled to output end vo ut simultaneously；The grid of NMOS tube N15 is the negative output terminal of output stage；NMOS
The source electrode of pipe N14~N15 is electrically coupled to ground terminal VSS.
Term is explained:
PTAT current source: the full name in English of " PATA " is " proportionaltoabsolutetemperature ", Chinese
It is translated as " with absolute temperature is proportional ", therefore the meaning of " PTAT current source " is " with the current source that absolute temperature is proportional ".
Compared with prior art, the present invention has a characteristic that
1, it uses output electric current and the positively related current source of temperature to provide current offset for comparator, is able to suppress height temperate zone
The penalty come；
2, using the folded common source and common grid amplifier with negative resistance type load, it can be realized biggish gain, increase is compared
The precision of device；
3, using the output stage with positive feedback, it is capable of increasing the speed of comparator.
The technical solution that the present invention is mentioned, working principle and theory analysis carry out specifically in a specific embodiment
It is bright, it has the advantage that:
(1) precision of comparator is high；
(2) speed of comparator is fast；
(3) comparator is able to suppress high temperature bring penalty.
Detailed description of the invention
Fig. 1 is the circuit diagram of the voltage comparator of traditional structure；
Fig. 2 is the voltage comparator of traditional structure in 60 DEG C of temperature, inputs 33MHz frequency, wink when input difference is 70mV
State analogous diagram；
Fig. 3 is the voltage comparator of traditional structure in 60 DEG C of temperature, inputs 33MHz frequency, wink when input difference is 50mV
State analogous diagram；
Fig. 4 is the voltage comparator of traditional structure in 150 DEG C of temperature, inputs 33MHz frequency, wink when input difference is 70mV
State analogous diagram；
Fig. 5 is the functional block diagram of the embodiment of the present invention；
Fig. 6 is the circuit diagram of the voltage comparator of the embodiment of the present invention；
Fig. 7 is the voltage comparator of the embodiment of the present invention at 60 DEG C, inputs 50MHz frequency, wink when input difference is 50mV
State analogous diagram；
Fig. 8 is the voltage comparator of the embodiment of the present invention at 150 DEG C, inputs 50MHz frequency, wink when input difference is 50mV
State analogous diagram.
Specific embodiment
Fig. 5 show the functional schematic block diagram of circuit comparator of the invention, comprising: PTAT current source, differential gain stage
And output stage and voltage positive input VIP, voltage negative input VIN, power end VCC, ground terminal VSS and output end
Vout；The positive feeder ear of PTAT current source, the positive feeder ear of differential gain stage, output stage positive feeder ear be connected to power end
VCC；The negative feeder ear of PTAT current source, the negative feeder ear of differential gain stage, output stage negative feeder ear be connected to ground terminal
VSS；The positive input terminal of voltage positive input VIP connection differential gain stage, voltage negative input VIN connection differential gain stage
Negative input end, PTAT current source output end connection differential gain stage bias current inputs, differential gain stage it is just defeated
Outlet connect output stage positive input terminal, differential gain stage negative output terminal connection output stage negative input end, output stage it is defeated
Outlet connects output end vo ut.In order to make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing
And embodiment, the present invention is described in more detail.It should be appreciated that specific embodiment described herein is only used to explain this
Invention, is not intended to limit the present invention.
Fig. 6 is the circuit diagram of the voltage comparator of the embodiment of the present invention, and the voltage comparator ontology is by PMOS
Pipe P1~P8, NMOS tube N1~N15, resistance R1~R6 and capacitor C1~C2 are constituted；
Wherein, PTAT current source, including NMOS tube N1~N4, PMOS tube P1~P3 and resistance R1；
Differential gain stage, including NMOS tube N5~N13, PMOS tube P4~P6, resistance R2~R4 and capacitor C1~C2；
Output stage, including NMOS tube N14~N15, PMOS tube P7~P8 and resistance R5~R6；
Each circuit forms connection relationship are as follows:
PTAT current source, wherein be the positive feeder ear of PTAT current source after the source electrode connection of PMOS tube P1~P3, and Electricity Federation
It is connected to power end VCC；The grid of PMOS tube P1~P3 electrically connects, and is electrically coupled to the leakage of PMOS tube P2 and NMOS tube N2 simultaneously
Pole；The anode of the drain electrode of PMOS tube P1, the grid of the N1 of NMOS tube and resistance R1 electrically connects；Cathode, the NMOS tube N1 of resistance R1
Drain electrode and the grid of NMOS tube N2 electrically connect；The drain electrode of PMOS tube P3, the drain electrode of the grid and N4 of NMOS tube N4 electrically connect；
The drain electrode of the grid, N3 of NMOS tube N3 connected with the source electrode of NMOS tube N4 after be PTAT current source output end；NMOS tube N1~
It is the negative feeder ear of PTAT current source after the source electrode connection of N3, and is electrically coupled to ground terminal VSS.
Differential gain stage, wherein it is negative that NMOS tube N5~N12, PMOS tube P4~P5, resistance R2~R3 and capacitor C1 constitute band
The Folded-cascode amplifier of load is hindered, NMOS tube N13, PMOS tube P6, resistance R4 and capacitor C2 constitute biasing circuit；Electricity
The anode of resistance R2~R4 is the positive feeder ear of differential gain stage after connecting with the top crown of capacitor C2, and is electrically coupled to power end
VCC；The cathode of resistance R2, the drain electrode of NMOS tube N6, the drain electrode of N9, the grid of N10 and PMOS tube P4 source electrode electrically connect；Resistance
The cathode of R3, the drain electrode of NMOS tube N7, the drain electrode of N10, the grid of N9 and PMOS tube P5 source electrode electrically connect；The grid of NMOS tube N6
The extremely negative input end of differential gain stage is electrically coupled to voltage negative input VIN；The grid of NMOS tube N7 is differential gain stage
Positive input terminal, be electrically coupled to voltage positive input VIP；The source electrode of NMOS tube N6~N7 and the drain electrode Electricity Federation of NMOS tube N5
It connects；The grid of NMOS tube N5, the grid of N8, N11~13 grid connected with the top crown of capacitor C1 after for differential gain stage
Bias current inputs Vb, and it is electrically coupled to the output end of PTAT current source simultaneously；The source electrode and NMOS tube of NMOS tube N9~N10
The drain electrode of N8 electrically connects；The grid of PMOS tube P4~P5, the grid of P6, the drain electrode of P6, the drain electrode of NMOS tube N13 and capacitor C2
Bottom crown electrically connects；The cathode of resistance R4 and the source electrode of PMOS tube P6 electrically connect；The drain electrode of PMOS tube P4 and the leakage of NMOS tube N11
It is the negative output terminal ON of differential gain stage after the connection of pole；The drain electrode of PMOS tube P5 is difference after connecting with the drain electrode of NOMS pipe N12
The positive output end OP of gain stage；The source electrode of NMOS tube N5, the source electrode of N8, N11~N13 source electrode connected with the bottom crown of capacitor C1
Afterwards it is the negative feeder ear of differential gain stage, and is electrically coupled to ground terminal VSS.
Output stage, wherein NMOS tube N14~N15, PMOS tube P7~P8 and resistance R5~R6 constitute the defeated of positive feedback structure
Circuit out；It is the positive feeder ear of output stage after the anode connection of the source electrode and resistance R5~R6 of PMOS tube P7~P8, and electrically connects
To power end VCC；The cathode of the drain electrode of the grid, P8 of PMOS tube P7, the drain electrode of NMOS tube N14 and resistance R5 electrically connects；NMOS
The grid of pipe N14 is electrically coupled to the positive output end of differential gain stage；The drain electrode of PMOS tube P7, the leakage of the grid of P8, NMOS tube N15
Pole is the output end of output stage after connecting with the cathode of resistance R6, and is electrically coupled to output end vo ut simultaneously；The grid of NMOS tube N15
Pole is electrically coupled to the negative output terminal of differential gain stage；It is the negative feeder ear of output stage after the source electrode connection of NMOS tube N14~N15,
It is electrically coupled to ground terminal VSS.
The working principle of the present embodiment are as follows:
As shown in fig. 6, the present embodiment includes PTAT current source, differential gain stage and output stage:
PTAT current source: N1, N2, R1, P1 and P2 constitute PTAT current generation circuit, flow through the electric current I of P2DP2It can be with table
It is shown as:
In above formula, VGSN1Poor, the V for the gate source voltage of N1GSN2It is poor for the gate source voltage of N2；Due to VGSN1And VGSN2Difference tool
There are positive temperature coefficient, therefore IDP2With positive temperature coefficient.P3 and N3 is current mirror branch, for replicating IDP2, give differential gain
Grade provides current offset；N4 can reduce the current mismatch as caused by channel-length modulation, improve current mirror accuracy of repetition.
Differential gain stage: N5, N6, N7, which are constituted, folds Differential Input, and N6, N7 are common source Differential Input to pipe, and N5 is tail electricity
Flow tube；N5 provides bias current for N6 and N7；R2, R3, P4, P5, N11 and N12 constitute cathode-input amplifier, N11 and N12 duplication
PTAT current provides current offset for cathode-input amplifier, and P4 and P5 are common-gate amplifier tube；N8, N9, N10 are cross-coupling load,
Common source stage gain can be increased；N13, P6, R4 constitute biasing circuit, provide voltage bias for cathode-input amplifier；C1 and C2 can be with
Ripple is filtered out, current mirror precision is improved；VIP end signal and VIN end signal can be had the folding of cross-coupling negative resistance load
The amplification of formula common source and common grid amplifier, is capable of providing higher voltage gain compared to traditional folded common source and common grid amplifier, this
The precision of comparator will be increased.If VIP end signal increases, OP end signal can be quickly greatly lowered；If VIP end signal drops
Low, OP end signal quickly can significantly increase.Similarly, VIN end signal increases, and ON end signal can quickly be greatly lowered；If
VIN end signal reduces, and ON end signal quickly can significantly increase.
Output stage: the difference common-source amplifier with positive feedback；N14 and N15 is common source amplifier tube, R5 and R6 negative for resistance
It carries, P7 and P8 are cross-coupled positive feedback；When ON end signal increases, due to common-source stage amplifier characteristic, Vout end signal meeting
It reduces, due to the characteristic of PMOS tube, P8 can make VP point (the i.e. cathode of the grid of P7, the drain electrode of P8, the drain electrode of N14 and R5
Tie point) signal will increase, and due to the effect of P7, Vout end signal can be made lower, have the function of positive feedback, therefore can be with
Speed is compared in increase；Conversely, Vout end signal is more quickly increased when ON end signal reduces.Similarly, when OP end signal
When increase, due to common-source stage amplifier characteristic, VP end signal can be reduced, and due to the characteristic of PMOS tube, P7 can make the end Vout believe
Number increase；Conversely, due to common-source stage amplifier characteristic, VP end signal will increase, due to PMOS tube when OP end signal is reduced
Characteristic, P7 can make the reduction of Vout end signal.The end VP and Vout end signal influence each other, and increase the speed of comparator.
It is designed and emulates, Fig. 7 using speed and precision of the dongbu45V technique to the voltage comparator of the present embodiment
The voltage comparator of the embodiment of the present invention is shown at 60 DEG C, inputs 50MHz frequency, Transient when input difference is 50mV
Figure；Fig. 8 show the voltage comparator of the embodiment of the present invention at 150 DEG C, inputs 50MHz frequency, wink when input difference is 50mV
State analogous diagram；Fig. 7 and Fig. 8 includes the voltage of the voltage positive input VIP voltage oscillogram of voltage comparator, voltage comparator
Negative input VIN voltage waveform diagram and output end vo ut voltage oscillogram, simulation result show at 60 DEG C and 150 DEG C, than
Speed compared with device is greater than 50MHz, and the precision of comparator is less than 50mV；The simulation result illustrates that the above measure improves voltage comparator
The validity of speed and precision, and to the validity that high temperature compensates.
The above is only the preferred embodiment of the present invention, it is noted that above-mentioned preferred embodiment is not construed as pair
Limitation of the invention, for those skilled in the art, without departing from the spirit and scope of the present invention, also
Several improvements and modifications can be made, these modifications and embellishments should also be considered as the scope of protection of the present invention, here no longer with implementation
Example repeats, and protection scope of the present invention should be defined by the scope defined by the claims..
In addition, all relationships such as " electrically connecting " and " connection " being related in patent application document, not singly refer to structure
Part directly connects, and referring to can be according to specific implementation situation, and by adding or reducing couple auxiliary, Lai Zucheng more preferably couples knot
Structure, the place for being clearly intended merely to emphasize this meaning with the place of " electrically connecting ", but use " connection " being not precluded etc. in the present invention
Also has such meaning.
Claims (4)
1. a kind of voltage comparator, it is characterised in that: including the PTAT current source, differential gain stage and output sequentially electrically connected
Grade and voltage positive input VIP, voltage negative input VIN, power end VCC, ground terminal VSS and output end vo ut；
The positive feeder ear of PTAT current source, the positive feeder ear of differential gain stage, output stage positive feeder ear be connected to power end
VCC；The negative feeder ear of PTAT current source, the negative feeder ear of differential gain stage, output stage negative feeder ear be connected to ground terminal
VSS；The positive input terminal of voltage positive input VIP connection differential gain stage, voltage negative input VIN connection differential gain stage
Negative input end, PTAT current source output end connection differential gain stage bias current inputs, differential gain stage it is just defeated
Outlet connect output stage positive input terminal, differential gain stage negative output terminal connection output stage negative input end, output stage it is defeated
Outlet connects output end vo ut；
PTAT current source, the benchmark directlyed proportional to the ratio between resistance generation to temperature using the difference of the gate source voltage difference of two metal-oxide-semiconductors
Electric current inhibits influence of the high temperature to comparator performance for providing current offset for differential gain stage；
Differential gain stage, including Folded-cascode amplifier and biasing circuit with negative resistance load；Folding with negative resistance load
Stacked common source and common grid amplifier, Foldable cascade structure are used to further increase gain for improving gain, negative resistance load,
Biasing circuit is used to provide DC offset voltage for differential gain stage；
Output stage, using the common source circuit for having cross-coupled positive feedback, for increasing the speed of comparator.
2. voltage comparator according to claim 1, it is characterised in that: the PTAT current source include NMOS tube N1~
N4, PMOS tube P1~P3 and resistance R1；The source electrode of PMOS tube P1~P3 is electrically coupled to power end VCC；The grid of PMOS tube P1~P3
Pole electrically connects, and is electrically coupled to the drain electrode of PMOS tube P2 and NMOS tube N2 simultaneously；The drain electrode of PMOS tube P1, the N1 of NMOS tube grid
The anode of pole and resistance R1 electrically connect；The drain electrode of cathode, NMOS tube N1 of resistance R1 and the grid of NMOS tube N2 electrically connect；PMOS
The drain electrode of pipe P3, the drain electrode of the grid and N4 of NMOS tube N4 electrically connect；The drain electrode of the grid, NMOS tube N3 of NMOS tube N3 and NMOS
The source electrode of pipe N4 electrically connects, and tie point is the output end of PTAT current source；The source electrode of NMOS tube N1~N3 is electrically coupled to ground terminal
VSS。
3. voltage comparator according to claim 1, it is characterised in that: the differential gain stage include NMOS tube N5~
N13, PMOS tube P4~P6, resistance R2~R4 and capacitor C1~C2；Wherein, NMOS tube N5~N12, PMOS tube P4~P5, resistance
R2~R3 and capacitor C1 constitutes the Folded-cascode amplifier with negative resistance load, NMOS tube N13, PMOS tube P6, resistance R4
Biasing circuit is constituted with capacitor C2；The anode of resistance R2~R4 and the top crown of capacitor C2 are electrically coupled to power end VCC；Resistance R2
Cathode, the drain electrode of NMOS tube N6, the drain electrode of N9, the grid of N10 and PMOS tube P4 source electrode electrically connect；The cathode of resistance R3,
The drain electrode of NMOS tube N7, the drain electrode of N10, the grid of N9 and PMOS tube P5 source electrode electrically connect；The grid of NMOS tube N6 electrically connects
To voltage negative input VIN；The grid and voltage positive input VIP of NMOS tube N7 electrically connects；The source of NMOS tube N6~N7
The drain electrode of pole and NMOS tube N5 electrically connects；The upper pole of the grid of NMOS tube N5, the grid of N8, the grid of N11~13 and capacitor C1
Plate electrically connects, and tie point is the bias current inputs of differential gain stage；The leakage of the source electrode and NMOS tube N8 of NMOS tube N9~N10
Pole electrically connects；The grid of PMOS tube P4~P5, the grid of P6, the drain electrode of P6, the drain electrode of NMOS tube N13 and capacitor C2 bottom crown
It electrically connects；The cathode of resistance R4 and the source electrode of PMOS tube P6 electrically connect；The drain electrode of PMOS tube P4 and the drain electrode Electricity Federation of NMOS tube N11
It connects, tie point is the negative output terminal of differential gain stage；The drain electrode of PMOS tube P5 and the drain electrode of NOMS pipe N12 electrically connect, tie point
For the positive output end of differential gain stage；The source electrode of NMOS tube N5, the source electrode of N8, the source electrode of N11~N13 and capacitor C1 bottom crown
It is electrically coupled to ground terminal VSS.
4. voltage comparator according to claim 1, it is characterised in that: the output stage include NMOS tube N14~
N15, PMOS tube P7~P8 and resistance R5~R6；Wherein NMOS tube N14~N15, PMOS tube P7~P8 and resistance R5~R6 are constituted
The output circuit of positive feedback structure；The source electrode of PMOS tube P7~P8 and the anode of resistance R5~R6 are electrically coupled to power end VCC；
The grid of PMOS tube P7, the drain electrode of PMOS tube P8, the drain electrode of NMOS tube N14 and resistance R5 cathode electrically connect；NMOS tube N14's
Grid is the positive input terminal of output stage；The drain electrode of PMOS tube P7, the grid of PMOS tube P8, the drain electrode of NMOS tube N15 and resistance R6
Cathode electrically connect, and be electrically coupled to output end vo ut simultaneously；The grid of NMOS tube N15 is the negative output terminal of output stage；NMOS
The source electrode of pipe N14~N15 is electrically coupled to ground terminal VSS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910438624.4A CN110247645B (en) | 2019-05-24 | 2019-05-24 | Voltage comparator |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910438624.4A CN110247645B (en) | 2019-05-24 | 2019-05-24 | Voltage comparator |
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| CN110247645A true CN110247645A (en) | 2019-09-17 |
| CN110247645B CN110247645B (en) | 2023-06-06 |
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|---|---|---|---|
| CN201910438624.4A Active CN110247645B (en) | 2019-05-24 | 2019-05-24 | Voltage comparator |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111510090A (en) * | 2020-05-19 | 2020-08-07 | 成都微光集电科技有限公司 | Operational amplifier with high voltage slew rate and wide output range |
| CN113489474A (en) * | 2021-08-19 | 2021-10-08 | 曹先国 | Comparator and electronic equipment |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111510090A (en) * | 2020-05-19 | 2020-08-07 | 成都微光集电科技有限公司 | Operational amplifier with high voltage slew rate and wide output range |
| CN111510090B (en) * | 2020-05-19 | 2023-03-31 | 成都微光集电科技有限公司 | Operational amplifier with high voltage slew rate and wide output range |
| CN113489474A (en) * | 2021-08-19 | 2021-10-08 | 曹先国 | Comparator and electronic equipment |
| CN113489474B (en) * | 2021-08-19 | 2024-02-09 | 曹先国 | A comparator and electronic device |
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| CN110247645B (en) | 2023-06-06 |
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