CN114495800B

CN114495800B - Display panel driving method and display device

Info

Publication number: CN114495800B
Application number: CN202210217141.3A
Authority: CN
Inventors: 冯博; 杨炜帆; 刘磊; 林金楠; 侯清娜; 魏重光; 王琳琳
Original assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Beijing BOE Display Technology Co Ltd
Priority date: 2022-03-07
Filing date: 2022-03-07
Publication date: 2023-12-26
Anticipated expiration: 2042-03-07
Also published as: CN114495800A

Abstract

The embodiment of the disclosure discloses a driving method of a display panel and a display device, comprising the following steps: acquiring display data of a current display frame; determining a voltage difference value between target data voltages corresponding to sub-pixels electrically coupled to the same data line and to every two adjacent gate lines according to the display data; judging whether absolute values of all voltage difference values corresponding to sub-pixels electrically coupled with at least one data line are not smaller than a set threshold value; if yes, inputting a first control pulse signal to the grid driving circuit, loading a first grid scanning signal to the grid line, inputting display data to the source driving circuit, and loading data voltages to the data line so as to charge each sub-pixel with corresponding data voltages; if not, a second control pulse signal is input to the gate driving circuit, a second gate scanning signal is loaded to the gate line, display data is input to the source driving circuit, and data voltages are loaded to the data lines so that each sub-pixel is charged with the corresponding data voltage.

Description

Display panel driving method and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a driving method of a display panel and a display device.

Background

In displays such as liquid crystal displays (Liquid Crystal Display, LCDs) and Organic Light-Emitting Diode (OLED) displays, a plurality of pixel cells are generally included. Each pixel unit may include: red, green, and blue sub-pixels. The color image is displayed by mixing the colors to be displayed by controlling the brightness corresponding to each sub-pixel.

Disclosure of Invention

The driving method of the display panel provided by the embodiment of the disclosure comprises the following steps:

acquiring display data of a current display frame;

determining a voltage difference value between target data voltages corresponding to sub-pixels electrically coupled to the same data line and to every two adjacent gate lines according to the display data;

judging whether absolute values of all voltage difference values corresponding to at least one sub-pixel electrically coupled with the data line are not smaller than a set threshold value;

if yes, inputting a first control pulse signal to a grid driving circuit in the display panel, loading a first grid scanning signal to the grid line, inputting the display data to a source driving circuit in the display panel, and loading a data voltage to the data line so as to charge each sub-pixel in the display panel with the corresponding data voltage;

If not, inputting a second control pulse signal to the grid driving circuit, loading a second grid scanning signal to the grid line, inputting the display data to the source driving circuit, and loading a data voltage to the data line so as to charge each sub-pixel in the display panel with a corresponding data voltage;

the duration of one effective pulse of the first gate scanning signal is smaller than the duration of one effective pulse of the second gate scanning signal.

In some examples, the active pulses of the first gate scan signals loaded by two adjacent gate lines do not have overlapping times; the active pulses of the second gate scan signals loaded by at least two adjacent gate lines have overlapping times.

In some examples, the second gate scan signal loaded on each of the gate lines has one active pulse, and there is an overlap time of the active pulses of the second gate scan signals loaded on adjacent K gate lines; wherein K is an integer and K is more than or equal to 2;

when K is even, the number of effective pulses of the first grid scanning signals loaded on each grid line is K/2;

when K is an odd number, the number of effective pulses of the first gate scan signal loaded on each gate line is (k+1)/2.

In some examples, the first gate scan signal has a sustain period of one active pulse of tw1, and the second gate scan signal has a sustain period of one active pulse of tw2, tw1=tw2/K.

In some examples, each subpixel to which the gate line is electrically coupled inputs a data voltage corresponding to the display data when the first gate scan signal loaded by each of the gate lines is at a last active pulse.

In some examples, when the first gate scan signal has a plurality of active pulses, each sub-pixel to which the gate lines are electrically coupled charges a precharge voltage when the first gate scan signal loaded by each of the gate lines is in an active pulse other than a last active pulse.

In some examples, when there is an overlap time of a second gate scan signal loaded on an adjacent K gate line, a data voltage corresponding to the display data is charged to a sub-pixel to which the K gate line is electrically coupled after the overlap time and during a time in which the second gate scan signal is loaded on the K gate line, and a precharge voltage is charged to the sub-pixel to which the K gate line is electrically coupled during the overlap time.

In some examples, the first control pulse signal includes a first clock signal having a first target period and a second clock signal having a second target period, and the first clock signal and the second clock signal alternate;

the second control pulse signal includes a third clock signal having a first reference period;

the first target period and the second target period are both smaller than the first reference period.

In some examples, the first target period, the second target period, and the first reference period satisfy the following formula;

Tz1＝Tm1+Tm2；

wherein Tm1 represents the first target period, tm2 represents the second target period, and Tz1 represents the first reference period.

In some examples, the duty cycle of the first clock signal is 50%, the duty cycle of the second clock signal is 25%, and the duty cycle of the third clock signal is 50%.

In some examples, the first control pulse signal includes a fourth clock signal having a third target period, and the second control pulse signal includes a fifth clock signal having a second reference period;

the third target period is smaller than the second reference period.

In some examples, the third target period and the second reference period satisfy the following formula when there is an overlap time of the second gate scan signals loaded by the adjacent K gate lines;

Tm3＝K*Tz2；

wherein Tz2 represents the second reference period, tm3 represents the third target period, K is an integer and K is more than or equal to 2.

The display device provided by the embodiment of the disclosure comprises:

a display panel including a gate driving circuit and a source driving circuit;

a timing controller configured to acquire display data of a current display frame; determining a voltage difference value between target data voltages corresponding to sub-pixels electrically coupled to the same data line and to every two adjacent gate lines according to the display data; judging whether absolute values of all voltage difference values corresponding to at least one sub-pixel electrically coupled with the data line are not smaller than a set threshold value; if yes, inputting a first control pulse signal to the grid driving circuit, and inputting the display data to the source driving circuit; if not, inputting a second control pulse signal to the grid driving circuit and inputting the display data to the source driving circuit;

the grid driving circuit is configured to load a first grid scanning signal to the grid line according to the received first control pulse signal; loading a second grid scanning signal to the grid line according to the received second control pulse signal;

The source driving circuit is configured to load a data voltage to the data line according to the received display data, so that each sub-pixel in the display panel is charged with the corresponding data voltage.

In some examples, the timing controller includes:

an acquisition unit configured to acquire display data of a current display frame;

a mode detection function unit configured to determine a voltage difference between target data voltages corresponding to sub-pixels electrically coupled to the same data line and to every two adjacent gate lines according to the display data; judging whether all voltage difference values corresponding to at least one sub-pixel electrically coupled with the data line meet a set range; if yes, inputting a first control pulse signal to the grid driving circuit, and inputting the display data to the source driving circuit; if not, a second control pulse signal is input to the gate driving circuit, and the display data is input to the source driving circuit.

In some examples, the display panel includes:

a plurality of sub-pixels; wherein the plurality of sub-pixels are divided into a plurality of sub-pixel groups; each sub-pixel group comprises two adjacent sub-pixels in the same row;

A plurality of gate lines; wherein each sub-pixel row corresponds to two gate lines; one subpixel of the subpixel group is electrically coupled to one of the corresponding two gate lines, and the other subpixel is electrically coupled to the other of the corresponding two gate lines;

a plurality of data lines; and one data line is electrically coupled to the odd numbered rows of the one row of the sub-pixel groups arranged between the two data lines, and the other data line is electrically coupled to the even numbered rows of the one row of the sub-pixel groups arranged between the two data lines.

Drawings

Fig. 1 is a schematic view of some structures of a display device in an embodiment of the disclosure;

FIG. 2a is a schematic diagram of some configurations of a display panel in an embodiment of the disclosure;

FIG. 2b is a schematic view of other structures of a display panel according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of some structures of a gate driving circuit according to an embodiment of the disclosure;

FIG. 4 is a timing diagram of some signals in an embodiment of the present disclosure;

FIG. 5 is a timing diagram of other signals in an embodiment of the present disclosure;

FIG. 6 is some flow charts of a driving method in an embodiment of the present disclosure;

FIG. 7 is a timing diagram of further signals in an embodiment of the present disclosure;

FIG. 8 is a timing diagram of further signals in an embodiment of the present disclosure;

FIG. 9 is a timing diagram of further signals in an embodiment of the present disclosure;

FIG. 10 is a timing diagram of yet other signals in an embodiment of the present disclosure;

FIG. 11 is a timing diagram of yet other signals in an embodiment of the present disclosure;

fig. 12 is a timing diagram of further signals in an embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. And embodiments of the disclosure and features of embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "coupled" or "connected," and the like, are not limited to physical or mechanical coupling, but may include electrical coupling, whether direct or indirect.

It should be noted that the dimensions and shapes of the various figures in the drawings do not reflect true proportions, and are intended to illustrate the present disclosure only. And the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

In some embodiments of the present disclosure, as shown in fig. 1, a display device may include a display panel 100, a timing controller 200. The display panel 100 may include a plurality of pixel units arranged in an array. Illustratively, each pixel cell includes a plurality of differently colored sub-pixels. A transistor and a pixel electrode may be included in each sub-pixel. For example, the pixel unit may include red, green, and blue sub-pixels, so that color mixing can be performed by red, green, and blue to realize color display. Alternatively, the pixel unit may include red, green, blue and white sub-pixels, so that color mixing can be performed by red, green, blue and white to realize color display. Of course, in practical application, the emission color of the sub-pixels in the pixel unit may be designed and determined according to the practical application environment, which is not limited herein. The following description will take a pixel unit including red, green and blue sub-pixels as an example.

In some embodiments of the present disclosure, as shown in fig. 1, the display panel 100 may further include a plurality of gate lines GA, a plurality of data lines DA, a gate driving circuit 110, and a source driving circuit 120. The gate driving circuits 110 are respectively coupled to the gate lines GA, and the source driving circuits 120 are respectively coupled to the data lines DA. And, one sub-pixel row may be made to correspond to at least one gate line, the gate of the transistor is electrically coupled to the corresponding gate line, the source of the transistor is electrically coupled to the corresponding data line, and the drain of the transistor is electrically coupled to the pixel electrode. For example, the timing controller 200 may acquire display data of a picture to be displayed in a current display frame, and the timing controller 200 may input a control signal to the gate driving circuit 110, so that the gate driving circuit 110 may output a gate scan signal to each gate line GA according to the input control signal, thereby driving each gate line GA to control the transistors in the coupled sub-pixels to be turned on. And, the timing controller 200 inputs the acquired display data to the source driving circuit 120, so that the source driving circuit 120 can input a data voltage to the coupled data line DA according to the input display data, thereby inputting the voltage on the data line DA to the sub-pixels through the turned-on transistors to charge the sub-pixels, and further charging each sub-pixel with a corresponding data voltage, thereby realizing a picture display function.

For example, as shown in fig. 2a, each subpixel row may correspond to a gate line, and, for example, a column of subpixels, the subpixels in the odd-numbered row are coupled to the data lines located at the left side of the column of subpixels, and the subpixels in the even-numbered row are coupled to the data lines located at the right side of the column of subpixels. Alternatively, the odd-numbered row sub-pixels of the column sub-pixels are coupled to the data lines on the right side of the column sub-pixels, and the even-numbered row sub-pixels are coupled to the data lines on the left side of the column sub-pixels. For example, the first sub-pixel row corresponds to the gate line GA1, the second sub-pixel row corresponds to the gate line GA2, the third sub-pixel row corresponds to the gate line GA3, the fourth sub-pixel row corresponds to the gate line GA4, the fifth sub-pixel row corresponds to the gate line GA5, and the sixth sub-pixel row corresponds to the gate line GA6. The red sub-pixel R11, the red sub-pixel R31 and the red sub-pixel R51 are coupled to the data line DA1, and the red sub-pixel R21, the red sub-pixel R41 and the red sub-pixel R61 are coupled to the data line DA2. The green sub-pixels G11, G31 and G51 are coupled to the data line DA3, and the green sub-pixels G21, G41 and G61 are coupled to the data line DA4. The rest is the same and is not described in detail herein.

For example, as shown in fig. 2b, each sub-pixel row may correspond to two gate lines, so that the pixel array in the present disclosure may be arranged in a double gate structure to reduce half of the data lines (i.e., including the data lines between two adjacent columns of pixels, and not including the data lines between two adjacent columns of pixels). For example, the first sub-pixel row corresponds to the gate lines GA1, GA2, the second sub-pixel row corresponds to the gate lines GA3, GA4, the third sub-pixel row corresponds to the gate lines GA5, GA6, the fourth sub-pixel row corresponds to the gate lines GA7, GA8, the fifth sub-pixel row corresponds to the gate lines GA9, GA10, and the sixth sub-pixel row corresponds to the gate lines GA11, GA12.

In the embodiment of the present disclosure, a plurality of sub-pixels in a display panel may be divided into a plurality of sub-pixel groups, each of which may include two adjacent sub-pixels in the same row. And, one sub-pixel of the sub-pixel group is electrically coupled to one of the corresponding two gate lines, and the other sub-pixel is electrically coupled to the other of the corresponding two gate lines. Illustratively, as shown in fig. 2b, in the first sub-pixel row, the red sub-pixel R11 and the green sub-pixel G11 are a sub-pixel group, the red sub-pixel R11 is electrically coupled to the gate line GA1, and the green sub-pixel G11 is electrically coupled to the gate line GA2. The blue sub-pixel B11 and the red sub-pixel R12 are a sub-pixel group, the blue sub-pixel B11 is electrically coupled to the gate line GA2, and the red sub-pixel R12 is electrically coupled to the gate line GA1. The green sub-pixel G12 and the blue sub-pixel B12 are a sub-pixel group, the green sub-pixel G12 is electrically coupled to the gate line GA2, and the blue sub-pixel B12 is electrically coupled to the gate line GA1. The red sub-pixel R13 and the green sub-pixel G13 are a sub-pixel group, the red sub-pixel R13 is electrically coupled to the gate line GA1, and the green sub-pixel G13 is electrically coupled to the gate line GA2. The blue sub-pixel B13 and the red sub-pixel R14 are a sub-pixel group, the blue sub-pixel B13 is electrically coupled to the gate line GA2, and the red sub-pixel R14 is electrically coupled to the gate line GA1. The green sub-pixel G14 and the blue sub-pixel B14 are one sub-pixel group. The green sub-pixel G14 is electrically coupled to the gate line GA2, and the blue sub-pixel B14 is electrically coupled to the gate line GA1.

In the second sub-pixel row, the red sub-pixel R21 and the green sub-pixel G21 are a sub-pixel group, the red sub-pixel R21 is electrically coupled to the gate line GA3, and the green sub-pixel G21 is electrically coupled to the gate line GA4. The blue sub-pixel B21 and the red sub-pixel R22 are a sub-pixel group, the blue sub-pixel B21 is electrically coupled to the gate line GA4, and the red sub-pixel R22 is electrically coupled to the gate line GA3. The green sub-pixel G22 and the blue sub-pixel B22 are a sub-pixel group, the green sub-pixel G22 is electrically coupled to the gate line GA4, and the blue sub-pixel B22 is electrically coupled to the gate line GA3. The red sub-pixel R23 and the green sub-pixel G23 are a sub-pixel group, the red sub-pixel R23 is electrically coupled to the gate line GA3, and the green sub-pixel G23 is electrically coupled to the gate line GA4. The blue sub-pixel B23 and the red sub-pixel R24 are a sub-pixel group, the blue sub-pixel B23 is electrically coupled to the gate line GA4, and the red sub-pixel R24 is electrically coupled to the gate line GA3. The green sub-pixel G24 and the blue sub-pixel B24 are one sub-pixel group. The green sub-pixel G24 is electrically coupled to the gate line GA4, and the blue sub-pixel B24 is electrically coupled to the gate line GA3. The remaining sub-pixel rows are divided into sub-pixel groups in the same manner, and are not described herein.

In the embodiment of the disclosure, a column of sub-pixel groups may be disposed between every two adjacent data lines, and for the two adjacent data lines, one data line is coupled to an odd-numbered row of the column of sub-pixel groups disposed between the two data lines, and the other data line is coupled to an even-numbered row of the column of sub-pixel groups disposed between the two data lines. It can also be said that two adjacent columns of subpixels are disposed between two adjacent data lines. This can reduce power consumption of the source driving circuit. Illustratively, as shown in fig. 2b, a first column of sub-pixel group LX1 is disposed between data lines DA1 and DA2, a second column of sub-pixel group LX2 is disposed between data lines DA2 and DA3, a third column of sub-pixel group LX3 is disposed between data lines DA3 and DA4, a fourth column of sub-pixel group LX4 is disposed between data lines DA4 and DA5, a fifth column of sub-pixel group LX5 is disposed between data lines DA5 and DA6, and a sixth column of sub-pixel group LX6 is disposed between data lines DA6 and DA 7.

For the first column subpixel group LX1: the data line DA1 is electrically coupled to the odd columns (i.e., the red sub-pixel R11, the green sub-pixel G11, the red sub-pixel R31, the green sub-pixel G31, the red sub-pixel R51, the green sub-pixel G51) in the fifth column of the first row sub-pixel group LX 1. The data line DA2 is electrically coupled to the even columns (i.e., the red sub-pixel R21 and the green sub-pixel G21 in the second column, the red sub-pixel R41 and the green sub-pixel G41 in the fourth column, and the red sub-pixel R61 and the green sub-pixel G61 in the sixth column) in the first column sub-pixel group LX 1.

For the second column subpixel group LX2: the data line DA2 is electrically coupled to the odd-numbered rows (i.e., the blue sub-pixel B11, the red sub-pixel R12, the blue sub-pixel B31, the red sub-pixel R32, the blue sub-pixel B51, the red sub-pixel R52) in the second column sub-pixel group LX 2. The data line DA3 is electrically coupled to the even-numbered rows (i.e., the blue sub-pixel B21, the red sub-pixel R22, the blue sub-pixel B41, the red sub-pixel R42, the blue sub-pixel B61, the red sub-pixel R62) in the second column sub-pixel group LX 2.

The other sub-pixel groups are similarly coupled to the data lines, and are not described herein.

It should be noted that the display panel in the embodiments of the present disclosure may be a liquid crystal display panel. Illustratively, the liquid crystal display panel generally includes upper and lower substrates of a pair of cells, and liquid crystal molecules encapsulated between the upper and lower substrates. When a picture is displayed, since a voltage difference exists between the data voltage applied to the pixel electrode of each sub-pixel and the common electrode voltage applied to the common electrode, the voltage difference can form an electric field, so that the liquid crystal molecules are deflected by the electric field. The different electric fields with different intensities lead the deflection degrees of the liquid crystal molecules to be different, so that the transmittance of the sub-pixels is different, the sub-pixels realize the brightness with different gray scales, and further the picture display is realized. Of course, the display panel in the embodiments of the present disclosure may be an OLED display panel, which is not limited herein.

In some examples, the gate driving circuit may include a plurality of shift registers. For example, as shown in fig. 3, the 1 st to nth shift registers: SR (1), SR (2) … SR (N-1), SR (N) … SR (N-1) and SR (N) (N shift registers in total, N is greater than or equal to 1 and less than or equal to N, N is an integer), and SR (1) to SR (12) are taken as examples in FIG. 3. Illustratively, the signal timing diagram corresponding to the gate driving circuit shown in fig. 3 is shown in fig. 4. Where CK1 represents the clock signal transmitted on the clock signal line CK1, CK2 represents the clock signal transmitted on the clock signal line CK2, CK3 represents the clock signal transmitted on the clock signal line CK3, CK4 represents the clock signal transmitted on the clock signal line CK4, CK5 represents the clock signal transmitted on the clock signal line CK5, and CK6 represents the clock signal transmitted on the clock signal line CK 6. The signal ga1 represents the gate scan signal outputted from the output signal terminal GO of the 1 st stage shift register SR (1). The signal ga2 represents the gate scan signal outputted from the output signal terminal GO of the 2 nd stage shift register SR (2). The signal ga3 represents the gate scan signal outputted from the output signal terminal GO of the 3 rd stage shift register SR (3). The … … signal ga12 represents the gate scan signal outputted from the output signal terminal GO of the 12 th shift register SR (12).

The 1 st stage shift register SR (1) outputs the first high level of the clock signal ck1 through the output signal terminal GO to generate the high level in the signal ga 1. The shift register SR (2) of stage 2 outputs the first high level of the clock signal ck2 through the output signal terminal GO to generate the high level in the signal ga 2. The 3 rd stage shift register SR (3) outputs the first high level of the clock signal ck1 through the output signal terminal GO to generate the high level in the signal ga 3. … … the 12 th shift register SR (12) outputs the first high level of the clock signal ck12 through the output signal terminal GO to generate the high level in the signal ga 12. That is, the pulse corresponding to the high level of the clock signal may be its active pulse, and the pulse corresponding to the low level may be its inactive pulse. Of course, when the shift register outputs the low level of the clock signal through the output signal terminal GO to generate the low level signal for controlling the on of the transistor in the signal, the pulse corresponding to the low level of the clock signal may be used as the active pulse, and the pulse corresponding to the high level may be used as the inactive pulse.

In the embodiments of the present disclosure, the configuration of the gate driving circuit is merely described as an example. In practical applications, the structure of the gate driving circuit may also adopt other realizable structures, which are not limited herein.

Gray scale, which generally divides the brightness change between darkest and brightest into several parts, is convenient for screen brightness control. For example, an image to be displayed is composed of three colors of red, green, and blue, each of which may exhibit a different brightness level, and red, green, and blue of different brightness levels may be combined to form different colors. For example, when the gray scale number of the liquid crystal display panel is 6 bits, the three colors of red, green and blue respectively have 64 (i.e. 2 ⁶ ) The 64 gray levels are respectively 0 to 63. The gray scale number of the LCD panel is 8 bits, and the three colors of red, green and blue respectively have 256 (i.e. 2 ⁸ ) The 256 gray levels are respectively 0 to 255. The gray scale of the LCD panel is 10 bits, and the three colors of red, green and blue respectively have 1024 (i.e. 2 ¹⁰ ) The 1024 gray scales are respectively 0 to 1023. The liquid crystal display panel has a gray scale number of 12 bits, and the three colors of red, green and blue respectively have 4096 (i.e. 2 ¹² ) The 4096 gray scales are respectively 0 to 4093.

Taking one subpixel as an example, vcom represents the common electrode voltage. When the data voltage input in the pixel electrode of the sub-pixel is greater than the common electrode voltage Vcom, the liquid crystal molecules at the sub-pixel may be made positive, and the polarity corresponding to the data voltage in the sub-pixel may be made positive. When the data voltage input to the pixel electrode of the sub-pixel is smaller than the common electrode voltage Vcom, the liquid crystal molecules at the sub-pixel may be made negative, and the polarity corresponding to the data voltage in the sub-pixel may be negative. For example, the common electrode voltage may be 8.3V, and if a data voltage of 8.8V to 16V is inputted to the pixel electrode of the sub-pixel SPX, the liquid crystal molecules at the sub-pixel SPX may be positive, and the data voltage of 8.8V to 16V is a data voltage corresponding to positive. When a data voltage of 0.6V to 7.8V is input to the pixel electrode of the subpixel SPX, the liquid crystal molecules at the subpixel SPX can be made negative, and the data voltage of 0.6V to 7.8V corresponds to the data voltage of the negative polarity. Taking an example of an 8bit 0-255 gray scale, if a 16V data voltage is input to the pixel electrode of the sub-pixel SPX, the sub-pixel SPX may realize the brightness of the maximum gray scale value (i.e., 255 gray scale values) using a positive polarity data voltage. When a data voltage of 0.6V is input to the pixel electrode of the sub-pixel SPX, the sub-pixel SPX can realize the brightness of the maximum gray scale value (i.e., 255 gray scale values) using the data voltage of negative polarity. It should be noted that, a voltage difference may be between the data voltage of 0 gray scale value and the common electrode voltage, for example, the common electrode voltage is 8.3V, the data voltage of positive polarity corresponding to 0 gray scale value may be 8.8V, and the data voltage of negative polarity corresponding to 0 gray scale value may be 7.8V. Therefore, the display panel can realize a frame turnover mode, a column turnover mode, a row turnover mode, a point turnover mode and the like according to the corresponding polarity of the control sub-pixels.

Of course, the data voltage of 0 gray scale value and the common electrode voltage may be the same. In practical application, the determination may be performed according to the needs of practical application, which is not limited herein.

When the display panel displays a picture, there is a possibility that the picture may be displayed poorly due to the difference in charging rates of the sub-pixels. For example, when a display panel displays a heavy-duty screen (for example, a screen displayed when the gray-scale values of two adjacent lines differ greatly, for example, an 8bit screen may be a screen displayed when the gray-scale values of two adjacent lines differ by 127 gray-scale values or more), a serial problem may occur due to the difference in charging rate.

The display panel shown in fig. 2a is taken as an example to display a heavy-duty screen and a column flip. For example, taking the example that the first row of sub-pixels corresponds to 0 gray scale value, the second row of sub-pixels corresponds to 255 gray scale value, the third row of sub-pixels corresponds to 0 gray scale value, the fourth row of sub-pixels corresponds to 255 gray scale value, the fifth row of sub-pixels corresponds to 0 gray scale value, and the sixth row of sub-pixels corresponds to 255 gray scale value, the process of driving the display panel to display the heavy-duty image is as follows in conjunction with the description of fig. 2a and fig. 5. GA1 represents the gate scan signal loaded on the gate line GA1, GA2 represents the gate scan signal loaded on the gate line GA2, GA3 represents the gate scan signal loaded on the gate line GA3, GA4 represents the gate scan signal loaded on the gate line GA4, GA5 represents the gate scan signal loaded on the gate line GA5, and GA6 represents the gate scan signal loaded on the gate line GA 6. Vda2 represents the data voltage applied to the data line DA 2. And, the high level in the signals ga 1-ga 6 may control the transistors in the sub-pixels to be turned on. Taking one display frame F01, the data line DA2, and the subpixel connected to the data line DA2 as an example, when the signal GA1 on the gate line GA1 outputs a high level, the transistor in the green subpixel G11 is turned on. In the data charging stage T11 corresponding to the high level of the signal ga1, the data line DA2 connected to the green subpixel G11 is charged with the data voltage V02 corresponding to the 0 gray scale value, so that the green subpixel G11 inputs the target data voltage V02. And, in the data charge phase T11, the signal GA2 on the gate line GA2 outputs a high level, and the transistor in the red subpixel R21 is turned on. The data voltage V02 is simultaneously input into the red subpixel R21 as a precharge voltage to precharge the red subpixel R21. And, in the data charge phase T11, the signal GA3 on the gate line GA3 outputs a high level, and the transistor in the green subpixel G31 is turned on. The data voltage V02 is simultaneously input to the green sub-pixel G31 as a precharge voltage to precharge the green sub-pixel G31.

In the data charging period T12 corresponding to the high level of the signal ga2, the data line DA2 connected to the red subpixel R21 is charged with the data voltage V01 corresponding to the 255 gray scale value, so that the red subpixel R21 is charged with the target data voltage V01. And, in the data charge phase T12, the signal GA3 on the gate line GA3 outputs a high level, and the transistor in the green subpixel G31 is turned on. The data voltage V01 is simultaneously input to the green sub-pixel G31 as a precharge voltage to precharge the green sub-pixel G31. And, in the data charge phase T12, the signal GA4 on the gate line GA4 outputs a high level, and the transistor in the red subpixel R41 is turned on. The data voltage V01 is simultaneously input into the red subpixel R41 as a precharge voltage to precharge the red subpixel R41.

In the data charging period T13 corresponding to the high level of the signal ga3, the data line DA2 connected to the green subpixel G31 is charged with the data voltage V02 corresponding to the 0 gray scale value, so that the green subpixel G31 is charged with the target data voltage V02. And, in the data charging stage T13, the signal GA4 on the gate line GA4 outputs a high level, and the transistor in the red subpixel R41 is turned on. The data voltage V02 is simultaneously input into the red subpixel R41 as a precharge voltage to precharge the red subpixel R41. And, in the data charging stage T13, the signal GA5 on the gate line GA5 outputs a high level, and the transistor in the green subpixel G51 is turned on. The data voltage V02 is simultaneously input to the green sub-pixel G51 as a precharge voltage to precharge the green sub-pixel G51.

In the data charging period T14 corresponding to the high level of the signal ga4, the data line DA2 connected to the red subpixel R41 is charged with the data voltage V01 corresponding to the 255 gray scale value, so that the red subpixel R41 is charged with the target data voltage V01. And, in the data charging stage T14, the signal GA5 on the gate line GA5 outputs a high level, and the transistor in the green subpixel G51 is turned on. The data voltage V01 is simultaneously input to the green sub-pixel G51 as a precharge voltage to precharge the green sub-pixel G51. And, in the data charging stage T14, the signal GA6 on the gate line GA6 outputs a high level, and the transistor in the red subpixel R61 is turned on. The data voltage V01 is simultaneously input into the red subpixel R61 as a precharge voltage to precharge the red subpixel R61.

In the data charging period T15 corresponding to the high level of the signal ga5, the data line DA2 connected to the green subpixel G51 is charged with the data voltage V02 corresponding to the 0 gray scale value, so that the green subpixel G51 is charged with the target data voltage V02. And, in the data charge phase T15, the signal GA6 on the gate line GA6 outputs a high level, and the transistor in the red subpixel R61 is turned on. The data voltage V02 is simultaneously input into the red subpixel R51 as a precharge voltage to precharge the red subpixel R51. And precharge the next subpixel.

In the data charging period T16 corresponding to the high level of the signal ga6, the data line DA2 connected to the red subpixel R61 is charged with the data voltage V01 corresponding to the 255 gray scale value, so that the red subpixel R61 is charged with the target data voltage V01, and the next subpixel is precharged.

The embodiments of the remaining sub-pixels are analogized in order until the sub-pixels in the entire display panel are completely charged with the data voltages, which is not described herein.

As can be seen from the above description, taking one sub-pixel in the white sub-pixel row (the even sub-pixel row shown in fig. 2 a) as an example, the voltage charged in the sub-pixel is divided into 3 parts: the first part is charged with the data voltage V01 with 255 gray scale values as a pre-charge voltage, the second part is charged with the data voltage V02 with 0 gray scale values as a pre-charge voltage, and the third part is charged with the data voltage V01 with 255 gray scale values as a target data voltage corresponding to display data to be displayed. Taking one subpixel in a black subpixel row (an odd-numbered subpixel row as shown in fig. 2 a) as an example, the voltage charged in the subpixel is divided into 3 parts: the first part is charged with the data voltage V02 with 0 gray scale value as the pre-charge voltage, the second part is charged with the data voltage V01 with 255 gray scale value as the pre-charge voltage, and the third part is charged with the data voltage V02 with 0 gray scale value as the target data voltage corresponding to the display data to be displayed. From the above, it can be seen that the precharge of the first portion is beneficial to actually charge the corresponding charging rate of the target data voltage. The precharge of the second portion is not beneficial to the charging rate corresponding to the actual charging target data voltage, which may cause the charging rate corresponding to the sub-pixel charging target data voltage to be insufficient, thereby causing image quality problems.

Taking the display panel shown in fig. 2b as an example, a blue-green screen is displayed in which the blue sub-pixel and the green sub-pixel are turned on and the red sub-pixel is turned off. Illustratively, the blue and green sub-pixels correspond to 255 gray scale values and the red sub-pixel corresponds to 0 gray scale value. Referring to fig. 2b and fig. 5, when the signal GA1 on the gate line GA1 outputs a high level, the transistor in the red subpixel R12 is turned on. And, in the data charging period T11 corresponding to the high level of the signal ga1, the data voltage V01 corresponding to the 255 gray scale value is applied to the data line DA2, so that the red subpixel R12 inputs the target data voltage V01. And, in the data charge phase T11, the signal GA2 on the gate line GA2 outputs a high level, and the transistor in the blue subpixel B11 is turned on. The data voltage V01 is simultaneously input to the blue sub-pixel B11 as a precharge voltage to precharge the blue sub-pixel B11. And, in the data charge phase T11, the signal GA3 on the gate line GA3 outputs a high level, the transistor in the red subpixel R21 is turned on, and the data voltage V01 is simultaneously input into the red subpixel R21 as a precharge voltage to precharge the red subpixel R21.

In the data charge phase T12 corresponding to the high level of the signal ga2, the data voltage V02 corresponding to the 0 gray scale value is applied to the data line DA2 so that the blue subpixel B11 is charged with the target data voltage V02. And, in the data charge phase T12, the signal GA3 on the gate line GA3 outputs a high level, the transistor in the red subpixel R21 is turned on, and the data voltage V02 is simultaneously input into the red subpixel R21 as a precharge voltage to precharge the red subpixel R21. And, in the data charging stage T12, the signal GA4 on the gate line GA4 outputs a high level, the transistor in the green sub-pixel G21 is turned on, and the data voltage V02 is simultaneously input to the green sub-pixel G21 as a precharge voltage to precharge the green sub-pixel G21.

In the data charging period T13 corresponding to the high level of the signal ga3, the data voltage V01 corresponding to the 255 gray-scale value is applied to the data line DA2 so that the red subpixel R21 charges the target data voltage V01. And, in the data charging stage T13, the signal GA4 on the gate line GA4 outputs a high level, and the transistor in the green subpixel G21 is turned on. The data voltage V01 is simultaneously input to the green sub-pixel G21 as a precharge voltage to precharge the green sub-pixel G21. And, in the data charging stage T13, the signal GA5 on the gate line GA5 outputs a high level, and the transistor in the red subpixel R32 is turned on. The data voltage V01 is simultaneously input into the red subpixel R32 as a precharge voltage to precharge the red subpixel R32.

In the data charging period T14 corresponding to the high level of the signal ga4, the data voltage V02 corresponding to the 0 gray scale value is applied to the data line DA2 so that the green sub-pixel G21 is charged with the target data voltage V02. And, in the data charging period T14, the signal GA5 on the gate line GA5 outputs a high level, and the transistor in the red subpixel R32 is turned on. The data voltage V02 is simultaneously input into the red subpixel R32 as a precharge voltage to precharge the red subpixel R32. And, in the data charge phase T14, the signal GA6 on the gate line GA6 outputs a high level, and the transistor in the blue subpixel B31 is turned on. The data voltage V02 is simultaneously input to the blue sub-pixel B31 as a precharge voltage to precharge the blue sub-pixel B31.

As can be seen from the above description, taking the sub-pixel connected to the data line DA2 as an example, for the sub-pixel inputting the target data voltage corresponding to 255 gray scale values, the voltage charged in the sub-pixel is divided into 3 parts: the first part is charged with the data voltage V01 with 255 gray scale values as a pre-charge voltage, the second part is charged with the data voltage V02 with 0 gray scale values as a pre-charge voltage, and the third part is charged with the data voltage V01 with 255 gray scale values as a target data voltage corresponding to display data to be displayed. For a subpixel to which a target data voltage corresponding to 0 gray scale value is input, the voltage charged in the subpixel is divided into 3 parts: the first part is charged with the data voltage V02 with 0 gray scale value as the pre-charge voltage, the second part is charged with the data voltage V01 with 255 gray scale value as the pre-charge voltage, and the third part is charged with the data voltage V02 with 0 gray scale value as the target data voltage corresponding to the display data to be displayed. From the above, it can be seen that the precharge of the first portion is beneficial to actually charge the corresponding charging rate of the target data voltage. The precharge of the second portion is not beneficial to the charging rate corresponding to the actual charging target data voltage, which may cause the charging rate corresponding to the sub-pixel charging target data voltage to be insufficient, thereby causing image quality problems.

In summary, if the sub-pixels have insufficient charging rate, the image quality of the picture displayed on the display panel is affected. In order to improve the charging rate problem of the sub-pixels, the embodiment of the present disclosure provides a driving method of a display panel, as shown in fig. 6, which may include the steps of:

s100, acquiring display data of a current display frame.

The acquired display data may include digital signal forms of data voltages carrying corresponding gray scale values for each sub-pixel in a one-to-one correspondence, for example. In this way, the gray scale value corresponding to each sub-pixel can be determined according to the display data of each sub-pixel. Thus, the target data voltage corresponding to each sub-pixel can be obtained according to the determined gray scale value.

S200, determining a voltage difference value between target data voltages corresponding to sub-pixels electrically coupled to the same data line and each two adjacent gate lines according to the display data.

For example, the gray scale value corresponding to each sub-pixel may be determined according to the display data of each sub-pixel. Thus, the target data voltage corresponding to each sub-pixel can be obtained according to the determined gray scale value. Taking the sub-pixels connected to the data line DA2 in the display panel shown in fig. 2a as an example, the sub-pixels connected to the data line DA2 are respectively: green subpixel G11, red subpixel R21, green subpixel G31, red subpixel R41, green subpixel G51, and red subpixel R61. The voltage difference between the target data voltage Vmg11 charged to the green subpixel G11 and the target data voltage Vmr21 charged to the red subpixel R21 is: vmg11-Vmr21. The voltage difference between the target data voltage Vmr21 charged to the red subpixel R21 and the target data voltage Vmg31 charged to the green subpixel G31 is: vmr21-Vmg31. The voltage difference between the target data voltage Vmg31 charged to the green subpixel G31 and the target data voltage Vmr41 charged to the red subpixel R41 is: vmg31-Vmr41. The voltage difference between the target data voltage Vmr41 charged to the red subpixel R41 and the target data voltage Vmg51 charged to the green subpixel G51 is: vmr41-Vmg51. The voltage difference between the target data voltage Vmg51 charged to the green subpixel G51 and the target data voltage Vmr61 charged to the red subpixel R61 is: vmg51-Vmr61. The remaining voltage differences are similarly available and will not be described in detail herein.

S300, judging whether absolute values of all voltage difference values corresponding to the sub-pixels electrically coupled with at least one data line are not smaller than a set threshold value. If yes, go to step S400; if not, step S500 is performed.

For example, the set threshold value may be set to an absolute value of a difference between the target data voltage corresponding to the maximum gray-scale value and the target data voltage corresponding to the minimum gray-scale value among the polarities. For example, taking 8 bits as an example, the set threshold may be set to |V _L+255 -V _L+0 |，V _L+255 Target data voltage (16V, for example) representing positive polarity corresponding to 255 gray scale values, V _L+0 Represents a positive polarity target data voltage (e.g., 8.8V) corresponding to a 0 gray scale value. For example, taking 8 bits as an example, the set threshold may be set to |V _L-255 -V _L-0 |，V _L-255 A target data voltage (e.g., 0.6V) representing a negative polarity corresponding to a 255 gray scale value, V _L-0 Represents a negative polarity target data voltage (e.g., 7.8V) corresponding to a 0 gray scale value.

For example, the set threshold value may be set to an absolute value of a difference between the target data voltage corresponding to the intermediate gray-scale value and the target data voltage corresponding to the minimum gray-scale value among the polarities. For example, taking 8 bits as an example, the set threshold may be set to |V _L+127 -V _L+0 |，V _L+127 Target data voltage (e.g., 12.6V) representing positive polarity corresponding to 127 gray-scale values, V _L+0 Represents a positive polarity target data voltage (e.g., 8.8V) corresponding to a 0 gray scale value. For example, taking 8 bits as an example, the set threshold may be set to |V _L-127 -V _L-0 |，V _L-127 A target data voltage (e.g., 4.0V) representing a negative polarity corresponding to 127 gray-scale values, V _L-0 Represents a negative polarity target data voltage (e.g., 7.8V) corresponding to a 0 gray scale value.

Of course, in practical application, the set threshold may be determined according to the requirement of practical application, which is not limited herein.

S400, inputting a first control pulse signal to a gate driving circuit in the display panel, loading a first gate scanning signal to a gate line, inputting display data to a source driving circuit in the display panel, and loading data voltages to the data lines so as to charge each sub-pixel in the display panel with the corresponding data voltage.

For example, taking the sub-pixel connected to the data line DA2 in the display panel shown in fig. 2a as an example, if the absolute value of Vmg11-Vmr21, the absolute value of Vmr21-Vmg31, the absolute value of Vmg31-Vmr41, the absolute value of Vmr41-Vmg51, and the absolute value of Vmg51-Vmr61 are not less than the set threshold, it may be determined that the precharge voltage of the sub-pixel on the data line DA2 has a great adverse effect on the charging rate of the target data voltage, and the charging rate is insufficient. In order to improve the problem of the insufficient charging rate, a first control pulse signal may be input to the gate driving circuit 110 in the display panel in the current display frame, so that the output signal terminal GO of the gate driving circuit 110 may load the first gate scan signal to each gate line, respectively. In addition, display data is input to the source driving circuit 120 in the display panel in the current display frame, so that the source driving circuit can load data voltages to the data lines according to the received display data, and when the transistors in the sub-pixels are turned on under the control of the effective pulses in the first gate scanning signals, the data voltages loaded on the connected data lines can be charged, so that each sub-pixel in the display panel can be charged with the target data voltages corresponding to the display data.

It should be noted that, when the absolute value of all the voltage differences corresponding to the sub-pixels electrically coupled by the one data line is not less than the set threshold, the operation mode of step S400 may be used to drive the display panel. Alternatively, the operation mode of step S400 may be used to drive the display panel when the absolute value of all voltage differences corresponding to the sub-pixels electrically coupled to two, three, four or more or each data line is not less than the set threshold, which is not limited herein.

S500, inputting a second control pulse signal to the grid driving circuit, loading a second grid scanning signal to the grid line, inputting display data to the source driving circuit, and loading data voltages to the data lines so as to charge each sub-pixel in the display panel with corresponding data voltages.

For example, when the absolute value of all the voltage differences corresponding to at least one data line is not smaller than the set threshold, taking the sub-pixel connected to the data line DA2 in the display panel shown in fig. 2a as an example, the absolute value of Vmg11-Vmr21, the absolute value of Vmr21-Vmg31, the absolute value of Vmg31-Vmr41, the absolute value of Vmr41-Vmg51 and the absolute value of Vmg51-Vmr61 corresponding to the data line DA2 are not smaller than the set threshold, it may be determined that the pre-charge voltage of the sub-pixel on the data line DA2 has a small or no adverse effect on the charging rate of the target data voltage, and the problem of insufficient charging rate does not occur. Therefore, in order to further increase the charging rate of the sub-pixels, as shown in fig. 2a and 7, a second control pulse signal may be input to the gate driving circuit 110 in the display panel in the current display frame, so that the output signal terminal GO of the gate driving circuit 110 may load the second gate scan signals ga1_2 to ga6_2 to each gate line GA1 to GA6, respectively. In addition, display data is input to the source driving circuit 120 in the display panel in the current display frame, so that the source driving circuit can load data voltages to the data lines according to the received display data, and when the transistors in the sub-pixels are turned on under the control of the effective pulses in the second gate scanning signals ga1_2 to ga6_2, the data voltages loaded on the connected data lines can be charged, so that each sub-pixel in the display panel can be charged with the target data voltages corresponding to the display data.

In some embodiments of the present disclosure, a sustain period of one active pulse of the first gate scan signal may be made smaller than a sustain period of one active pulse of the second gate scan signal. For the sub-pixels connected to the same data line (such as DA 2), by making the duration of one effective pulse of the first gate scan signal smaller than that of one effective pulse of the second gate scan signal, two different modes of driving the gate lines can be used to load the gate on signal to each gate line, so that it is possible to determine which mode of the two modes is used for improving the charging rate and improving the display image quality according to whether the charging rate is insufficient in each display frame.

In some embodiments of the present disclosure, the active pulses of the first gate scan signals loaded by two adjacent gate lines may not have overlapping times. Illustratively, the active pulses of the first gate scan signal loaded per two adjacent gate lines do not have overlapping times. Because the effective pulses of the first gate scanning signals loaded by two adjacent gate lines do not have overlapping time, for the sub-pixels connected to the same data line, the target data voltage input by the sub-pixel connected with the last gate line in the two gate lines can be avoided, and the target data voltage is input into the sub-pixel connected with the next gate line as the pre-charge voltage, and the pre-charge voltage which has adverse effect on the charging rate can be prevented from being input into the sub-pixel, so that the problem of insufficient charging rate of the sub-pixel can be solved, and the image quality of a display picture can be improved.

In some embodiments of the present disclosure, the active pulses of the second gate scan signals loaded by adjacent at least two gate lines may have overlapping times. Since the effective pulses of the second gate scan signals ga1_2 to ga6_2 applied to the adjacent two gate lines have overlapping time, the target data voltage input to the sub-pixel connected to the last gate line of the two gate lines can be input to the sub-pixel connected to the next gate line as the precharge voltage for the sub-pixel connected to the same data line (e.g., DA 2), and the precharge voltage having less or no adverse effect on the charging rate can be input to the sub-pixel, so that the charging rate of the sub-pixel can be further improved, and the image quality of the display screen can be further improved.

In some embodiments of the present disclosure, the timing controller may determine a voltage difference between target data voltages corresponding to sub-pixels electrically coupled to the same data line and to every two adjacent gate lines according to the display data after acquiring the display data of the current display frame. And then judging whether absolute values of all voltage difference values corresponding to the sub-pixels electrically coupled with at least one data line are not smaller than a set threshold value. If so, a first control pulse signal may be input to the gate driving circuit, and display data may be input to the source driving circuit. The gate driving circuit may load a first gate scan signal to the gate line according to the received first control pulse signal, and the source driving circuit may load a data voltage to the data line according to the received display data, so that each sub-pixel inputs a data voltage corresponding to the display data when the mode of step S400 is adopted. If not, however, a second control pulse signal is input to the gate driving circuit, and display data is input to the source driving circuit. The gate driving circuit may load a second gate scanning signal to the gate line according to the received second control pulse signal, and the source driving circuit may load a data voltage to the data line according to the received display data, so that each sub-pixel inputs a data voltage corresponding to the display data when the mode of step S500 is adopted.

In an embodiment of the present disclosure, the timing controller may include: an acquisition unit and a pattern detection function (Pattern Detection Function, PDF) unit. Wherein the acquisition unit may acquire the display data of the current display frame. The mode detection functional unit can determine a voltage difference value between target data voltages corresponding to sub-pixels electrically coupled to the same data line and to every two adjacent gate lines according to the display data; judging whether all voltage difference values corresponding to sub-pixels electrically coupled with at least one data line meet a set range; if yes, inputting a first control pulse signal to the grid driving circuit, and inputting display data to the source driving circuit; if not, a second control pulse signal is input to the gate driving circuit, and display data is input to the source driving circuit.

In some embodiments of the present disclosure, the second gate scan signal loaded on each gate line has one active pulse, and the active pulses of the second gate scan signals loaded on the adjacent K gate lines have overlapping times. Wherein K is an integer and K is not less than 2. Illustratively, k=2 may be set such that there is an overlap time for the active pulses of the second gate scan signal loaded on each adjacent 2 gate lines. As shown in fig. 7, k=3 may be also set so that the effective pulses of the second gate scan signals applied to each adjacent 3 gate lines have overlapping times. K=4 may be also set so that there is an overlapping time of the active pulses of the second gate scan signal loaded on each adjacent 4 gate lines. K=5 may be also set so that there is an overlapping time of the active pulses of the second gate scan signal loaded on every adjacent 5 gate lines. In practical application, the specific value of K may be determined according to the requirement of practical application, which is not limited herein.

In some embodiments of the present disclosure, when there is an overlap time of the second gate scan signals loaded by the adjacent K gate lines, the data voltage corresponding to the display data is charged to the sub-pixel electrically coupled to the K gate line after the overlap time and during the time when the second gate scan signals are loaded by the K gate line, and the precharge voltage is charged to the sub-pixel electrically coupled to the K gate line during the overlap time. Referring to fig. 2a and 7, the gate line GA1 is loaded with the second gate scan signal ga1_2, the gate line GA2 is loaded with the second gate scan signal ga2_2, the gate line GA3 is loaded with the second gate scan signal ga3_2, and the … … gate line GA6 is loaded with the second gate scan signal ga6_2. In the data charging period T11, the signal ga1_2 may control the transistor in the green sub-pixel G11 to be turned on, the signal ga2_2 may control the transistor in the red sub-pixel R21 to be turned on, the signal ga3_1 may control the transistor in the green sub-pixel G31 to be turned on, the data voltage V03 may be input into the green sub-pixel G11 as a target data voltage, and V03 may be input into the red sub-pixel R21 and the green sub-pixel G31 as a precharge voltage, respectively. In the data charging period T12, the signal ga2_2 may control the transistor in the red subpixel R21 to be turned on, the signal ga3_2 may control the transistor in the green subpixel G31 to be turned on, the signal ga4_2 may control the transistor in the red subpixel R41 to be turned on, the data voltage V04 may be input into the red subpixel R21 as a target data voltage, and V04 may be input into the green subpixel G31 and the red subpixel R41 as a precharge voltage, respectively. The remaining sub-pixels are the same and are not described in detail herein.

In an embodiment of the present disclosure, the second control pulse signal may include a third clock signal having the first reference period. For example, when the gate driving circuit employs 6 clock signal lines, as shown in fig. 8, the second control pulse signals cs1_2 to cs6_2 may include a third clock signal having the first reference period Tz 1. Illustratively, the duty cycle of the third clock signal is 50%. The second control pulse signals cs1_2 to cs6_2 differ by pi/6 in sequence. Referring to fig. 2a and 8, in the current display frame, the second control pulse signals cs1_2 to cs6_2 may be input to the gate driving circuit 110 in the display panel, so that the output signal terminals GO of the gate driving circuit 110 may load the first gate scan signals ga1_2 to ga12_2 to the gate lines GA1 to GA12, respectively. Specifically, the second control pulse signal cs1_2 is input to the clock signal line CK1, the second control pulse signal cs2_2 is input to the clock signal line CK2, the second control pulse signal cs3_2 is input to the clock signal line CK3, the second control pulse signal cs4_2 is input to the clock signal line CK4, the second control pulse signal cs5_2 is input to the clock signal line CK5, and the second control pulse signal cs6_2 is input to the clock signal line CK 6. The 1 st stage shift register SR (1) outputs an active pulse corresponding to the first high level of the second control pulse signal cs1_2 through the output signal terminal GO to generate an active pulse of the high level in the signal ga1_2. The 2 nd stage shift register SR (2) outputs the active pulse corresponding to the first high level of the second control pulse signal cs2_2 through the output signal terminal GO to generate the active pulse of the high level in the signal ga2_2. The … … stage 6 shift register SR (6) outputs the active pulse corresponding to the first high level of the second control pulse signal cs6_2 through the output signal terminal GO to generate the active pulse of the high level in the signal ga6_2. The 7 th shift register SR (7) outputs the second active pulse corresponding to the second high level of the second control pulse signal cs1_2 through the output signal terminal GO to generate the active pulse of the high level in the signal ga7_2. The 8 th stage shift register SR (8) outputs the second active pulse corresponding to the second high level of the second control pulse signal cs2_2 through the output signal terminal GO to generate the active pulse of the high level in the signal ga8_2. The … … stage 12 shift register SR (12) outputs the active pulse corresponding to the second high level of the second control pulse signal cs6_2 through the output signal terminal GO to generate the active pulse of the high level in the signal ga12_1.

In some embodiments of the present disclosure, when K is an odd number, the number of effective pulses of the first gate scan signal loaded on each gate line may be (k+1)/2. For example, at k=3, the number of effective pulses of the first gate scan signal loaded on each gate line may be made to be 2. For example, as shown in fig. 2a and 9, the first gate scan signal ga1_1 is loaded on the gate line GA1, the first gate scan signal ga2_1 is loaded on the gate line GA2, the first gate scan signal ga3_1 is loaded on the gate line GA3, and the first gate scan signal ga6_1 is loaded on the … … gate line GA 6. And, the active pulses corresponding to the two high levels in the signals ga1_1 to ga6_1 can control the connected transistors to be turned on so that the sub-pixels can be charged with the data voltages. And, the two high-level effective pulses of the signal ga1_1 and the signal ga2_1 do not have overlapping time, the two high-level effective pulses of the signal ga2_1 and the signal ga3_1 do not have overlapping time, the two high-level effective pulses of the signal ga3_1 and the signal ga4_1 do not have overlapping time, the two high-level effective pulses of the signal ga4_1 and the signal ga5_1 do not have overlapping time, and the two high-level effective pulses of the signal ga5_1 and the signal ga6_1 do not have overlapping time. At k=5, the number of effective pulses of the first gate scan signal loaded on each gate line may be made to be 3. At k=7, the number of effective pulses of the first gate scan signal loaded on each gate line may be made to be 4.

In some embodiments of the present disclosure, when K is an even number, the number of active pulses of the first gate scan signal loaded on each gate line is K/2. Illustratively, when k=2, the number of effective pulses of the first gate scan signal loaded on each gate line may be made to be 1. At k=4, the number of effective pulses of the first gate scan signal loaded on each gate line may be made to be 2. At k=6, the number of effective pulses of the first gate scan signal loaded on each gate line may be made to be 3.

In some embodiments of the present disclosure, the first gate scan signal has a sustain period of one active pulse of tw1, and the second gate scan signal has a sustain period of one active pulse of tw2, tw1=tw2/K. The sustain period of each effective pulse of each first gate scan signal is equal, and the sustain period of each effective pulse of each second gate scan signal is also equal. Illustratively, when k=3, tw1=tw2/3 is shown in conjunction with fig. 7 and 9. Alternatively, when k=4, tw1=tw2/4. Alternatively, tw1=tw2/5 when k=5. Alternatively, tw1=tw2/2 when k=2.

In some embodiments of the present disclosure, when the first gate scan signal has a plurality of active pulses, each subpixel to which the gate line is electrically coupled inputs a data voltage corresponding to display data when the first gate scan signal loaded on each gate line is at a last active pulse. And when the first gate scan signal has a plurality of effective pulses, each sub-pixel electrically coupled to the gate line charges a precharge voltage when the first gate scan signal loaded on each gate line is in other effective pulses except the last effective pulse. For example, as shown in fig. 2a and 9, in the case that the first row of sub-pixels corresponds to 0 gray scale value, the second row of sub-pixels corresponds to 255 gray scale value, the third row of sub-pixels corresponds to 0 gray scale value, the fourth row of sub-pixels corresponds to 255 gray scale value, the fifth row of sub-pixels corresponds to 0 gray scale value, and the sixth row of sub-pixels corresponds to 255 gray scale value, when the formed heavy-duty picture is displayed, the sub-pixels connected by the data line DA2 are taken as an example, since the effective pulses of the first gate scanning signals loaded on every two adjacent gate lines do not have overlapping time, in the data charging period T11, the signal ga1_1 may control the transistors in the green sub-pixel G11 to be turned on, the signal ga2_1 may control the transistors in the red sub-pixel R21 to be turned off, the signal ga3_1 may control the transistors in the green sub-pixel G31 to be turned on, V02 may be input into the green sub-pixel G11 as a target data voltage, and V02 may not be input into the red sub-pixel R21 as a precharge voltage, but V02 may be input into the green sub-pixel G31. In the data charging period T12, the signal ga2_1 may control the transistor in the red sub-pixel R21 to be turned on, the signal ga3_1 may control the transistor in the green sub-pixel G31 to be turned off, the signal ga4_1 may control the transistor in the red sub-pixel R41 to be turned on, V01 may be input into the red sub-pixel R21 as a target data voltage, and V01 may not be input into the green sub-pixel G31 as a precharge voltage, but V01 may be input into the red sub-pixel R41 as a precharge voltage. The remaining sub-pixels are the same and are not described in detail herein.

As an example, taking the red sub-pixel R12, the blue sub-pixel B11, the red sub-pixel R21, the green sub-pixel G21, the red sub-pixel R32, and the blue sub-pixel B31 as examples in the sub-pixels connected to the data line DA2 in the display panel shown in fig. 2B, the voltage difference between the target data voltage Vmr12 charged in the red sub-pixel R12 and the target data voltage Vmb11 charged in the blue sub-pixel B11 is as follows: vmr12-Vmb11. The voltage difference between the target data voltage Vmb11 charged to the blue subpixel B11 and the target data voltage Vmr21 charged to the red subpixel R21 is: vmb11-Vmr21. The voltage difference between the target data voltage Vmr21 charged to the red subpixel R21 and the target data voltage Vmg21 charged to the green subpixel G21 is: vmr21-Vmg21. The voltage difference between the target data voltage Vmg21 charged to the green subpixel G21 and the target data voltage Vmr32 charged to the red subpixel R32 is: vmg21-Vmr32. The voltage difference between the target data voltage Vmr32 charged to the red subpixel R32 and the target data voltage Vmb31 charged to the blue subpixel B31 is: vmr32-Vmb31. The remaining voltage differences are similarly available and will not be described in detail herein.

If the absolute value of Vmr12-Vmb11, the absolute value of Vmb11-Vmr21, the absolute value of Vmr21-Vmg21, the absolute value of Vmg21-Vmr32, and the absolute value of Vmr32-Vmb31 are not smaller than the set threshold, it can be determined that the precharge voltage of the sub-pixel on the data line DA2 has a large adverse effect on the charging rate of the target data voltage, and the problem of insufficient charging rate occurs. In order to improve the problem of the insufficient charging rate, a first control pulse signal may be input to the gate driving circuit 110 in the display panel in the current display frame, so that the output signal terminal GO of the gate driving circuit 110 may load the first gate scan signal to each gate line, respectively. In addition, display data is input to the source driving circuit 120 in the display panel in the current display frame, so that the source driving circuit can load data voltages to the data lines according to the received display data, and when the transistors in the sub-pixels are turned on under the control of the effective pulses in the first gate scanning signals, the data voltages loaded on the connected data lines can be charged, so that each sub-pixel in the display panel can be charged with the target data voltages corresponding to the display data. For example, as shown in connection with fig. 2B and 9, when the blue and green sub-pixels correspond to 255 gray scale values and the red sub-pixel corresponds to 0 gray scale value, since the effective pulses of the first gate scan signals applied to each adjacent two gate lines do not have overlapping time, in the data charging period T11, the signal ga1_1 may control the transistor in the red sub-pixel R12 to be turned on, the signal ga2_1 may control the transistor in the blue sub-pixel B11 to be turned off, the signal ga3_1 may control the transistor in the red sub-pixel R21 to be turned on, V02 may be input into the red sub-pixel R12 as a target data voltage, and V02 may not be input into the blue sub-pixel B11 as a precharge voltage, but V02 may be input into the red sub-pixel R21 as a precharge voltage. In the data charge period T12, the signal ga2_1 may control the transistor in the blue sub-pixel B11 to be turned on, the signal ga3_1 may control the transistor in the red sub-pixel R21 to be turned off, the signal ga4_1 may control the transistor in the green sub-pixel G21 to be turned on, V01 may be input into the blue sub-pixel B11 as a target data voltage, and V01 may not be input into the red sub-pixel R21 as a precharge voltage, but V01 may be input into the green sub-pixel G21 as a precharge voltage. The remaining sub-pixels are the same and are not described in detail herein.

In some embodiments of the present disclosure, the first control pulse signal may be made to include a first clock signal having a first target period and a second clock signal having a second target period, and the first clock signal and the second clock signal alternate. And, the first target period and the second target period are both smaller than the first reference period. Illustratively, the duty cycle of the first clock signal is 50% and the duty cycle of the second clock signal is 25%. For example, when the gate driving circuit employs 6 clock signal lines, as shown in fig. 10, the first control pulse signals cs1_1 to cs6_1 may include a first clock signal having a first target period Tm1 and a second clock signal having a second target period Tm 2. Illustratively, the duty cycle of the first clock signal is 50% and the first clock signals of the first control pulse signals cs1_1 through cs6_1 differ in sequence by pi/2. The duty ratio of the second clock signal is 25%, and the second clock signals in the first control pulse signals cs1_1 to cs6_1 are sequentially different by pi/4. Referring to fig. 2a and 10, in the current display frame, the first control pulse signals cs1_1 to cs6_1 may be input to the gate driving circuit 110 in the display panel, so that the output signal terminals GO of the gate driving circuit 110 may load the first gate scan signals ga1_1 to ga12_1 to the gate lines GA1 to GA12, respectively. Specifically, the first control pulse signal cs1_1 is input to the clock signal line CK1, the first control pulse signal cs2_1 is input to the clock signal line CK2, the first control pulse signal cs3_1 is input to the clock signal line CK3, the first control pulse signal cs4_1 is input to the clock signal line CK4, the first control pulse signal cs5_1 is input to the clock signal line CK5, and the first control pulse signal cs6_1 is input to the clock signal line CK 6. The 1 st stage shift register SR (1) outputs an active pulse corresponding to a first high level (e.g., an active pulse corresponding to a high level in the first clock signal) and an active pulse corresponding to a second high level (e.g., an active pulse corresponding to a high level in the second clock signal) of the first control pulse signal cs1_1 through the output signal terminal GO to generate two active pulses of high level in the signal ga1_1. The 2 nd stage shift register SR (2) outputs an active pulse corresponding to a first high level (e.g., an active pulse corresponding to a high level in the first clock signal) and an active pulse corresponding to a second high level (e.g., an active pulse corresponding to a high level in the second clock signal) of the first control pulse signal cs2_1 through the output signal terminal GO to generate two active pulses of high level in the signal ga2_1. The … … stage 6 shift register SR (6) outputs an active pulse corresponding to a first high level (e.g., an active pulse corresponding to a high level in the first clock signal) and an active pulse corresponding to a second high level (e.g., an active pulse corresponding to a high level in the second clock signal) of the first control pulse signal cs6_1 through the output signal terminal GO to generate two active pulses of high level in the signal ga6_1. The 7 th shift register SR (7) outputs an active pulse corresponding to the third high level (e.g., an active pulse corresponding to the high level in the first clock signal) and an active pulse corresponding to the fourth high level (e.g., an active pulse corresponding to the high level in the second clock signal) of the first control pulse signal cs1_1 through the output signal terminal GO to generate two active pulses of the high level in the signal ga7_1. The 8 th stage shift register SR (8) outputs an active pulse corresponding to the third high level (e.g., an active pulse corresponding to the high level in the first clock signal) and an active pulse corresponding to the fourth high level (e.g., an active pulse corresponding to the high level in the second clock signal) of the first control pulse signal cs2_1 through the output signal terminal GO to generate two active pulses of the high level in the signal ga8_1. … … the 12-th shift register SR (12) outputs an active pulse corresponding to the third high level (e.g., an active pulse corresponding to the high level in the first clock signal) and an active pulse corresponding to the fourth high level (e.g., an active pulse corresponding to the high level in the second clock signal) of the first control pulse signal cs6_1 through the output signal terminal GO to generate two active pulses of high level in the signal ga12_1.

In some embodiments of the present disclosure, as exemplarily shown in fig. 8 and 10, the first target period, the second target period, and the first reference period satisfy the formula; tz1=tm1+tm2; wherein Tm1 represents the first target period, tm2 represents the second target period, and Tz1 represents the first reference period.

Embodiments of the present disclosure provide examples of driving methods of other display panels, which are modified from the implementations of the above-described embodiments. Only the differences between the present embodiment and the above-described embodiments are described below, and their details are not repeated here.

In some embodiments of the present disclosure, the second control pulse signal may be made to include a fifth clock signal having a second reference period. For example, when the gate driving circuit employs 6 clock signal lines, as shown in fig. 11, the second control pulse signals cs1_2 to cs6_2 may include a fifth clock signal having the second reference period Tz 2. Illustratively, the duty cycle of the fifth clock signal is 50%. The second control pulse signals cs1_2 to cs6_2 differ by pi/6 in sequence. Referring to fig. 2a and 11, in the current display frame, the second control pulse signals cs1_2 to cs6_2 may be input to the gate driving circuit 110 in the display panel, so that the output signal terminals GO of the gate driving circuit 110 may load the first gate scan signals ga1_2 to ga12_2 to the gate lines GA1 to GA12, respectively. Specifically, the second control pulse signal cs1_2 is input to the clock signal line CK1, the second control pulse signal cs2_2 is input to the clock signal line CK2, the second control pulse signal cs3_2 is input to the clock signal line CK3, the second control pulse signal cs4_2 is input to the clock signal line CK4, the second control pulse signal cs5_2 is input to the clock signal line CK5, and the second control pulse signal cs6_2 is input to the clock signal line CK 6. The 1 st stage shift register SR (1) outputs an active pulse corresponding to the first high level of the second control pulse signal cs1_2 through the output signal terminal GO to generate an active pulse of the high level in the signal ga1_2. The 2 nd stage shift register SR (2) outputs the active pulse corresponding to the first high level of the second control pulse signal cs2_2 through the output signal terminal GO to generate the active pulse of the high level in the signal ga2_2. The … … stage 6 shift register SR (6) outputs the active pulse corresponding to the first high level of the second control pulse signal cs6_2 through the output signal terminal GO to generate the active pulse of the high level in the signal ga6_2. The 7 th shift register SR (7) outputs the second active pulse corresponding to the second high level of the second control pulse signal cs1_2 through the output signal terminal GO to generate the active pulse of the high level in the signal ga7_2. The 8 th stage shift register SR (8) outputs the second active pulse corresponding to the second high level of the second control pulse signal cs2_2 through the output signal terminal GO to generate the active pulse of the high level in the signal ga8_2. The … … stage 12 shift register SR (12) outputs the active pulse corresponding to the second high level of the second control pulse signal cs6_2 through the output signal terminal GO to generate the active pulse of the high level in the signal ga12_1.

In some embodiments of the present disclosure, the first control pulse signal may be made to include a fourth clock signal having a third target period. And, the third target period is smaller than the second reference period. Illustratively, the duty cycle of the fourth clock signal is 50%. For example, when the gate driving circuit employs 6 clock signal lines, as shown in fig. 12, the first control pulse signals cs1_1 to cs6_1 may include a fourth clock signal having the third target period Tm 3. Illustratively, the duty cycle of the fourth clock signal is 50%, and the fourth clock signals in the first control pulse signals cs1_1 to cs6_1 are sequentially different by pi/2. Referring to fig. 2a and 12, in the current display frame, the first control pulse signals cs1_1 to cs6_1 may be input to the gate driving circuit 110 in the display panel, so that the output signal terminals GO of the gate driving circuit 110 may load the first gate scan signals ga1_1 to ga12_1 to the gate lines GA1 to GA12, respectively. Specifically, the first control pulse signal cs1_1 is input to the clock signal line CK1, the first control pulse signal cs2_1 is input to the clock signal line CK2, the first control pulse signal cs3_1 is input to the clock signal line CK3, the first control pulse signal cs4_1 is input to the clock signal line CK4, the first control pulse signal cs5_1 is input to the clock signal line CK5, and the first control pulse signal cs6_1 is input to the clock signal line CK 6. The 1 st stage shift register SR (1) outputs an active pulse corresponding to a first high level (e.g., an active pulse corresponding to a high level in the fourth clock signal) and an active pulse corresponding to a second high level (e.g., an active pulse corresponding to a high level in the fourth clock signal) of the first control pulse signal cs1_1 through the output signal terminal GO to generate two active pulses of high level in the signal ga1_1. The 2 nd stage shift register SR (2) outputs an active pulse corresponding to a first high level (e.g., an active pulse corresponding to a high level in the fourth clock signal) and an active pulse corresponding to a second high level (e.g., an active pulse corresponding to a high level in the fourth clock signal) of the first control pulse signal cs2_1 through the output signal terminal GO to generate two active pulses of high level in the signal ga2_1. The … … stage 6 shift register SR (6) outputs an active pulse corresponding to a first high level (e.g., an active pulse corresponding to a high level in the fourth clock signal) and an active pulse corresponding to a second high level (e.g., an active pulse corresponding to a high level in the fourth clock signal) of the first control pulse signal cs6_1 through the output signal terminal GO to generate two active pulses of high level in the signal ga6_1. The 7 th shift register SR (7) outputs an active pulse corresponding to the fourth high level (e.g., an active pulse corresponding to the high level in the fourth clock signal) and an active pulse corresponding to the fifth high level (e.g., an active pulse corresponding to the high level in the fourth clock signal) of the first control pulse signal cs1_1 through the output signal terminal GO to generate two active pulses of the high level in the signal ga7_1. The 8 th stage shift register SR (8) outputs an active pulse corresponding to the fourth high level (e.g., an active pulse corresponding to the high level in the fourth clock signal) and an active pulse corresponding to the fifth high level (e.g., an active pulse corresponding to the high level in the fourth clock signal) of the first control pulse signal cs2_1 through the output signal terminal GO to generate two active pulses of high level in the signal ga8_1. The … … stage 12 shift register SR (12) outputs an active pulse corresponding to the fourth high level (e.g., an active pulse corresponding to the high level in the fourth clock signal) and an active pulse corresponding to the fifth high level (e.g., an active pulse corresponding to the high level in the fourth clock signal) of the first control pulse signal cs6_1 through the output signal terminal GO to generate two active pulses of high level in the signal ga12_1.

In some embodiments of the present disclosure, exemplarily, as shown in fig. 11 and 12, when there is an overlapping time of the second gate scan signals loaded by the adjacent K gate lines, the third target period and the second reference period may be satisfied as follows; tm3=kxtz 2; wherein Tz2 represents a second reference period, tm3 represents a third target period, K is an integer and K is not less than 2. Illustratively, tm3=2×tz2 may be made at k=2. When k=3, tm3=3×tz2 can be set. When k=4, tm3=4×tz2 can be set. At k=5, tm3=5×tz2 may be set. At k=6, tm3=6×tz2 may be set.

It will be apparent to those skilled in the art that embodiments of the present disclosure may be provided as a method, system, or computer program product. Accordingly, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present disclosure is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the disclosure. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the preferred embodiments of the present disclosure have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.

It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the spirit and scope of the disclosed embodiments. Thus, given that such modifications and variations of the disclosed embodiments fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is also intended to encompass such modifications and variations.

Claims

1. A driving method of a display panel, comprising:

acquiring display data of a current display frame;

wherein, the duration of one effective pulse of the first gate scanning signal is smaller than the duration of one effective pulse of the second gate scanning signal;

the active pulses of the first gate scan signals loaded by two adjacent gate lines do not have overlapping time; the active pulses of the second gate scan signals loaded by at least two adjacent gate lines have overlapping times.

2. The method of driving a display panel according to claim 1, wherein the second gate scan signal applied to each of the gate lines has one active pulse, and the active pulses of the second gate scan signals applied to the adjacent K gate lines have overlapping times; wherein K is an integer and K is more than or equal to 2;

3. The method of driving a display panel according to claim 2, wherein the first gate scan signal has a sustain period of one active pulse of tw1, and the second gate scan signal has a sustain period of one active pulse of tw2, tw1=tw2/K.

4. A driving method of a display panel according to claim 3, wherein each sub-pixel to which the gate line is electrically coupled inputs a data voltage corresponding to the display data when the first gate scan signal applied to each gate line is in a last active pulse.

5. The method of driving a display panel according to claim 4, wherein when the first gate scan signal has a plurality of active pulses, each sub-pixel to which the gate line is electrically coupled is charged with a precharge voltage when the first gate scan signal loaded by each of the gate lines is in an active pulse other than a last active pulse.

6. The driving method of a display panel according to any one of claims 1 to 5, wherein when there is an overlap time of second gate scan signals loaded by adjacent K gate lines, sub-pixels electrically coupled to the K gate lines are charged with data voltages corresponding to the display data after the overlap time and during a time in which the second gate scan signals are loaded by the K gate lines, and the sub-pixels electrically coupled to the K gate lines are charged with precharge voltages during the overlap time.

7. The driving method of a display panel according to any one of claims 2 to 5, wherein the first control pulse signal includes a first clock signal having a first target period and a second clock signal having a second target period, and the first clock signal and the second clock signal alternate;

8. The driving method of a display panel according to claim 7, wherein the first target period, the second target period, and the first reference period satisfy the following formula;

Tz1＝Tm1+Tm2；

9. The driving method of a display panel according to claim 8, wherein a duty ratio of the first clock signal is 50%, a duty ratio of the second clock signal is 25%, and a duty ratio of the third clock signal is 50%.

10. The driving method of a display panel according to any one of claims 2 to 5, wherein the first control pulse signal includes a fourth clock signal having a third target period, and the second control pulse signal includes a fifth clock signal having a second reference period;

The third target period is smaller than the second reference period.

11. The driving method of a display panel according to claim 10, wherein the third target period and the second reference period satisfy the following formula when there is an overlap time of second gate scan signals loaded by adjacent K gate lines;

Tm3＝K*Tz2；

12. A display device, comprising:

a display panel including a gate driving circuit and a source driving circuit;

the source driving circuit is configured to load data voltages to the data lines according to the received display data so that each sub-pixel in the display panel is charged with the corresponding data voltage;

13. The display device according to claim 12, wherein the timing controller includes:

14. The display device according to claim 12 or 13, wherein the display panel includes: