CN118397982A - Liquid crystal display device having a light shielding layer - Google Patents
Liquid crystal display device having a light shielding layer Download PDFInfo
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- CN118397982A CN118397982A CN202410768635.XA CN202410768635A CN118397982A CN 118397982 A CN118397982 A CN 118397982A CN 202410768635 A CN202410768635 A CN 202410768635A CN 118397982 A CN118397982 A CN 118397982A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The present application provides a liquid crystal display device, the liquid crystal display device includes: the display device comprises a pixel circuit, a plurality of scanning lines, a plurality of data lines, a grid driving module and a source driving module, wherein in the driving period of a frame of picture, a grid driving signal transmitted by the scanning line electrically connected with any row of pixel units comprises a first low-level signal, a first high-level signal, a second low-level signal and a second high-level signal which are continuous in time; the first high level signal of the gate driving signal received by the N-th row of pixel units and the second high level signal of the gate driving signal received by the n+m-th row of pixel units are at least partially overlapped in time. The application improves the charging voltage starting point of the pixel unit, is beneficial to ensuring the charging rate of the pixel unit, and can further avoid the phenomenon of uneven display caused by insufficient charging rate.
Description
Technical Field
The application relates to the technical field of display, in particular to a liquid crystal display device.
Background
As the size of the liquid crystal display panel increases, the Resistance Capacitance (RC) of the data line in the display panel also becomes larger and larger.
The charging time of the liquid crystal display panel of the Tri-gate architecture is only one third of that of the liquid crystal display panel of the normal 1G1D architecture, so the phenomenon of uneven display caused by insufficient charging rate due to the increase of the panel size is more obvious.
Disclosure of Invention
The application provides a liquid crystal display device, which aims to solve the technical problems.
In a first aspect, the present application provides a liquid crystal display device comprising:
a plurality of pixel units arranged in an array, wherein the colors of any two pixel units in the same row of pixel units are the same, and the colors of three rows of pixel units which are arranged continuously are different;
a plurality of scanning lines, each scanning line being connected to a row of pixel units;
a plurality of data lines, each scan line is connected with a column of pixel units;
The grid driving module is connected with the plurality of scanning lines to output a grid driving signal to each row of pixel units through the plurality of scanning lines; and
The source driving module is connected with the plurality of data lines to output a source driving signal to each row of pixel units through the plurality of signal lines;
in a driving period of a frame of picture, a grid driving signal transmitted by a scanning line electrically connected with any row of pixel units comprises a first low-level signal, a first high-level signal, a second low-level signal and a second high-level signal which are continuous in time;
The first high-level signal and the second high-level signal are used for opening the switch of the pixel unit, and the first low-level signal and the second low-level signal are used for closing the switch of the pixel unit;
The first high level signal of the gate driving signal received by the N-th row of pixel units and the second high level signal of the gate driving signal received by the n+m-th row of pixel units are at least partially overlapped in time, M is an integer greater than 1, and N is an integer greater than 0.
In some embodiments, the nth row of pixel cells is the same color as the n+m th row of pixel cells.
In some embodiments, M is equal to a multiple of 3; or alternatively
M is equal to a multiple of 4.
In some embodiments, M is equal to 3 or 4.
In some embodiments, the duration of the first high level signal and the duration of the second high level signal are both equal to the first unit time.
In some embodiments, the duration of the second low level signal is equal to M-1 times the first unit time.
In some embodiments, the first high level signal of the gate driving signal received by the N-th row of pixel units and the second high level signal of the gate driving signal received by the n+m-th row of pixel units are completely coincident in time.
In some embodiments, in a driving period of a frame, a start time of a first high level signal transmitted by a scan line electrically connected to one row of pixel units and a start time of a first high level signal transmitted by a scan line electrically connected to another adjacent row of pixel units are different by a second unit time.
In some embodiments, the second unit time is equal to the first unit time.
In some embodiments, the second unit time is unequal over the first unit time.
In the driving period of a frame of picture, the grid driving signals transmitted by the scanning lines electrically connected with any row of pixel units comprise a first low-level signal, a first high-level signal, a second low-level signal and a second high-level signal which are continuous in time, and because the first high-level signal of the grid driving signals received by the N-th row of pixel units and the second high-level signal of the grid driving signals received by the N+M-th row of pixel units are at least partially overlapped in time, the switches of the N-th row of pixel units and the N+M-th row of pixel units can be simultaneously opened, and when a plurality of source driving signals drive the N-th row of pixel units to refresh, the N+M-th row of pixel units can be precharged. Meanwhile, the first high-level signal, the second low-level signal and the second high-level signal are continuous in time, so that the state of closing is kept after the n+M row of pixel units are precharged, the precharge voltage of the n+M row of pixel units can be kept, and further when the n+M row of pixel units are refreshed, the charging voltage starting point of the n+M row of pixel units is higher, the time for fully charging the n+M row of pixel units is shorter, the charging rate of the pixel units is guaranteed, and the phenomenon of uneven display caused by insufficient charging rate of the pixel units can be avoided.
Drawings
FIG. 1 is a schematic diagram of a related art LCD panel with a Tri-gate architecture;
FIG. 2 is a schematic diagram showing the gate driving signals of a related art LCD panel of the Tri-gate architecture;
FIG. 3 is a voltage variation diagram of the gate driving signal and the pixel capacitor in the related art;
FIG. 4 is a schematic diagram of a liquid crystal display device according to an embodiment of the present application;
fig. 5 is a schematic diagram of gate driving signals in a liquid crystal display device according to an embodiment of the present application;
fig. 6 is a schematic diagram illustrating a pixel unit charging process in a liquid crystal display device according to an embodiment of the application;
fig. 7 is another schematic diagram of gate driving signals in a liquid crystal display device according to an embodiment of the present application;
fig. 8 is another schematic diagram of a liquid crystal display device according to an embodiment of the present application;
Fig. 9 is another schematic diagram of gate driving signals in the liquid crystal display device according to the embodiment of the application.
The pixel comprises a 100-pixel circuit, a 10-pixel unit, a 200-grid driving module and a 300-source driving module.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. The technical solutions described below are only for explaining and explaining the idea of the present application and should not be construed as limiting the scope of protection of the present application.
Currently, in order to reduce the number of data lines, a liquid crystal display panel adopts a Tri-gate architecture, for example, referring to fig. 1, fig. 1 shows a schematic diagram of a liquid crystal display panel of a Tri-gate architecture in the related art, wherein each row of pixel units has the same light emitting color, and the light emitting colors of the adjacent three rows of pixel units are respectively red, green and blue, so that the combination of the pixel units corresponding to the red, green and blue emits light rays of the corresponding colors, the data lines (D1, D2...dn) of the liquid crystal display panel under the Tri-gate architecture become one third, and the scan lines (G1, G2...gn.) become three times, which is finally beneficial to reducing the number of ports of the source driving chip and the cost of the liquid crystal display device.
Referring to fig. 2, fig. 2 is a schematic diagram showing a gate driving signal of a liquid crystal display panel of Tri-gate architecture in the related art, when a high level signal is inputted to a scan line G1, a first row of red pixel cells is turned on, and a data line D1, D2...dn inputs voltage data to each pixel cell of the first row of red pixel cells, so that each pixel cell of the first row of red pixel cells is refreshed and emits light; when a high-level signal is input to the scanning line G2, the second row of green pixel units are turned on, and the data lines D1 and D2.. DN input voltage data to each pixel unit of the second row of green pixel units, so that each pixel unit of the second row of green pixel units is refreshed and emits light; when a high-level signal is input to the scanning line G3, the third row of blue pixel units is turned on, and the data lines D1 and D2.. DN input voltage data to each pixel unit of the third row of blue pixel units, so that each pixel unit of the third row of blue pixel units is refreshed and emits light, and so on, until all rows of pixel units are refreshed, and then refreshing of a display frame of the liquid crystal display panel is completed.
However, when the size of the liquid crystal display panel increases, the time constant τ corresponding to the completion of the charging of the pixel unit increases due to the increase in the data line resistance, which easily causes the pixel unit to not reach the desired light emitting data voltage without the completion of the charging. For example, referring to fig. 3, fig. 3 shows a voltage variation diagram of the gate driving signal and the pixel capacitor, and since the time for the scan line GN to maintain at the high level is less than the time constant of the pixel capacitor, the pixel cell is charged from being turned on to being turned off, and is not fully charged and reaches the ideal light emitting data voltage, which results in the phenomenon of uneven display caused by insufficient charging rate of the pixel cell.
Accordingly, the present application provides a liquid crystal display device, which will be described in detail below. First, referring to fig. 4, fig. 4 shows a schematic diagram of a liquid crystal display device according to an embodiment of the application, wherein the liquid crystal display device includes a plurality of pixel units 10, a plurality of scan lines G1 to GN, a plurality of data signals D1 to DN, a gate driving module 200 and a source driving module 300 arranged in an array.
Specifically, taking fig. 4 as an example, the pixel unit 10 includes a switching transistor, a storage capacitor and a pixel capacitor, where a gate of the switching transistor is electrically connected to a scanning line of a corresponding row, a source of the switching transistor is electrically connected to a data line of a corresponding column, a drain of the switching transistor is connected to the storage capacitor and one plate of the pixel capacitor, and the other plate of the storage capacitor and the pixel capacitor is connected to the common electrode. When the switch transistor is turned on, the voltage signal input by the data line charges the storage capacitor and the pixel capacitor, so that the liquid crystal between the pixel capacitors deflects and passes light to emit light.
It is understood that the embodiment of the pixel unit 10 is not limited thereto, and for example, the pixel unit 10 may also employ a 2T1C pixel circuit structure or a 4T1C pixel circuit structure.
The pixel circuits 100 are formed by a plurality of pixel units 10 arranged in an array, each scanning line is connected with one row of pixel units 10, each scanning line is connected with one column of pixel units 10, the colors of any two pixel units 10 in the same row of pixel units 10 are the same, and the colors of three rows of pixel units 10 which are arranged continuously are different from each other. For example, referring to fig. 4, the light emitting color of the first row of pixel units 10 is red, the light emitting color of the second row of pixel units 10 is green, the light emitting color of the third row of pixel units 10 is blue, the light emitting color of the fourth row of pixel units 10 is red, the light emitting color of the fifth row of pixel units 10 is green, the light emitting color of the sixth row of pixel units 10 is blue, and so on.
It is understood that the arrangement of the pixel units 10 of different colors is not limited to, for example, the light emission color of the pixel units 10 of the first row is green, the light emission color of the pixel units 10 of the second row is red, and the light emission color of the pixel units 10 of the third row is blue; for another example, the light emission color of the first row of pixel units 10 is red, the light emission color of the second row of pixel units 10 is blue, and the light emission color of the third row of pixel units 10 is green.
The gate driving module 200 is configured to output a plurality of gate driving signals, and the gate driving module 200 is connected to the plurality of scan lines G1 to GN to output a gate driving signal to each row of pixel units 10 through the plurality of scan lines G1 to GN, and each gate driving signal is configured to control one row of pixel units 10. For example, referring to fig. 4, the scan line G1 is connected to the gate of the switching transistor of the first row of pixel units 10, and the gate driving signal transmitted through the scan line G1 may turn on the first row of pixel units 10; the scan line G2 is connected to the gate of the switching transistor of the second row of pixel units 10, and the second row of pixel units 10 may be turned on by the gate driving signal transmitted through the scan line G2; the scan line GN is connected to the gate of the switching transistor of the nth row of pixel units 10, and the gate driving signal transmitted through the scan line GN may turn on the nth row of pixel units 10.
Illustratively, the gate driving module 200 outputting the plurality of gate driving signals may be, but is not limited to, a gate driving chip (GATE DRIVER IC), a Power management chip (Power MANAGEMENT IC, PMIC), or a level shifter (LEVEL SHIFT).
The source driving module 300 is configured to output a plurality of source driving signals, and the source driving module 300 is connected to the plurality of data lines D1 to DN, so as to output a source driving signal to each row of pixel units 10 through the plurality of signal lines D1 to DN, and each source driving signal is configured to drive a row of pixel units 10 to emit light. For example, referring to fig. 4, the data line D1 is connected to the source of the switching transistor of the first column of pixel units 10, and the source driving signal transmitted through the data line D1 can charge the pixel capacitance and the storage capacitance of the first column of pixel units 10, so that the first column of pixel units 10 emits light; the data line D2 is connected to the source of the switching transistor of the second column pixel unit 10, and the source driving signal transmitted through the data line D2 can charge the pixel capacitor and the storage capacitor of the second column pixel unit 10, so that the second column pixel unit 10 emits light; the data line DN is connected to the source of the switching transistor of the nth column pixel unit 10, and the source driving signal transmitted through the data line DN can charge the pixel capacitance and the storage capacitance of the nth column pixel unit 10, thereby making the nth column pixel unit 10 emit light.
Illustratively, the Source driving module 300 outputting a plurality of Source driving signals may be, but is not limited to, a Source driving Chip (Source Driver IC) or a flip-Chip-On-Film circuit (Chip-On-Film).
In the embodiment of the present application, in the driving period of one frame of picture, the gate driving signals transmitted by the scan lines electrically connected to any row of the pixel units 10 include a first low level signal, a first high level signal, a second low level signal and a second high level signal which are consecutive in time, and since the first high level signal of the gate driving signals received by the nth row of the pixel units 10 and the second high level signal of the gate driving signals received by the n+mth row of the pixel units 10 are at least partially overlapped in time, M is an integer greater than 1, N is an integer greater than 0, and thus the switches of the nth row of the pixel units 10 and the n+mth row of the pixel units 10 can be simultaneously turned on, and the n+mth row of the pixel units 10 can be precharged when the source driving signals drive the nth row of the pixel units to refresh. Meanwhile, since the first high-level signal, the second low-level signal and the second high-level signal are continuous in time, after the n+m row of pixel units 10 are precharged, the second low-level signal can keep the off state, so that the precharge voltage of the n+m row of pixel units 10 can be kept, and further when the n+m row of pixel units 10 are refreshed, the charging voltage starting point of the n+m row of pixel units 10 is higher, so that the full charge time of the n+m row of pixel units 10 is shorter, the charging rate of the pixel units 10 is guaranteed, and the phenomenon of uneven display caused by insufficient charging rate of the pixel units 10 can be avoided finally.
For example, referring to fig. 5 and 6, fig. 6 shows a schematic diagram of a charging process of the pixel units 10 in the embodiment of the application, for the red pixel units 10 in the fourth row and in the first column and the red pixel units 10 in the first row and in the first column, the first high level signal of the gate driving signal GD4 overlaps the second high level signal of the gate driving signal GD1 in time, and when the second high level signal of the gate driving signal GD1 refreshes the pixel units 10 in the first row, the gate driving signal GD4 simultaneously turns on the red pixel units 10 in the fourth row and in the first column, so that the red pixel units 10 in the fourth row and in the first column are precharged. Subsequently, the second low level signal of the gate driving signal GD4 comes to turn off the fourth row of the pixel cells 10, so that the precharge voltage of the red pixel cells 10 in the fourth row and in the first column is maintained until the second high level signal of the gate driving signal GD4 comes to turn on the red pixel cells 10 in the fourth row and in the first column again, so that the red pixel cells 10 in the fourth row and in the first column are lifted from the precharge voltage, thereby raising the charging voltage starting point when the pixel cells 10 are refreshed, so that the time for fully charging the pixel cells 10 is shorter, which is finally advantageous for guaranteeing the charging rate of the pixel cells 10.
In some embodiments of the present application, the nth row of pixel cells 10 is the same color as the n+m row of pixel cells 10. For example, referring to fig. 4 and 5, when the liquid crystal display device refreshes the first row of pixel units 10, the gate driving signal GD1 and the gate driving signal GD4 turn on the first row of pixel units 10 and the fourth row of pixel units 10 having the same light emission color as red at the same time, thereby precharging the fourth row of pixel units 10, and the liquid crystal display device starts refreshing the fourth row of pixel units 10, and the precharge voltage of the fourth row of pixel units 10 is maintained at the light emission data voltage corresponding to the first row of pixel units 10.
For another example, when the liquid crystal display device refreshes the second row pixel unit 10, the gate driving signal GD2 and the gate driving signal GD5 turn on the second row pixel unit 10 and the fifth row pixel unit 10 having the same emission color as green at the same time, thereby precharging the fifth row pixel unit 10, and the liquid crystal display device starts refreshing the fifth row pixel unit 10, and the precharge voltage of the fifth row pixel unit 10 is maintained at the emission data voltage corresponding to the second row pixel unit 10.
For another example, when the liquid crystal display device refreshes the third row pixel unit 10, the third row pixel unit 10 and the sixth row pixel unit 10 having the emission color of blue are simultaneously turned on by the gate driving signal GD3 and the gate driving signal GD6, thereby precharging the sixth row pixel unit 10, and the liquid crystal display device starts refreshing the sixth row pixel unit 10, and the precharge voltage of the sixth row pixel unit 10 is maintained at the emission data voltage corresponding to the third row pixel unit 10.
It should be noted that, in the display screen, most of the same color and the light emitting colors of the adjacent pixels are generally the same, that is, the light emitting data voltages of the two adjacent rows of pixel units 10 with the same light emitting color are basically similar, because the N-th row of pixel units 10 and the n+m-th row of pixel units 10 have the same color, and when the N-th row of pixel units 10 are refreshed, the n+m-th row of pixel units 10 will be precharged, so that the precharge voltage of the n+m-th row of pixel units 10 will be the light emitting data voltage corresponding to the N-th row of pixel units 10, and for the n+m-th row of pixel units 10, the light emitting data voltages of the two adjacent rows of pixel units 10 are basically similar, after the precharge, the ideal charge voltage can be reached more quickly, thereby further shortening the charge time of the pixel units 10, being beneficial to further ensuring the charge rate of the pixel units 10 and avoiding the phenomenon of insufficient charge rate.
In some embodiments of the application, M is equal to 3. For example, referring to fig. 4 and 5, during the liquid crystal display device brushes the first row of pixel units 10, the gate driving signals GD1 and GD4 turn on the first row of pixel units 10 and the fourth row of pixel units 10 that are adjacent to each other and emit red light, and the second row of pixel units 10 that emit green light and the third row of pixel units 10 that emit blue light remain off.
For another example, during the second row of pixel units 10 is being brushed by the liquid crystal display device, the gate driving signal GD2 and the gate driving signal GD5 turn on the second row of pixel units 10 and the fifth row of pixel units 10 that are adjacent to each other and emit light in the same color as green, and the third row of pixel units 10 and the fourth row of pixel units 10 that emit light in the color of blue and emit light in the color of red simultaneously remain turned off.
For another example, during the period when the liquid crystal display device brushes the third row of pixel units 10, the gate driving signals GD3 and GD6 turn on the third row of pixel units 10 and the sixth row of pixel units 10 that are adjacent to each other and emit light in blue at the same time, and the fourth row of pixel units 10 that emit light in red and the fifth row of pixel units 10 that emit light in green remain turned off.
For another example, during the period from when the liquid crystal display device refreshes the fourth row pixel unit 10 to the fifth row pixel unit 10, that is, when the gate driving signal GD4 turns on the fourth row pixel unit 10 or the gate driving signal GD5 turns on the fifth row pixel unit 10, the gate driving signal GD6 is at a low level to turn off the sixth row pixel unit 10, so that the precharge voltage of the sixth row pixel unit 10 is maintained at the light emitting data voltage corresponding to the third row pixel unit 10 before the sixth row pixel unit 10 starts to refresh. And so on, ultimately allowing each row of pixel cells 10 to complete the precharge and precharge voltage holding process.
It will be appreciated that the above embodiment is exemplified by the case where two adjacent rows of the pixel units 10 are simultaneously turned on with the same emission color, and that it is actually possible to simultaneously turn on the pixel units 10 of more adjacent rows (for example, three rows) with the same emission color; or M may be a multiple of 3, that is, two rows of pixel units 10 with the same emission color and with the same interval may be turned on at the same time, for example, referring to fig. 4 and fig. 7, fig. 7 shows another schematic diagram of the gate driving signal in the embodiment of the present application, and when the first row of pixel units 10 is refreshed, the seventh row of pixel units 10 with the same emission color as red are turned on correspondingly, so that the seventh row of pixel units 10 are precharged.
In some embodiments of the present application, referring to fig. 5, the duration of the first high level signal and the duration of the second high level signal are both equal to the first unit time T1.
In some embodiments of the present application, for example, for embodiments in which the duration of the first high level signal and the duration of the second high level signal are both equal to the first unit time T1, referring to fig. 5, the first high level signal of the gate driving signal received by the nth row of pixel units 10 and the second high level signal of the gate driving signal received by the n+mth row of pixel units 10 are completely overlapped in time, thereby maximally extending the precharge duration of the pixel units 10.
It will be appreciated that the duration of the first high level signal and the duration of the second high level signal may also be unequal; alternatively, the first high level signal of the gate driving signal received by the N-th row of pixel units 10 and the second high level signal of the gate driving signal received by the n+m-th row of pixel units 10 may only partially overlap in time.
In some embodiments of the present application, the duration of the second low level signal is equal to M-1 times the first unit time T1. For example, referring to fig. 5, the first high level signal of the gate driving signal received by the first row of pixel units 10 in fig. 5 overlaps with the second high level signal of the gate driving signal received by the fourth row of pixel units 10 in time at least partially, where M is equal to 3, and thus the duration of the second low level signal is equal to 2 times the first unit time T1, so that the second row of pixel units 10 and the third row of pixel units 10 are refreshed within the duration of the second low level signal.
In some embodiments of the present application, in the driving period of one frame, the start time of the first high level signal transmitted by the scan line electrically connected to one row of the pixel units 10 and the start time of the first high level signal transmitted by the scan line electrically connected to the adjacent other row of the pixel units 10 are different by the second unit time T2. For example, referring to fig. 5, the start time of the first high level of the gate driving signal GD1 inputted to the first row of pixel units 10 is different from the start time of the first high level of the gate driving signal GD2 inputted to the second row of pixel units 10 by a second unit time T2; the start time of the first high level of the gate driving signal GD2 input to the second row of pixel units 10 and the start time of the first high level of the gate driving signal GD3 input to the third row of pixel units 10 are also different by the second unit time T2; the start timing of the first high level of the gate driving signal GD3 input to the third row pixel unit 10 is different from the start timing of the first high level of the gate driving signal GD4 input to the fourth row pixel unit 10 by the same second unit time T2.
In some embodiments of the present application, the second unit time T2 is greater than the first unit time T1, that is, the duration of the first high level signal may be less than the precharge/refresh time interval of two adjacent rows of the pixel cells 10, thereby ensuring that each row of the pixel cells is precharged/refreshed with a certain time interval. In some embodiments of the present application, the second unit time T2 may be equal to the first unit time T1, that is, the next pixel unit may be precharged/refreshed immediately after the previous row of pixel units 10 are precharged/refreshed, so as to further improve the refresh frequency of the liquid crystal display device.
It should be understood that the above-mentioned liquid crystal display device is exemplified by the RGB color mode, and is not limited thereto, for example, the liquid crystal display device may be in the RGBW color mode or the CMYK color mode, where M may be equal to a multiple of 4, or M may be equal to 4, for example, referring to fig. 8 and 9, the liquid crystal display device is in the RGBW color mode, the light emitting color of the first row of pixel units 10 is red, the light emitting color of the second row of pixel units 10 is green, the light emitting color of the third row of pixel units 10 is blue, the light emitting color of the fourth row of pixel units 10 is red, and so on. When the liquid crystal display device refreshes the first row of pixel units 10, the gate driving signals GD1 and GD5 simultaneously turn on the first row of pixel units 10 and the fifth row of pixel units 10 with red emission color, thereby precharging the fifth row of pixel units 10; when the liquid crystal display device refreshes the second row of pixel units 10, the gate driving signals GD2 and GD6 simultaneously turn on the second row of pixel units 10 and the sixth row of pixel units 10 with the same green emission color, thereby precharging the sixth row of pixel units 10; when the liquid crystal display device refreshes the third row of pixel units 10, the gate driving signals GD3 and GD7 turn on the third row of pixel units 10 and the seventh row of pixel units 10 which are adjacent to each other and have the same blue emission color at the same time, thereby precharging the seventh row of pixel units 10, and so on.
The foregoing has outlined some of the more detailed description of the preferred embodiments of the present application in order that the detailed description of the principles and embodiments of the present application may be had by way of example only, the above description of the preferred embodiments being provided to facilitate the understanding of the method and core concepts of the present application; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, the present description should not be construed as limiting the present application.
Claims (10)
1. A liquid crystal display device, comprising:
a plurality of pixel units arranged in an array, wherein the colors of any two pixel units in the same row of pixel units are the same, and the colors of three rows of pixel units which are arranged continuously are different from each other;
A plurality of scanning lines, each scanning line being connected to a row of the pixel units;
a plurality of data lines, each of which is connected with a column of pixel units;
The grid driving module is connected with the scanning lines so as to output a grid driving signal to the pixel units in each row through the scanning lines; and
The source electrode driving module is connected with the data lines so as to output a source electrode driving signal to each row of pixel units through the signal lines;
in a driving period of a frame of picture, a gate driving signal transmitted by a scanning line electrically connected with any row of pixel units comprises a first low-level signal, a first high-level signal, a second low-level signal and a second high-level signal which are continuous in time;
the first high-level signal and the second high-level signal are used for opening a switch of the pixel unit, and the first low-level signal and the second low-level signal are used for closing the switch of the pixel unit;
The first high level signal of the gate driving signal received by the pixel unit in the nth row is at least partially overlapped with the second high level signal of the gate driving signal received by the pixel unit in the n+mth row in time, M is an integer greater than 1, and N is an integer greater than 0.
2. The liquid crystal display device according to claim 1, wherein the pixel cells of the nth row are the same color as the pixel cells of the n+m row.
3. The liquid crystal display device of claim 2, wherein M is equal to a multiple of 3; or alternatively
M is equal to a multiple of 4.
4. A liquid crystal display device as claimed in claim 3, characterized in that M is equal to 3 or 4.
5. The liquid crystal display device according to claim 1, wherein a duration of the first high-level signal and a duration of the second high-level signal are both equal to a first unit time.
6. The liquid crystal display device according to claim 5, wherein a duration of the second low level signal is equal to M-1 times the first unit time.
7. The liquid crystal display device of claim 5, wherein the first high level signal of the gate driving signal received by the pixel unit of the nth row is completely overlapped in time with the second high level signal of the gate driving signal received by the pixel unit of the n+m row.
8. The liquid crystal display device of claim 5, wherein in a driving period of one frame, a start timing of a first high level signal transmitted by a scan line electrically connected to one row of the pixel units and a start timing of a first high level signal transmitted by a scan line electrically connected to another adjacent row of the pixel units are different by a second unit time.
9. The liquid crystal display device according to claim 8, wherein the second unit time is equal to the first unit time.
10. The liquid crystal display device according to claim 8, wherein the second unit time is greater than the first unit time.
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