CN114446168B - Manufacturing method of array substrate and array substrate - Google Patents
Manufacturing method of array substrate and array substrate Download PDFInfo
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- CN114446168B CN114446168B CN202210076979.5A CN202210076979A CN114446168B CN 114446168 B CN114446168 B CN 114446168B CN 202210076979 A CN202210076979 A CN 202210076979A CN 114446168 B CN114446168 B CN 114446168B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
- G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
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Abstract
The embodiment of the application discloses a manufacturing method of an array substrate and the array substrate, wherein the manufacturing method of the array substrate comprises the following steps: forming a via hole on a substrate; filling conductive paste in the via hole to form a connecting electrode, wherein the connecting electrode comprises a first conductive block arranged in the via hole, a second conductive block lapped on one end of the first conductive block and a third conductive block lapped on the other end of the first conductive block, and the second conductive block and the third conductive block are arranged outside the via hole; forming a first wire on one side of the substrate, wherein the first wire is covered on the substrate and the second conductive block; the second wiring is formed on the other side of the substrate and covers the substrate and the third conductive block, so that the technical problem that the front trend and the back wiring of the display panel are difficult to electrically connect through the through hole can be solved.
Description
Technical Field
The application relates to the field of display, in particular to a manufacturing method of an array substrate and the array substrate.
Background
With the development of display technology, the full screen has become a hot spot for market pursuit. Limited to the current technology, the screen occupation ratio of the full screen can be realized to be more than 90%. Display panels typically include a display area and a non-display area, and in order to achieve a full screen, the size of the non-display area needs to be reduced, for example, the display panel adopts a narrow bezel or a borderless design.
For display panels employing a narrow frame or borderless design, packaging of the driver ICs (chips) is particularly important, and connection of the driver ICs and the display panel is accomplished through a Bonding (Bonding) process. In the manufacturing process of the display panel, binding points of the driving ICs are reserved. In order to realize a narrow frame or borderless design, a driving IC such as a Chip On Film (COF) needs to be bent to the back surface of the display panel, and a bonding area of an external circuit is disposed On the back surface of the display panel. However, the bent COF is not only easy to damage the circuit, and the circuit conduction is affected, but also has a larger gap with the side surface of the display panel. Even if the driving IC is disposed on the back of the display panel through the binding structure, and then the printed circuit board is bound with the driving IC to avoid bending of the COF, due to the limitation of the technology, a gap still exists between the existing binding structure and the side of the display panel, and an outer frame with a certain width needs to be disposed for shielding, so that the display, especially the spliced display, cannot be narrowed or borderless.
Aiming at the defects, a novel back binding structure is provided, and the front wiring of the display panel is connected with the back wiring through the via hole, so that the binding area of the display panel is transferred to the back of the display panel, and the design of a narrow frame or a frame-free structure is facilitated. However, when copper is entirely coated on the front and back surfaces of the display panel to form the traces, the copper layer is difficult to fill the vias due to the small aperture of the vias, so that the front and back traces of the display panel cannot be normally connected.
Disclosure of Invention
The embodiment of the application provides a manufacturing method of an array substrate and the array substrate, which can solve the technical problem that the front trend and the back trend of a display panel are difficult to be electrically connected through a via hole.
The embodiment of the application provides a manufacturing method of an array substrate, which comprises the following steps:
step B1, forming a via hole on a substrate;
step B2, filling conductive paste in the via hole to form a connection electrode, wherein the connection electrode comprises a first conductive block arranged in the via hole, a second conductive block lapped on one end of the first conductive block and a third conductive block lapped on the other end of the first conductive block, and the second conductive block and the third conductive block are arranged outside the via hole;
and B3, forming a first wire on one side of the substrate, forming a second wire on the other side of the substrate, wherein the first wire is covered on the substrate and the second conductive block, and the second wire is covered on the substrate and the third conductive block.
Optionally, in some embodiments of the present application, in the step B2, a cross-sectional area of the second conductive bump is larger than a cross-sectional area of the first conductive bump, and the second conductive bump is covered on the substrate; and/or the number of the groups of groups,
the cross-sectional area of the third conductive block is larger than that of the first conductive block, and the third conductive block covers the substrate.
Optionally, in some embodiments of the present application, the via has a pore size greater than or equal to 20 microns.
Optionally, in some embodiments of the present application, in the step B1, the via hole is made on the substrate by using a laser drilling method;
in the step B2, the conductive paste is filled in the via hole by using an inkjet printing method.
Optionally, in some embodiments of the present application, the step B1 further includes: and forming a diversion trench on the substrate, wherein the diversion trench is communicated with the corresponding through hole.
The embodiment of the application also provides an array substrate, which comprises:
a substrate provided with a via hole;
the connecting electrode comprises a first conductive block arranged in the via hole, a second conductive block lapped on one end of the first conductive block and a third conductive block lapped on the other end of the first conductive block, and the second conductive block and the third conductive block are arranged outside the via hole;
the first wiring is arranged on one side of the substrate and covers the substrate and the second conductive block; and
the second wiring is arranged on the other side of the substrate and covers the substrate and the third conductive block.
Optionally, in some embodiments of the present application, a cross-sectional area of the second conductive bump is greater than a cross-sectional area of the first conductive bump, and the second conductive bump is covered on the substrate.
Optionally, in some embodiments of the present application, a cross-sectional area of the third conductive bump is greater than a cross-sectional area of the first conductive bump, and the third conductive bump covers the substrate.
Optionally, in some embodiments of the present application, the via has a pore size greater than or equal to 20 microns.
Optionally, in some embodiments of the present application, the substrate is further provided with a diversion trench, and the diversion trench is communicated with the corresponding via hole.
According to the manufacturing method of the array substrate and the array substrate, the conductive paste is filled in the through holes to form the connecting electrodes, compared with the whole copper-clad mode, the conductive paste has fluidity, the through holes are easier to fill, the first wiring formed later is electrically connected with the second wiring through the connecting electrodes, and the reliability of the array substrate is effectively improved; in addition, the connecting electrode comprises a first conductive block arranged in the through hole, a second conductive block lapped at one end of the first conductive block and a third conductive block lapped at the other end of the first conductive block, wherein the second conductive block and the third conductive block are arranged outside the through hole, namely, the connecting electrode is exposed out of the through hole, so that the contact area of the connecting electrode and wires at two opposite sides of the array substrate can be increased, the contact of the connecting electrode and wires at two opposite sides of the array substrate is tighter, and the connecting electrode is not easy to separate.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic flow chart of a method for manufacturing an array substrate according to an embodiment of the present application;
fig. 2 is a schematic top view of a first substrate according to an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional view taken along the direction A-A in FIG. 2;
FIG. 4 is a schematic diagram of a first substrate with connection electrodes formed thereon according to an embodiment of the present application;
fig. 5 is a schematic top view of a first substrate with connection electrodes according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of forming a first conductive layer and a second conductive layer on a first substrate according to an embodiment of the present application;
fig. 7 is a schematic diagram of a first conductive layer and a second conductive layer on a first substrate after patterning according to an embodiment of the present application;
fig. 8 is a schematic top view of a second substrate according to an embodiment of the present disclosure;
FIG. 9 is a schematic cross-sectional view taken along the direction B-B in FIG. 8;
FIG. 10 is a schematic diagram of forming a connection electrode on a second substrate according to an embodiment of the present disclosure;
fig. 11 is a schematic top view of a second substrate with connection electrodes according to an embodiment of the present disclosure;
fig. 12 is a schematic view of forming a first conductive layer and a second conductive layer on a second substrate according to an embodiment of the present disclosure;
fig. 13 is a schematic diagram of a second substrate after patterning a first conductive layer and a second conductive layer according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. Furthermore, it should be understood that the detailed description is presented herein for purposes of illustration and explanation only and is not intended to limit the present application. In this application, unless otherwise indicated, terms of orientation such as "upper" and "lower" are used to generally refer to the upper and lower positions of the device in actual use or operation, and specifically the orientation of the drawing figures; while "inner" and "outer" are for the outline of the device.
The embodiment of the application provides a manufacturing method of an array substrate and the array substrate. The following will describe in detail. The following description of the embodiments is not intended to limit the preferred embodiments.
Referring to fig. 1, an embodiment of the present application provides a method for manufacturing an array substrate, including:
step B1, as shown in fig. 2 and 3, forming a via 110 on the substrate 100;
step B2, as shown in fig. 4 and fig. 5, the via hole 110 is filled with a conductive paste to form a connection electrode 200, the connection electrode 200 includes a first conductive block 210 disposed in the via hole 110, a second conductive block 220 overlapped with one end of the first conductive block 210, and a third conductive block 230 overlapped with the other end of the first conductive block 210, and the second conductive block 220 and the third conductive block 230 are disposed outside the via hole 110;
in step B3, as shown in fig. 6 and 7, a first trace 310 is formed on one side of the substrate 100, a second trace 410 is formed on the other side of the substrate 100, the first trace 310 covers the substrate 100 and the second conductive block 220, and the second trace 410 covers the substrate 100 and the third conductive block 230, thereby manufacturing the array substrate.
In the embodiment of the present application, the conductive paste is filled in the via hole 110 to form the connection electrode 200, so that compared with the whole copper-clad manner, the conductive paste has fluidity and is easier to fill the via hole 110, so that the first trace 310 formed later is electrically connected with the second trace 410 through the connection electrode 200, and the reliability of the array substrate is effectively improved; in addition, the connection electrode 200 includes a first conductive block 210 disposed in the via hole 110, a second conductive block 220 overlapping one end of the first conductive block 210, and a third conductive block 230 overlapping the other end of the first conductive block 210, where the second conductive block 220 and the third conductive block 230 are disposed outside the via hole 110, i.e. the exposed surface area of the connection electrode 200 is large, which can increase the contact area between the connection electrode 200 and the wires on two opposite sides of the array substrate, so that the connection electrode 200 contacts the wires on two opposite sides of the array substrate more tightly and is not easy to break away.
Specifically, in the step B1, the number of the via holes 110 may be plural; in the above step B3, the number of the first wires 310 and the second wires 410 may be plural, and each first wire 310 corresponds to one via 110 and one first wire 410. Of course, the number of the via holes 110, the first wires 310 and the second wires 410 may be appropriately adjusted according to the actual situation and the specific requirements, which is not limited herein.
Specifically, the manufactured array substrate includes a display area AA and a non-display area NA, the via hole 110, the connection electrode 200, the first trace 310 and the second trace 410 are disposed in the non-display area NA, and the array substrate is mainly used for realizing back binding of a driving IC, the driving IC can be directly bound to the second trace 410, and also can be bound to the second trace 410 through a flexible circuit board, thereby being beneficial to realizing narrow-frame or borderless design.
Specifically, in the step B1, the via hole 110 may be fabricated on the substrate 100 by using a laser drilling method, and compared with other drilling methods, the laser drilling method has the advantages of high speed and high efficiency, and can improve the production capacity; in addition, the laser drilling can obtain a large depth-to-diameter ratio, and the aperture of the via hole 110 prepared by adopting the laser drilling mode is smaller, so that the narrow-frame or borderless design is realized.
Specifically, the aperture of the via 110 is greater than or equal to 20 microns, for example, the aperture of the via 110 may be 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, or greater. Of course, the aperture of the via hole 110 may be adjusted in the present year according to the actual situation selection and specific requirement, which is not limited herein.
Specifically, in the embodiment of the present application, the material of the substrate 100 may be glass or polyimide, and of course, the material of the substrate 100 may be modified appropriately according to the actual situation and the specific requirement, which is not limited herein.
Specifically, in the step B2, the conductive paste may be filled in the via hole 110 by using an inkjet printing method, and compared with other processes, the inkjet printing process may achieve an accuracy of less than 10 micrometers, and by aligning the nozzle 500 with the via hole 110, the conductive paste may be accurately filled in the via hole 110.
Specifically, in the embodiment of the application, the conductive paste includes an organic carrier and nano conductive particles, the nano conductive particles are dispersed in the organic carrier, and the conductive paste has a fluid property. When the conductive paste is filled in the via hole 110, the via hole 110 is capillary holes because the conductive paste has a certain viscosity and the aperture of the via hole 110 is smaller, the via hole 110 is favorable for the conductive paste to generate capillary phenomenon, and the conductive paste cannot flow out from the via hole 110. In this embodiment, the spray head 500 sprays excessive conductive paste toward the via 110 such that the conductive paste overflows from both ends of the via 110, thereby forming the second and third conductive bumps 220 and 230.
Specifically, in the embodiment of the present application, since the conductive paste has fluid characteristics and gravity influence, the volume of the third conductive bump 230 is larger than the volume of the second conductive bump 220 in the manufactured connection electrode 200.
Specifically, the organic carrier comprises a high polymer resin and a solvent, wherein the high polymer resin is one or more materials selected from cellulose acetate butyrate, acrylic resin, melamine formaldehyde resin, polyamino resin, vinyl chloride-vinyl acetate copolymer resin, polyphenyleneoxide resin and polyurethane resin, and the solvent is one or more materials selected from diethylene glycol butyl ether acetate, isophorone, dipropylene glycol methyl ether, dimethyl glutarate, dimethyl succinate and dimethyl adipate. It will be appreciated that the particular materials of the polymer resin and solvent may be suitably modified according to the actual choice and particular needs, and are not limited solely herein.
Specifically, the nano conductive particles are one or more materials selected from gold powder, silver powder, aluminum powder, copper powder, nickel powder, carbon nanotubes, graphite, graphene, carbon fibers and carbon black. It will be appreciated that the specific materials of the nano-conductive particles may be suitably modified according to the actual situation selection and specific needs, and are not limited solely herein.
Specifically, in the above step B2, the material of the connection electrode 200 prepared using the conductive paste includes the above polymer resin and nano conductive particles.
Specifically, in the above step B2, as shown in fig. 4, 5 and 7, the cross-sectional area of the second conductive bump 220 is larger than that of the first conductive bump 210, and the second conductive bump 220 is covered on the substrate 100. Under this structure, the exposed surface area of the connection electrode 200 is large, so that the contact area between the connection electrode 200 and the first trace 310 can be increased, so that the connection electrode 200 is more tightly contacted with the first trace 310, and is not easy to separate.
Specifically, in the above step B2, the cross-sectional area of the third conductive bump 230 is larger than the cross-sectional area of the first conductive bump 210, and the third conductive bump 230 covers the substrate 100. Under this structure, the exposed surface area of the connection electrode 200 is large, so that the contact area between the connection electrode 200 and the second trace 410 can be increased, so that the connection electrode 200 contacts the second trace 410 more tightly, and is not easy to separate.
Specifically, in the embodiment of the present application, the shape of the via hole 110 may be a circle, and of course, the shape of the via hole 110 may also be a polygon (triangle, quadrangle, pentagon, etc.), an arc or other irregular patterns, which are not limited only herein.
Specifically, when the conductive paste is injected into the via hole 110, the via hole 110 is not easily filled with the conductive paste due to the small hole diameter of the via hole 110, and the prepared connection electrode 200 contains bubbles, which results in poor contact between the first trace 310 and the second trace 410. In order to solve the above problem, as shown in fig. 8 and 9, the step B1 further includes: a guide groove 120 is formed on the substrate 100, and the guide groove 120 communicates with the corresponding via hole 110. With this structure, in the subsequent step B2, as shown in fig. 10 and 11, when the conductive paste is injected into the via hole 110, air in the via hole 110 can be discharged from the diversion trench 120, which is beneficial to filling the via hole 110 with the conductive paste, thereby eliminating air bubbles in the connection electrode 200, facilitating the electrical connection of the first trace 310 and the second trace 410, and improving reliability.
Specifically, the diversion trench 120 penetrates through the substrate 100, and the aperture of the diversion trench 120 is smaller than that of the via hole 110. In the step B2, as shown in fig. 10 and 11, the conductive paste is filled in the via hole 110 by using an inkjet printing method, and the nozzle 500 ejects the conductive paste toward the via hole 110, and due to the action of gravity, the conductive paste overflows from the lower end of the via hole 110 and covers the lower end of the diversion trench 120, so that the lower end of the diversion trench 120 is closed; after the via hole 110 is filled with the conductive paste, the conductive paste overflows from the upper end of the via hole 110 covers the upper end of the diversion trench 120, and the conductive paste overflows from the upper end of the via hole 110 does not fill the diversion trench 120 because the aperture of the diversion trench 120 is smaller. In this embodiment, the conductive paste overflowing from the upper end of the via hole 110 forms the second conductive bump 220, and the conductive paste overflowing from the lower end of the via hole 110 forms the third conductive bump 230. In this embodiment, a portion of the conductive paste overflows from the via hole 110 to the guide groove 120, so that a portion of the first conductive block 210 of the connection electrode 200 manufactured later is disposed in the guide groove 120.
Specifically, as shown in fig. 6, 7, 12 and 13, the step B3 includes:
step B31, forming a first conductive layer 300 on one side of the substrate 100 to cover the substrate 100 and the second conductive block 220;
step B32, forming a second conductive layer 400 on the other side of the substrate 100 and covering the substrate 100 and the third conductive block 230;
step B33, performing patterning treatment on the first conductive layer 300 to obtain a first trace 310;
in step B34, the second conductive layer 400 is patterned to obtain a second trace 410. In this embodiment, the order of the step B31, the step B32, the step B33 and the step B34 may be appropriately adjusted, so long as the step B33 is ensured to follow the step B31, the step B34 follows the step B32, and the present invention is not limited thereto.
Specifically, in the above step B31 and step B33, the first conductive layer 300 and the second conductive layer 400 may be formed by physical vapor deposition, and of course, the manufacturing process of the first conductive layer 300 and the second conductive layer 400 may be appropriately modified according to the actual selection and specific requirements, which is not limited herein.
Specifically, the materials of the first trace 310 (the first conductive layer 300) and the second trace 410 (the second conductive layer 400) may be one or more materials selected from copper, molybdenum, aluminum, and titanium. It will be appreciated that the specific materials of the first trace 310 and the second trace 410 may be modified appropriately according to the actual situation selection and specific requirements, and are not limited thereto.
Referring to fig. 7 and 13, the embodiment of the present application further provides an array substrate manufactured by the above manufacturing method, where the array substrate includes a substrate 100, a connection electrode 200, a first trace 310 and a second trace 410, the substrate 100 is provided with a via 110, the connection electrode 200 includes a first conductive block 210 disposed in the via 110, a second conductive block 220 overlapped with one end of the first conductive block 210, and a third conductive block 230 overlapped with the other end of the first conductive block 210, and the second conductive block 220 and the third conductive block 230 are disposed outside the via 110; the first trace 310 is disposed on one side of the substrate 100, and the first trace 310 covers the substrate 100 and the second conductive block 220; the second trace 410 is disposed on the other side of the substrate 100, and the second trace 410 covers the substrate 100 and the third conductive block 230.
Specifically, in the array substrate of the present embodiment, the number of the via holes 110 may be multiple, and the number of the first wires 310 and the second wires 410 may be multiple, where each of the first wires 310 corresponds to one via hole 110 and one first wire 410. Of course, the number of the via holes 110, the first wires 310 and the second wires 410 may be appropriately adjusted according to the actual situation and the specific requirements, which is not limited herein.
Specifically, the array substrate includes a display area AA and a non-display area NA, and the via hole 110, the connection electrode 200, the first trace 310 and the second trace 410 are disposed in the non-display area NA, and are mainly used for implementing back binding of the driving IC, where the driving IC may be directly bound to the second trace 410, and may also be bound to the second trace 410 by a flexible circuit board, so as to facilitate implementation of a narrow frame or a borderless design.
Specifically, the aperture of the via 110 is greater than or equal to 20 microns, for example, the aperture of the via 110 may be 20 microns, 30 microns, 40 microns, 50 microns, 60 microns, 70 microns, 80 microns, 90 microns, 100 microns, or greater. Of course, the aperture of the via hole 110 may be adjusted in the present year according to the actual situation selection and specific requirement, which is not limited herein.
Specifically, in the array substrate of the embodiment of the present application, the material of the substrate 100 may be glass or polyimide, and of course, the material of the substrate 100 may be modified appropriately according to the actual situation and specific needs, which is not limited only herein.
Specifically, in the embodiment of the present application, since the aperture of the via hole 110 is smaller, the via hole 110 is a capillary, and in the process of forming the connection electrode 200, the via hole 110 is beneficial to the capillary phenomenon of the conductive paste, and the conductive paste cannot flow out from the via hole 110, so that the connection electrode 200 is stably adsorbed in the via hole 110.
Specifically, in the embodiment of the present application, since the conductive paste has fluid characteristics and gravity influence, the volume of the third conductive bump 230 is larger than the volume of the second conductive bump 220 in the manufactured connection electrode 200.
Specifically, in the array substrate of the embodiment of the present application, the material of the connection electrode 200 includes a polymer resin and nano conductive particles dispersed in the polymer resin.
Specifically, in the array substrate of the embodiment of the application, the high polymer resin is one or more materials selected from cellulose acetate butyrate, acrylic resin, melamine formaldehyde resin, polyamino resin, vinyl chloride-vinyl acetate copolymer resin, polyphenylene oxide resin and polyurethane resin. It will be appreciated that the particular materials of the polymeric resin may be suitably modified according to the actual selection and particular needs, and are not limited solely herein.
Specifically, the nano conductive particles are one or more materials selected from gold powder, silver powder, aluminum powder, copper powder, nickel powder, carbon nanotubes, graphite, graphene, carbon fibers and carbon black. It will be appreciated that the specific materials of the nano-conductive particles may be suitably modified according to the actual situation selection and specific needs, and are not limited solely herein.
Specifically, as shown in fig. 4, 5 and 7, the cross-sectional area of the second conductive bump 220 is larger than that of the first conductive bump 210, and the second conductive bump 220 is covered on the substrate 100. Under this structure, the exposed surface area of the connection electrode 200 is large, so that the contact area between the connection electrode 200 and the first trace 310 can be increased, so that the connection electrode 200 is more tightly contacted with the first trace 310, and is not easy to separate.
Specifically, the cross-sectional area of the third conductive bump 230 is larger than that of the first conductive bump 210, and the third conductive bump 230 covers the substrate 100. Under this structure, the exposed surface area of the connection electrode 200 is large, so that the contact area between the connection electrode 200 and the second trace 410 can be increased, so that the connection electrode 200 contacts the second trace 410 more tightly, and is not easy to separate.
Specifically, in the array substrate of the present embodiment, the shape of the via hole 110 may be circular, and of course, the shape of the via hole 110 may also be polygonal (triangle, quadrilateral, pentagon, etc.), arc-shaped or other irregular patterns according to the actual situation and specific requirements, which is not limited only herein.
Specifically, as shown in fig. 8 and 9, the substrate 100 is further provided with a diversion trench 120, and the diversion trench 120 is communicated with the corresponding via hole 110. With this structure, as shown in fig. 10 and 11, when the conductive paste is injected into the via hole 110, air in the via hole 110 can be discharged from the guide groove 120, which is advantageous to fill the via hole 110 with the conductive paste, thereby eliminating air bubbles in the connection electrode 200, facilitating the electrical connection of the first trace 310 and the second trace 410, and improving reliability.
Specifically, the diversion trench 120 penetrates through the substrate 100, and the aperture of the diversion trench 120 is smaller than that of the via hole 110. As shown in fig. 10 and 11, the via hole 110 is filled with the conductive paste by adopting an inkjet printing manner, the nozzle 500 ejects the conductive paste toward the via hole 110, and the conductive paste overflows from the lower end of the via hole 110 and covers the lower end of the diversion trench 120 due to the action of gravity, so that the lower end of the diversion trench 120 is closed; after the via hole 110 is filled with the conductive paste, the conductive paste overflows from the upper end of the via hole 110 covers the upper end of the diversion trench 120, and the conductive paste overflows from the upper end of the via hole 110 does not fill the diversion trench 120 because the aperture of the diversion trench 120 is smaller. In this embodiment, the conductive paste overflowing from the upper end of the via hole 110 forms the second conductive bump 220, and the conductive paste overflowing from the lower end of the via hole 110 forms the third conductive bump 230. In this embodiment, a portion of the conductive paste overflows from the via hole 110 to the guide groove 120, so that a portion of the first conductive block 210 of the connection electrode 200 manufactured later is disposed in the guide groove 120.
Specifically, the materials of the first trace 310 and the second trace 410 may be one or more materials selected from copper, molybdenum, aluminum, and titanium. It will be appreciated that the specific materials of the first trace 310 and the second trace 410 may be modified appropriately according to the actual situation selection and specific requirements, and are not limited thereto.
The foregoing describes in detail a method for manufacturing an array substrate and an array substrate provided in the embodiments of the present application, and specific examples are applied to describe the principles and embodiments of the present application, where the descriptions of the foregoing examples are only used to help understand the method and core ideas of the present application; meanwhile, those skilled in the art will have variations in the specific embodiments and application scope in light of the ideas of the present application, and the present description should not be construed as limiting the present application in view of the above.
Claims (8)
1. The manufacturing method of the array substrate is characterized by comprising the following steps of:
step B1, forming a via hole which is a capillary hole on a substrate, and forming a diversion trench on the substrate, wherein the diversion trench is communicated with the corresponding via hole;
step B2, filling conductive paste in the via hole to form a connection electrode, wherein the connection electrode comprises a first conductive block arranged in the via hole, a second conductive block lapped on one end of the first conductive block and a third conductive block lapped on the other end of the first conductive block, and the second conductive block and the third conductive block are arranged outside the via hole;
and B3, forming a first wire on one side of the substrate, forming a second wire on the other side of the substrate, wherein the first wire is covered on the substrate and the second conductive block, and the second wire is covered on the substrate and the third conductive block.
2. The method according to claim 1, wherein in the step B2, the cross-sectional area of the second conductive bump is larger than the cross-sectional area of the first conductive bump, and the second conductive bump is covered on the substrate; and/or the number of the groups of groups,
the cross-sectional area of the third conductive block is larger than that of the first conductive block, and the third conductive block covers the substrate.
3. The method of claim 1, wherein the via has a pore size greater than or equal to 20 microns.
4. The method according to claim 1, wherein in the step B1, the via hole is formed on the substrate by laser drilling;
in the step B2, the conductive paste is filled in the via hole by using an inkjet printing method.
5. An array substrate, characterized by comprising:
the substrate is provided with a via hole, the via hole is a capillary hole, and a diversion trench communicated with the via hole is formed on the substrate;
the connecting electrode comprises a first conductive block arranged in the via hole, a second conductive block lapped on one end of the first conductive block and a third conductive block lapped on the other end of the first conductive block, and the second conductive block and the third conductive block are arranged outside the via hole;
the first wiring is arranged on one side of the substrate and covers the substrate and the second conductive block; and
the second wiring is arranged on the other side of the substrate and covers the substrate and the third conductive block.
6. The array substrate of claim 5, wherein the cross-sectional area of the second conductive bump is greater than the cross-sectional area of the first conductive bump, the second conductive bump overlying the substrate.
7. The array substrate of claim 5, wherein the cross-sectional area of the third conductive bump is greater than the cross-sectional area of the first conductive bump, the third conductive bump overlying the substrate.
8. The array substrate of claim 5, wherein the aperture of the via is greater than or equal to 20 microns.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210076979.5A CN114446168B (en) | 2022-01-24 | 2022-01-24 | Manufacturing method of array substrate and array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210076979.5A CN114446168B (en) | 2022-01-24 | 2022-01-24 | Manufacturing method of array substrate and array substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114446168A CN114446168A (en) | 2022-05-06 |
| CN114446168B true CN114446168B (en) | 2024-02-09 |
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| CN202210076979.5A Active CN114446168B (en) | 2022-01-24 | 2022-01-24 | Manufacturing method of array substrate and array substrate |
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| JP2002368414A (en) * | 2001-06-11 | 2002-12-20 | Matsushita Electric Ind Co Ltd | Method and apparatus for manufacturing highly conductive wiring board, and wiring board |
| JP2003209359A (en) * | 2002-01-11 | 2003-07-25 | Dainippon Printing Co Ltd | Core board and its manufacturing method |
| JP2007103698A (en) * | 2005-10-05 | 2007-04-19 | Fujikura Ltd | Wiring board |
| CN101378634A (en) * | 2007-08-30 | 2009-03-04 | 株式会社电装 | Method of manufacturing multilayer printed circuit board |
| CN112712764A (en) * | 2019-10-24 | 2021-04-27 | 深圳市百柔新材料技术有限公司 | Method for manufacturing display panel |
| CN113327890A (en) * | 2021-04-21 | 2021-08-31 | 上海步哒科技合伙企业(有限合伙) | Manufacturing method of backboard, display panel and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9892816B2 (en) * | 2013-06-27 | 2018-02-13 | Heraeus Precious Metals North America Conshohocken Llc | Platinum containing conductive paste |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002368414A (en) * | 2001-06-11 | 2002-12-20 | Matsushita Electric Ind Co Ltd | Method and apparatus for manufacturing highly conductive wiring board, and wiring board |
| JP2003209359A (en) * | 2002-01-11 | 2003-07-25 | Dainippon Printing Co Ltd | Core board and its manufacturing method |
| JP2007103698A (en) * | 2005-10-05 | 2007-04-19 | Fujikura Ltd | Wiring board |
| CN101378634A (en) * | 2007-08-30 | 2009-03-04 | 株式会社电装 | Method of manufacturing multilayer printed circuit board |
| CN112712764A (en) * | 2019-10-24 | 2021-04-27 | 深圳市百柔新材料技术有限公司 | Method for manufacturing display panel |
| CN113327890A (en) * | 2021-04-21 | 2021-08-31 | 上海步哒科技合伙企业(有限合伙) | Manufacturing method of backboard, display panel and display device |
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| CN114446168A (en) | 2022-05-06 |
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