CN114445260A - Distributed GPU communication method and device based on FPGA - Google Patents

Abstract

The utility model relates to a distributed GPU communication method and device based on FPGA, the method is applied to a communication device, the communication device comprises a first FPGA processing chip, the first FPGA processing chip receives request information sent by GPU, the request information comprises a data storage address, data is read from the data storage address of the GPU, the data is sent to a server according to configuration information received from a remote resource scheduling center device, or the data is sent to a second FPGA processing chip according to the configuration information, the FPGA processing chip is used as a switching card between the GPU and the server, the coupling degree between the GPU and the server is reduced, a two-dimensional ring network topology can be formed with adjacent FPGA processing chips, the flexibility between the GPUs is greatly improved, and the time for mutual communication between the GPUs is reduced.

Description

Method and device for distributed GPU communication based on FPGA

technical field

The present application relates to the field of communication technologies, and in particular, to a method and device for FPGA-based distributed GPU communication.

Background technique

Graphics Processing Unit (GPU) is a dedicated graphics processing chip, which is an important computing chip whether it is used for graphics and image processing in the early days or is now widely used in the field of AI artificial intelligence computing. As a high-speed serial computer expansion bus standard (Peripheral Component Interconnect express, PCIe) device, the GPU is plugged into the slot of the server in the data center, and communicates with the host server and other GPU nodes through the PCIe interface.

Due to the tight coupling relationship between the GPU and the server through the PCIe interface, the GPU cannot run independently of the server, and the communication between GPUs across nodes can only be carried out by connecting the network card to the switch. The communication network topology is not flexible enough, data forwarding efficiency is low, and communication delays big time.

SUMMARY OF THE INVENTION

Based on this, it is necessary to provide a method and device for FPGA-based distributed GPU communication in view of the above technical problems. The FPGA processing chip is used as an adapter card between the GPU and the server, which not only reduces the coupling between the GPU and the server. , and can also form a two-dimensional ring network topology with adjacent FPGA processing chips, which greatly improves the flexibility of the communication network topology, reduces the time for mutual communication between GPUs, and improves data forwarding efficiency.

A first aspect provides a method for FPGA-based distributed GPU communication, the method is applied to a communication device, the communication device includes a first FPGA processing chip, and the first FPGA processing chip includes a first interface, a second interface, a first network an interface and a plurality of second network interfaces; the first interface of the first FPGA processing chip is communicatively connected to the GPU, the second interface of the first FPGA processing chip is communicatively connected to the server; the first network interface is communicatively connected to the remote resource scheduling center device; A plurality of second network interfaces are used for communication and connection with the second FPGA processing chip; the method includes:

Receive the request information sent by the GPU, and the request information includes the address of the data storage;

Read data from the data storage address of the GPU;

Send data to the server according to the configuration information received from the remote resource scheduling center device; or send data to the second FPGA processing chip according to the configuration information.

In a possible implementation manner, the first FPGA processing chip further includes a data processing module, and the data processing module includes a GPU direct data access unit; reading data from a data storage address of the GPU includes:

Data is read from the data storage address of the GPU through the GPU direct data access unit.

In a possible implementation manner, the first FPGA processing chip further includes a bridge module; before sending data to the server according to the configuration information received from the remote resource scheduling center device; or before sending data to the second FPGA processing chip according to the configuration information , the method also includes:

Receive the configuration information sent by the remote resource scheduling center equipment through the bridge module.

In a possible implementation manner, the configuration information includes first indication information; sending data to the server according to the configuration information includes:

According to the first indication information, data is sent to the server.

In a possible implementation manner, the configuration information includes second indication information; sending data to the second FPGA processing chip according to the configuration information includes:

According to the second indication information, data is sent to the second FPGA processing chip.

In a possible implementation manner, the data processing module further includes an operation unit, and the configuration information further includes information of the operation rule and information of the target network interface; according to the second indication information, sending data to the second FPGA processing chip includes:

According to the second indication information, the operation unit uses the operation rule to process the data to obtain the processing result;

The data is sent to the second FPGA processing chip through the target network interface among the plurality of second network interfaces.

In a second aspect, an FPGA-based distributed GPU communication device is provided, the device includes a first FPGA processing chip, and the first FPGA processing chip includes a first interface, a second interface, a first network interface, and a plurality of first network interface; the first interface of the first FPGA processing chip is communicatively connected to the GPU, the second interface of the first FPGA processing chip is communicatively connected to the server; the first network interface is communicatively connected to the remote resource scheduling center device; a plurality of second network interfaces It is used to communicate and connect with the second FPGA processing chip; the first FPGA processing chip is used for:

Receive request information sent by the GPU through the first interface, where the request information includes the address of the data storage;

Read data from the data storage address of the GPU;

Send data to the server according to the configuration information received from the remote resource scheduling center device through the first network interface; or send data to the second FPGA processing chip according to the configuration information. The device communication connection; the second network interface is used to communicate with the second FPGA processing chip communication connection.

In a possible implementation manner, the first FPGA processing chip further includes a data processing module, and the data processing module includes a GPU direct data access unit; the first FPGA processing chip is specifically used for:

Data is read from the data storage address of the GPU through the GPU direct data access unit.

In a possible implementation manner, the first FPGA processing chip further includes a bridge module; the first FPGA processing chip is specifically used for:

Receive the configuration information sent by the remote resource scheduling center equipment through the bridge module.

In a possible implementation manner, the configuration information includes first indication information; the first FPGA processing chip is specifically used for:

According to the first indication information, data is sent to the server.

The above-mentioned FPGA-based distributed GPU communication method and device, by receiving the request information sent by the GPU, the request information including the data storage address, reading data from the data storage address of the GPU, according to the configuration received from the remote resource scheduling center equipment The information sends data to the server, or sends data to the second FPGA processing chip according to the configuration information. The FPGA processing chip acts as an adapter card between the GPU and the server, which not only reduces the coupling between the GPU and the server, but also reduces the server-side CPU, The overhead of resources such as memory and network can also form a two-dimensional ring network topology with adjacent FPGA processing chips, which greatly improves the flexibility between GPUs and reduces the time for mutual communication between GPUs.

Description of drawings

1 is an application environment diagram of an FPGA-based distributed GPU method in an embodiment of the application;

Fig. 2 is the structural block diagram of the first FPGA processing chip in one embodiment;

FIG. 3 is a schematic flowchart of an FPGA-based distributed GPU method in one embodiment.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application will be described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

In the prior art, the GPUDirect series is a GPU direct memory access technology, which allows the GPU to access the memory of other sub-devices or the host through the PCIe chipset bus system, thereby reducing unnecessary memory copies and reducing the cost of the central processing unit (Central Processing Unit). Unit, CPU) usage overhead to improve data transmission efficiency. Among them, GPUDirectShared Memory is a technology of GPUDirect series that directly shares memory between GPUs, which enables GPU and other PCIe devices to share memory pages of the host to realize data communication between different PCIe devices.

GPUDirect P2P is a technology of GPUDirect series that directly shares video memory between GPUs. It means that two GPU devices in the same PCIe Root Complex (PCIe RC) domain directly access GPU video memory, and there is no need to copy data between GPUs. Compared with the GPUDirect Shared Memory technology, the transfer to the host memory reduces the steps of copying data from the GPU memory to the host memory and from the host memory to the GPU memory, reducing the data path delay and improving the data transmission efficiency.

GPU Direct Remote Direct Memory Access (GPUDirect RDMA) technology uses RDMA-related technologies, physical network cards and transmission networks to realize direct interaction of video memory data between GPUs. This technology solves the problem of large processing delays in the traditional network data transmission process. , the problem of high CPU usage, and realizes the function of directly accessing GPU memory between different nodes.

GPUDirect Shared Memory technology and GPUDirect P2P technology are both developed and implemented based on GPU as a PCIe device under the host computer. Communication with other devices relies on the participation of CPU, host memory and PCIe switching system. The device and server CPU, memory, etc. are tightly coupled through PCIe to communicate Limited to GPUs within a single node. When using the GPUDirect SharedMemory technology to exchange video memory data between GPUs in a single node, it needs to pass through each CPU and CPU1 memory modules, resulting in high CPU overhead and large data transmission processing delays. When GPUDirect P2P technology is used to exchange video memory data between GPUs, it is limited to the direct interaction of video memory data between GPUs in the same PCIe RC domain through the PCIe chipset. If the PCIe RC domains of two CPUs span two CPUs, the CPU and CPU memory are also required to participate in data transmission. , resulting in a large amount of video memory data interaction delay and CPU overhead between GPUs.

Although GPUDirect RDMA technology uses RDMA technology to realize the problem of GPU communication between nodes, it requires high-performance network cards and local server CPUs in the same PCIe domain to participate in helping the GPU to complete data transmission across nodes. The GPU and the server are still through PCIe Due to the tight coupling relationship of the connection, the GPU cannot run independently of the server, and the communication between GPUs across nodes can only be carried out by connecting the network card to the switch. The communication network topology is not flexible enough, the data packet forwarding efficiency is low, and the communication delay is large.

In order to solve the problems in the prior art, the embodiments of the present application provide a method and apparatus for FPGA-based distributed GPU communication. The following first introduces the FPGA-based distributed GPU communication method provided by the embodiment of the present application. The method is applied to the application environment shown in FIG. 1 . As shown in FIG. 1 , the communication device 100 includes a plurality of FPGA processing chips. Each FPGA processing chip includes multiple network interfaces, wherein the first network interface 230 is communicatively connected to the remote resource scheduling center device through a switch, and the second network interface 240 forms a 2D ring communication topology with other surrounding FPGA processing chips. The number can be adjusted according to user needs, not limited to 4. The FPGA processing chip can send data to the adjacent FPGA processing chip through the second network interface 240, or receive data sent by the adjacent FPGA processing chip. The first network interface and the second network interface are 100G network optical ports, enabling efficient communication between GPUs and between GPUs and remote resource scheduling center equipment.

Any one of the FPGA processing chips is defined as the first FPGA processing chip, the FPGA processing chip connected to the first FPGA processing chip is defined as the second FPGA processing chip, and the first FPGA processing chip and the second FPGA processing chip have the same structure .

As shown in FIG. 2 , the first FPGA processing chip 200 includes a first interface 210, a second interface 220, a first network interface 230 and a plurality of second network interfaces 240; the first interface 210 of the first FPGA processing chip communicates with the GPU The second interface 220 of the first FPGA processing chip 200 is communicatively connected to the server; the first network interface 230 is communicatively connected to the remote resource scheduling center device; a plurality of second network interfaces 240 are used to communicate with the second FPGA processing chip.

The first FPGA processing chip 200 further includes an instruction configuration module 270, a routing module 280, a first transceiver module 290, and a second transceiver module 2100, wherein the first transceiver module 290 is a RoCE transceiver module, which is connected to the second network interface 240 and the routing module. 280 communication connection, receive the data packet from the adjacent FPGA processing chip through the RoCE protocol, parse the data packet, package the data of the first FPGA processing chip, and send the data packet to the adjacent FPGA processing chip.

The second transceiver module 2100 is a RoCEv2 transceiver module, which is in communication connection with the first network interface 230, the routing module 280 and the instruction configuration module 270, and receives configuration information sent by the remote resource scheduling center equipment to the first network interface 230 through the RoCEv2 protocol, and Parse the configuration information, and distribute the parsing results to the corresponding modules, for example, send the information of the algorithm to the instruction configuration module 270 to complete tasks such as registration and initialization of GPU resources. At the same time, the GPU data connected to the first FPGA processing chip can also be packaged, and connected to the switch through the first network interface 230 to communicate with the GPUs connected to other FPGA processing chips.

After the first FPGA processing chip is powered on, the routing module 280 communicates with the adjacent FPGA processing chip through the second network interface 240, obtains the MAC address information of the second network interface 240 of the adjacent FPGA processing chip and saves it in the memory , in order to communicate via the RoCE protocol.

FIG. 3 shows a schematic flowchart of a method for providing FPGA-based distributed GPU communication according to an embodiment of the present application. As shown in Figure 3, the method may include the following steps:

S310: Receive request information sent by the GPU, where the request information includes a data storage address.

Before performing data communication, the remote resource scheduling center equipment initializes the communication device, sends the data to be processed to the GPU through the server, and the GPU processes the received data, saves the processed data, and sends request information to the communication device. So that the communication device transmits the data saved by the GPU. Wherein, the request information includes a data storage address, so that the communication device can accurately obtain the data to be transmitted by the GPU.

The communication device receives the request information sent by the GPU through the first interface 210 of the first FPGA processing chip 200, wherein the first interface 210 is a PCIe interface, and is connected with the PCIe interface of the GPU in Root Point mode using the Gen5x16 standard golden finger.

S320, read data from the data storage address of the GPU.

The first FPGA processing chip uses the Direct Memory Access (Direct Memory Access, DMA) method to read data from the data storage address in the GPU display memory according to the received data storage address, so that the data transmission delay is small, Improve data read efficiency.

S330: Send data to the server according to the configuration information received from the remote resource scheduling center device; or send data to the second FPGA processing chip according to the configuration information.

The configuration information includes switching information, which determines the transmission path of the data. When the switching information is communicated by the GPU to the server, the first FPGA processing chip sends data to the server through the second interface 220. The communication device of the processing chip reduces the coupling between the GPU and the server and facilitates the independent pool management of the GPU. The second interface 220 is a PCIe interface in the Endpoint mode, and is connected to the PCIe interface of the GPU using the Gen5x16 standard to match the communication interface mode of the GPU.

When the switching information is that the GPU communicates with other FPGA processing chips, the first FPGA processing chip sends data to the second FPGA processing chip, and the GPU communicates with the GPU of other FPGA processing chips through multiple network interfaces of the FPGA processing chip. The network topology is more flexible . Communication with multiple FPGA processing chips through multiple network interfaces realizes simultaneous calculation and transmission of data in multiple dimensions, reduces the number of data calculation and transmission through the PCIe bus, reduces the time required for data update, and thus reduces data communication time overhead.

In the embodiment of the present application, by receiving request information sent by the GPU, the request information includes a data storage address, data is read from the data storage address of the GPU, and data is sent to the server according to the configuration information received from the remote resource scheduling center device, Or send data to the second FPGA processing chip according to the configuration information. The FPGA processing chip acts as an adapter card between the GPU and the server, which not only reduces the coupling between the GPU and the server, but also reduces the CPU, memory, network and other resources on the server side. It can also form a two-dimensional ring network topology with adjacent FPGA processing chips, which greatly improves the flexibility between GPUs and reduces the time for mutual communication between GPUs.

In some embodiments, the first FPGA processing chip further includes a data processing module 250, and the data processing module includes a GPU direct data access unit 251; reading data from the data storage address of the GPU includes:

The GPU direct data access unit 251 reads data from the data storage address in the GPU display memory, and the first FPGA processing chip 200 directly accesses the GPU internal display memory through PCIe and the GPU direct data access unit 251 to read the data to be transmitted, effectively Reduced communication latency between GPUs.

In some embodiments, the first FPGA processing chip 200 further includes a bridge module 260; before sending data to the server according to the configuration information received from the remote resource scheduling center device; or before sending data to the second FPGA processing chip according to the configuration information, Methods also include:

The configuration information sent by the remote resource scheduling center device is received through the bridge module 260 .

The bridge module 260 is connected to the instruction configuration module 270, the first interface 210, the second interface 220 and the data processing module, and the remote resource scheduling center device sends the configuration information to the first network interface 230 through the switch network, and the first network interface 230 pairs The configuration information is parsed to obtain the switching PCIe RC signal, and the switching PCIe RC signal is sent to the instruction configuration module 270. The instruction configuration module 270 judges the switching PCIe RC signal, and sends the judgment result to the bridge module 260, and the bridge module 260 according to the judgment result The connection relationship of the PCIe bus of the GPU can be switched.

In the initialization phase of the communication device, the remote resource scheduling center device sends configuration information to the first FPGA processing chip through the switch network, controls and switches the connection relationship of the PCIe bus of the GPU, determines the data transmission path, flexibly selects the data transmission object in the GPU, and releases the GPU. Dependency on the server host.

In some embodiments, the configuration information includes first indication information; sending data to the server according to the configuration information includes:

According to the first indication information, data is sent to the server.

The instruction configuration module 270 receives the switch PCIe RC signal in the configuration information, parses it, and determines whether the value corresponding to the switch PCIe RC signal is 1 or 0. Wherein, the first indication information is 0, and when the analysis result of the configuration information is 0, the GPU exchanges data with the server, and the bridge module 260 directly sends the data to the server.

The configuration information includes second indication information; sending the data to the second FPGA processing chip according to the configuration information includes:

According to the second indication information, the data is sent to the second FPGA processing chip.

The second indication information is 1. When the analysis result of the configuration information is 1, the GPU and the second FPGA processing chip perform data exchange. The bridge module 260 first sends the data to the data processing module 250, and the data processing module 250 processes it. The processed data is sent to the first transceiver module 290 , and finally sent to the second FPGA processing chip through the second network interface 240 .

In some embodiments, the data processing module 250 further includes an operation unit 252, and the configuration information further includes information of the operation rules and information of the target network interface; according to the second indication information, sending data to the second FPGA processing chip includes:

According to the second indication information, the operation module uses the operation rule to process the data to obtain the processing result;

The data is sent to the second FPGA processing chip through the target network interface among the plurality of second network interfaces.

In the process of data interaction between the GPU and the second FPGA processing chip, if the receiving unit of the data processing module 250 does not receive the data to be processed sent by the FPGA processing chips corresponding to other GPUs, the instruction configuration module 270 controls the operation unit 252 according to the configuration information. Without any calculation, the data read from the GPU by the GPU direct data access unit 251 is directly sent to the sending unit 253, the sending unit 253 sends the data to the first transceiver module 290, and the first transceiver module 290 obtains from the routing module 280 The AMC address information of the target network interface in the configuration information is sent to other FPGA processing chips through the target network interface.

If the receiving unit of the data processing module receives the data to be processed sent by the FPGA processing chips corresponding to other GPUs, the instruction configuration module 270 controls the operation unit 252 to perform corresponding calculations according to the information of the operation rules, and the GPU direct data access unit 251 obtains the data from the GPU After the data is received, the data is sent to the operation unit 252, and the operation unit 252 performs mixed calculation on the data read by the GPU and the data sent by the FPGA processing chip received by the receiving unit 254 according to the preconfigured operation rules, and sends the calculation result to The sending unit 253, the sending unit 253 sends the data to the first transceiver module 290, and the first transceiver module 290 obtains the AMC address information of the target network interface in the configuration information from the routing module 280, and sends the AMC address information to other FPGA processing chips through the target network interface. The FPGA processing chip writes the data into the corresponding GPU video memory through the GPU direct data access unit 251 to complete the update iteration of the GPU data.

In one embodiment, an FPGA-based distributed GPU communication device is provided, the device includes a first FPGA processing chip, and the first FPGA processing chip includes a first interface, a second interface, a first network interface, and a plurality of the first network interface; the first interface of the first FPGA processing chip is communicatively connected to the GPU, the second interface of the first FPGA processing chip is communicatively connected to the server; the first network interface is communicatively connected to the remote resource scheduling center device; a plurality of second The network interface is used for communicating with the second FPGA processing chip; the first FPGA processing chip is used for:

Receive request information sent by the GPU through the first interface, where the request information includes the address of the data storage;

Read data from the data storage address of the GPU;

Send data to the server according to the configuration information received from the remote resource scheduling center device through the first network interface; or send data to the second FPGA processing chip according to the configuration information. The device communication connection; the second network interface is used to communicate with the second FPGA processing chip communication connection.

In the embodiment of the present application, the first FPGA processing chip is used as an adapter card between the GPU and the server, which not only reduces the coupling degree between the GPU and the server, but also forms a two-dimensional ring network topology with adjacent FPGA processing chips , which greatly improves the flexibility of the communication network topology, reduces the time for mutual communication between GPUs, and improves the efficiency of data forwarding.

In one embodiment, the first FPGA processing chip further includes a data processing module, and the data processing module includes a GPU direct data access unit; the first FPGA processing chip is specifically used for:

Data is read from the data storage address of the GPU through the GPU direct data access unit.

In one embodiment, the first FPGA processing chip further includes a bridge module; the first FPGA processing chip is specifically used for:

Receive the configuration information sent by the remote resource scheduling center equipment through the bridge module.

In one embodiment, the configuration information includes first indication information; the first FPGA processing chip is specifically used for:

According to the first indication information, data is sent to the server.

In some embodiments, the configuration information includes second indication information; the first FPGA processing chip is specifically used for:

According to the second indication information, data is sent to the second FPGA processing chip.

In some embodiments, the data processing module further includes an arithmetic unit, and the configuration information further includes information of an arithmetic rule and information of a target network interface; the first FPGA processing chip is specifically used for:

According to the second indication information, the operation unit uses the operation rule to process the data to obtain the processing result;

The data is sent to the second FPGA processing chip through the target network interface among the plurality of second network interfaces.

The technical features of the above embodiments can be combined arbitrarily. In order to make the description simple, all possible combinations of the technical features in the above embodiments are not described. However, as long as there is no contradiction in the combination of these technical features It is considered to be the range described in this specification.

The above-mentioned embodiments only represent several embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as a limitation on the scope of the invention patent. It should be noted that, for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which all belong to the protection scope of the present application. Therefore, the scope of protection of the patent of the present application shall be subject to the appended claims.

Claims (10)

1. a method for FPGA-based distributed GPU communication, wherein the method is applied to a communication device, and the communication device includes a first FPGA processing chip, and the first FPGA processing chip includes a first interface, a first two interfaces, a first network interface and a plurality of second network interfaces; the first interface of the first FPGA processing chip is communicatively connected to the GPU, and the second interface of the first FPGA processing chip is communicatively connected to the server; the first FPGA processing chip is communicatively connected to the server; A network interface is in communication connection with the remote resource scheduling center device; the plurality of second network interfaces are used for communication connection with the second FPGA processing chip; the method includes: Receive request information sent by the GPU, where the request information includes an address for data storage; read data from the data storage address of the GPU; Send the data to the server according to the configuration information received from the remote resource scheduling center device; or send the data to the second FPGA processing chip according to the configuration information. 2. The method according to claim 1, wherein the first FPGA processing chip further comprises a data processing module, and the data processing module comprises a GPU direct data access unit; Read data from the data storage address, including: Data is read from the data storage address of the GPU by the GPU direct data access unit. 3. The method according to claim 1 or 2, wherein the first FPGA processing chip further comprises a bridge module; sending the data; or before sending the data to the second FPGA processing chip according to the configuration information, the method further includes: The configuration information sent by the remote resource scheduling center device is received by the bridge module. 4. The method according to claim 3, wherein the configuration information comprises first indication information; sending the data to the server according to the configuration information comprises: The data is sent to the server according to the first indication information. 5. The method according to claim 3, wherein the configuration information comprises second indication information; sending the data to the second FPGA processing chip according to the configuration information comprises: According to the second indication information, the data is sent to the second FPGA processing chip. 6 . The method according to claim 5 , wherein the data processing module further comprises an arithmetic unit, and the configuration information further comprises arithmetic rule information and target network interface information; information, sending the data to the second FPGA processing chip, including: According to the second indication information, the operation unit uses the operation rule to process the data to obtain a processing result; The data is sent to the second FPGA processing chip through the target network interface of the plurality of second network interfaces. 7. A device for FPGA-based distributed GPU communication, wherein the device includes a first FPGA processing chip, and the first FPGA processing chip includes a first interface, a second interface, a first network interface and multiple a first network interface; the first interface of the first FPGA processing chip is communicatively connected to the GPU, and the second interface of the first FPGA processing chip is communicatively connected to the server; the first network interface is connected to a remote resource scheduling center device communication connection; the plurality of second network interfaces are used for communication connection with the second FPGA processing chip; the first FPGA processing chip is used for: Receive request information sent by the GPU through the first interface, where the request information includes an address for data storage; read data from the data storage address of the GPU; Send the data to the server according to the configuration information received from the remote resource scheduling center device through the first network interface; or send the data device communication to the second FPGA processing chip according to the configuration information connection; the second network interface is used for communication and connection with the second FPGA processing chip. 8. The device according to claim 7, wherein the first FPGA processing chip further comprises a data processing module, and the data processing module comprises a GPU direct data access unit; the first FPGA processing chip specifically uses At: Data is read from the data storage address of the GPU by the GPU direct data access unit. 9. The device according to claim 7 or 8, wherein the first FPGA processing chip further comprises a bridge module; the first FPGA processing chip is specifically used for: The configuration information sent by the remote resource scheduling center device is received by the bridge module. 10. The apparatus according to claim 9, wherein the configuration information comprises first indication information; and the first FPGA processing chip is specifically used for: The data is sent to the server according to the first indication information.

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