CN114420196B - Semiconductor chip testing methods - Google Patents
Semiconductor chip testing methodsInfo
- Publication number
- CN114420196B CN114420196B CN202210050634.2A CN202210050634A CN114420196B CN 114420196 B CN114420196 B CN 114420196B CN 202210050634 A CN202210050634 A CN 202210050634A CN 114420196 B CN114420196 B CN 114420196B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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Abstract
本发明涉及一种半导体芯片的测试方法，所述半导体芯片中包括至少一个逻辑单元，每个所述逻辑单元中包括多个逻辑块，每个所述逻辑块包括多个逻辑页，每个所述逻辑页包括多个逻辑列，其特征在于，包括：启动测试程序，所述测试程序包括预设的地址规则，在所述地址规则中，用第一坐标表示所述多个逻辑页的地址，用第二坐标表示所述多个逻辑块的地址，用寄存器表示所述多个逻辑列的地址；读取测试文件，所述测试文件中包括待测试对象的地址；以及所述测试程序根据所述地址规则对所述待测对象进行定位和测试。本发明的测试方法降低了不同产品、同类型测试的开发成本和开发周期。
This invention relates to a testing method for semiconductor chips. The semiconductor chip includes at least one logic unit, each logic unit includes multiple logic blocks, each logic block includes multiple logic pages, and each logic page includes multiple logic columns. The method comprises: starting a test program, the test program including preset address rules, wherein the addresses of the multiple logic pages are represented by first coordinates, the addresses of the multiple logic blocks are represented by second coordinates, and the addresses of the multiple logic columns are represented by registers; reading a test file, the test file including the address of the object to be tested; and the test program locating and testing the object to be tested according to the address rules. This invention reduces the development cost and development cycle for different products and similar tests.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing, and more particularly, to a method for testing a semiconductor chip.
Background
With the development of microelectronic technology, the application range of semiconductor chips is becoming wider and wider, and products related to semiconductor chips are going deep into aspects of people's life from daily life to professional fields. With the development of technology, new requirements are put on the reliability of related products. In order to ensure reliability of semiconductor products, it is necessary to perform reliability tests such as burn-in tests, high and low temperature tests, etc. on the semiconductor chips and their related products before the semiconductor chips are shipped.
Disclosure of Invention
The invention aims to provide a method for testing a semiconductor chip, which has strong reusability and good expandability.
The technical scheme adopted by the invention for solving the technical problems is that the semiconductor chip comprises at least one logic unit, each logic unit comprises a plurality of logic blocks, each logic block comprises a plurality of logic pages, and each logic page comprises a plurality of logic columns, and the method is characterized by comprising the steps of starting a test program, wherein the test program comprises a preset address rule, in the address rule, a first coordinate is used for representing the addresses of the plurality of logic pages, a second coordinate is used for representing the addresses of the plurality of logic blocks, a register is used for representing the addresses of the plurality of logic columns, reading a test file, the test file comprises the addresses of objects to be tested, and positioning and testing the objects to be tested according to the address rule.
In an embodiment of the invention, the first coordinate is an abscissa and the second coordinate is an ordinate.
In an embodiment of the present invention, the first coordinate includes a first number of bits of a logical page, and in the test file, an address of the logical page where the object to be tested is located is obtained by setting each bit of the logical page.
In an embodiment of the present invention, the second coordinate includes a second number of bits of a logical block, and an address of the logical block where the object to be tested is located is obtained by setting each bit of the logical block in the test file.
In an embodiment of the invention, in the address rule, addresses of the plurality of logical units are also represented by the second coordinates.
In an embodiment of the present invention, the second coordinate includes a third number of bits of a logic unit, and in the test file, an address of the logic unit where the object to be tested is located is obtained by setting each bit of the logic unit.
In an embodiment of the present invention, the register includes a fourth number of bits of a logical column, and in the test file, an address of the logical column where the object to be tested is located is obtained by setting each bit of the logical column.
In an embodiment of the present invention, when the actual number of logical pages of the object to be tested is greater than the first number, updating the address rule in the test program so that the number of logical page bits in the first coordinate is equal to the actual number.
In an embodiment of the invention, the semiconductor chip is a memory chip, the logical page corresponds to a word line in the memory chip, and the logical column corresponds to a bit line in the memory chip.
In an embodiment of the present invention, the test program is used for a machine that performs a reliability test on the semiconductor chip.
The testing method of the invention presets specific address rules in the testing program, adopts different coordinates to respectively address the logical page and the logical block, so that the testing program is suitable for a plurality of different semiconductor products, the expansibility of the testing program is strong, and the development cost and the development period of different products and the same type of tests are reduced.
Drawings
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below, wherein:
FIG. 1 is an exemplary flow chart of a method of testing a semiconductor chip in accordance with one embodiment of the present invention;
Fig. 2 is an exemplary flowchart of a method of testing a semiconductor chip according to another embodiment of the present invention.
Detailed Description
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than as described herein, and therefore the present invention is not limited to the specific embodiments disclosed below.
As used in the specification and in the claims, the terms "a," "an," "the," and/or "the" are not specific to a singular, but may include a plurality, unless the context clearly dictates otherwise. In general, the terms "comprises" and "comprising" merely indicate that the steps and elements are explicitly identified, and they do not constitute an exclusive list, as other steps or elements may be included in a method or apparatus.
In describing embodiments of the present invention in detail, the cross-sectional view of the device structure is not partially exaggerated to a general scale for convenience of explanation, and the schematic drawings are only examples and should not limit the scope of the present invention herein. In addition, the three-dimensional dimensions of length, width and depth should be included in actual fabrication.
For ease of description, spatially relative terms such as "under", "below", "beneath", "above", "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary words "below" and "beneath" can encompass both an orientation of above and below. The device may have other orientations (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
In the context of the present application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.
In addition, the terms "first", "second", etc. are used to define the components, and are only for convenience of distinguishing the corresponding components, and the terms have no special meaning unless otherwise stated, and therefore should not be construed as limiting the scope of the present application.
The term "three-dimensional (3D) memory device" as used herein refers to a semiconductor device having a string of memory cell transistors (referred to herein as a "memory string," e.g., a NAND string) oriented vertically on a laterally oriented substrate such that the memory string extends in a vertical direction relative to the substrate. As used herein, the term "vertically" means nominally perpendicular to a lateral surface of a substrate.
A flowchart is used in the present application to describe the operations performed by a system according to embodiments of the present application. It should be understood that the preceding or following operations are not necessarily performed in order precisely. Rather, the various steps may be processed in reverse order or simultaneously. At the same time, other operations are added to or removed from these processes.
The method for testing the semiconductor chip can be used for testing the reliability of the semiconductor chip, is not limited to specific signals, functions, types and structures of the semiconductor chip, and comprises at least one logic unit, wherein each logic unit comprises a plurality of logic blocks, each logic block comprises a plurality of logic pages, and each logic page comprises a plurality of logic columns.
Fig. 1 is an exemplary flowchart of a method of testing a semiconductor chip according to an embodiment of the present invention. Referring to fig. 1, the test method of this embodiment includes the steps of:
Step S110, starting a test program, wherein the test program comprises a preset address rule, in the address rule, the addresses of a plurality of logic pages are represented by a first coordinate, the addresses of a plurality of logic blocks are represented by a second coordinate, and the addresses of a plurality of logic columns are represented by a register;
step S120, reading a test file including an address of the object to be tested, and
And 130, positioning and testing the object to be tested according to the address rule by the test program.
The above steps S110 to S130 are described in detail below.
In step S110, the semiconductor chip is typically tested on a specific machine. Different test machines may be used for different test contents. The test program may be loaded into the test station.
The test procedure in step S110 includes preset address rules.
In some embodiments, the first coordinate is an abscissa and the second coordinate is an ordinate. The X represents the abscissa and Y represents the ordinate, and addresses of logical pages, logical blocks, and logical columns can be set in the test program.
In other embodiments, the first coordinate is an ordinate and the second coordinate is an abscissa.
The registers in the address rules may be a type of registers provided by the test equipment that may be edited and used by the user. The present invention does not limit the number of registers.
Two address setting manners for the semiconductor chips a and B, respectively, are given below, which correspond to address rules different from those in step S110.
Address setting mode of the semiconductor chip a:
BBM_PAGE=_ADDR(X0,X1,X2,X3,X4,X5,X6,X7,X8,X9,X10);
BBM_BLOCK=_ADDR(X11,X12,X13,X14,X15,X16,X17,X18,X19,X20,X21);
BBM_LUN=_ADDR(X23).
address setting mode of the semiconductor chip B:
BBM_PAGE=_ADDR(X0,X1,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11);
BBM_BLOCK=_ADDR(X12,X13,X14,X15,X16,X17,X18,X19,X20,X21,X22);
BBM_LUN=_ADDR(X23).
Wherein bbm_page represents a logical PAGE, bbm_block represents a logical BLOCK, and bbm_lun represents a logical unit.
In the address setting of the semiconductor chip a, the address of the logical page thereof is represented by 11-bit X coordinates (X0: X10), the semiconductor chip a may have 2 11 =2048 logical pages, the address of the logical block thereof is represented by 11-bit X coordinates (X11: X21), the semiconductor chip a may have 2 11 =2048 logical blocks, and the address of the logical unit thereof is represented by 1-bit X coordinates (X23), and the semiconductor chip a may have 2 1 =2 logical units.
Similarly to the semiconductor chip a, in the address setting of the semiconductor chip B, the address of its logical page is represented by a 12-bit X coordinate (X0: X11), the semiconductor chip B may have 2 12 =4096 logical pages, the address of its logical block is represented by a 11-bit X coordinate (X12: X22), the semiconductor chip B may have 2 11 =2048 logical blocks, and the address of its logical unit is represented by a 1-bit X coordinate (X23), and the semiconductor chip B may have 2 1 =2 logical units.
In the address rule of the above-described semiconductor chips a and B, addresses of the logical pages, logical blocks, and logical units are set using only X coordinates, and addresses of the logical columns are also expressed using Y coordinates. Thus, when the test is performed, the address of the object to be tested can be known by reading the X coordinate and the Y coordinate in the test file. For example, the object to be tested is located in the 2 nd logic unit (Lun 2), the 5 th logic Block (Block 5), the 5 th logic Page (Page 5), and the 1 st logic Column (Column 1) of the semiconductor chip a. Then, according to the address setting mode of the semiconductor chip a above, the following are assigned to the X coordinate and the Y coordinate in the test file:
X0=1,X1=0,X2=1,X3=0;
X11=1,X12=0,X13=1,X14=0;
X23=0.
Y=0.
the test program reads the test file according to the address rule of the semiconductor chip A, so that the test program can locate the object to be tested and execute the test process.
However, the address rule described above has the following problems:
(1) The addresses of the logical pages, logical blocks and logical units are represented by X coordinates, and the relevant addresses need to be adjusted for different semiconductor chips when the number of bits of some of the addresses changes. For example, if the address rule in the test program is that of the semiconductor chip a, when the semiconductor chip B is to be tested, the number of bits of the logical page is changed from 11 bits to 12 bits, and then the total number of bits in the logical page is changed. This results in a large modification of the test procedure and is also prone to error, possibly leading to failure of the entire test.
(2) Due to the problem (1), different test programs need to be designed for different products, and development difficulty of the test programs is increased.
The present invention solves the above-mentioned problems by setting address rules to represent logical pages and logical blocks with different coordinates in step S110.
In some embodiments, the first coordinate includes a first number of logical page bits, and an address of a logical page where the object to be tested is located is obtained in the test file by setting each logical page bit.
In some embodiments, the second coordinate includes a second number of logical block bits, and an address of a logical block where the object to be tested is located is obtained by setting each logical block bit in the test file.
In some embodiments, in the address rule, the addresses of the plurality of logical units are also represented by second coordinates.
In some embodiments, the second coordinate includes a third number of logical unit bits, and an address of a logical unit where the object to be tested is located is obtained in the test file by setting each logical unit bit.
In some embodiments, the register includes a fourth number of logical column bits, and the address of the logical column in which the object to be tested is located is obtained in the test file by setting each logical column bit.
The present invention is not limited to the specific amounts of the first amount, the second amount, the third amount, and the fourth amount.
The above embodiments will be described by taking the first coordinate as the abscissa and the second coordinate as the ordinate as an example. According to the above embodiment, the address rule in step S110 is as follows:
BBM_PAGE=_ADDR(X0,X1,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11);
BBM_BLOCK=_ADDR(Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7,Y8,Y9,Y10,Y11,Y12);
BBM_LUN=_ADDR(Y13,Y14,Y15).
Wherein, the address of the logical page is represented by 12-bit X coordinates (X0: X11), the semiconductor chip to be tested can have 2 12 =4096 logical pages, the address of the logical block is represented by 13-bit Y coordinates (Y0: Y12), the semiconductor chip to be tested can have 2 13 =8192 logical blocks, the address of the logical unit is represented by 3-bit Y coordinates (Y13: Y15), and the semiconductor chip to be tested can have 2 3 =8 logical units.
In the above embodiment, the first number is 12, the first coordinate includes 12 bits of logical page bits, the second number is 13, the second coordinate includes 13 bits of logical block bits, the third number is 3, and the second coordinate further includes 3 bits of logical cell bits.
In an embodiment of the invention, the addresses of the logical block and the logical unit are set using the same coordinates, the addresses of the logical unit follow the addresses of the logical block.
The address rule described above is only an example, and is not intended to limit the number of bits of the first coordinate and the second coordinate in the address rule in step S110 of the present invention. The invention does not limit the number of bits of the register.
Referring to fig. 1, in step S120, a test file including an address of an object to be tested is read.
The invention does not limit how to read the test file. The test file may be read using the test program in step S110. The test file is written by a tester according to the test purpose, wherein the test file can also comprise test contents and the like besides the address of the object to be tested, and the invention is not limited to the test file.
In some embodiments, the test file is a file with a suffix name csv.
Referring to fig. 1, in step S130, the test program locates and tests the object to be tested according to the address rule.
In step S130, the test program may use the first coordinate to represent the address of the logical page of the object to be tested, the second coordinate to represent the address of the logical block of the object to be tested, or the second coordinate to represent the addresses of the logical block and the logical unit of the object to be tested, and the register to represent the address of the logical column of the object to be tested according to the address of the object to be tested and the address rule, so that the test machine can be positioned to the object to be tested and the test process can be executed on the object to be tested.
According to the test method provided by the invention, the reusability of the test program is enhanced. For different products, such as the semiconductor chips A and B, only a small amount of adjustment is needed, the code development is simple, and the execution efficiency is high. For example, continuing with the above-described embodiment, when the first number of logical page bits of the semiconductor chip to be tested changes, only the portion of the address rule associated with the logical page address need be modified, and no other portion need be modified.
In some embodiments, the test method of the present invention further comprises updating the address rule in the test program such that the number of logical page bits in the first coordinate is equal to the actual number when the actual number of logical pages of the object under test is greater than the first number. Taking the above example as an example, assuming that the actual number of logical PAGEs of the object to be tested is 2 13 =8192, only the bbm_page needs to be modified to:
BBM_PAGE=_ADDR(X0,X1,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12).
no modification of other BBM BLOCK and BBM LUN is required.
In some embodiments, the semiconductor chip to which the test method of the present invention relates is a memory chip, the logical page corresponds to a word line in the memory chip, and the logical column corresponds to a bit line in the memory chip.
The present invention does not limit the type of memory chip.
In some embodiments, the memory chip is a 3D NAND.
In some embodiments, the test program of the present invention is used in a machine for performing reliability tests on semiconductor chips. The reliability test content may include burn-in tests, environmental reliability tests, functional reliability tests, memory cell characteristics tests, and the like. Specifically, for example, single page read disturb (SPRD, SINGE PAGE READ disturb), block read disturb (BLRD, block read disturb), low temperature data retention (LTDR, low temperature data reterntion), low temperature operation lifetime (LTOL, low temperature operation life).
Fig. 2 is an exemplary flowchart of a method of testing a semiconductor chip according to another embodiment of the present invention. Fig. 2 shows a specific example of a test procedure performed according to the test method of the present invention. Referring to fig. 2, the test method includes the steps of:
Step S210, starting a test program.
The test program is a test program as in step S110, and includes a preset address rule. Before starting the test program, and loading the test degree in the test machine.
Step S220, judging whether the SPRD.csv file exists, if yes, executing step S230, and if not, executing step S240.
The SPRD.csv file is a test file written by a tester, whose file name indicates that the test file is used to perform a single page read disturb test. The test file may include addresses of the objects to be tested, such as addresses of logical units, logical blocks, logical pages, logical columns, etc. where the memory units to be tested are located. A test sequence of a plurality of memory cells to be tested, an applied voltage for performing a read disturb, etc. may also be included.
And step S230, executing SPRD test.
In this step, the SPRD test is performed according to the content of the SPRD.csv file.
Step S240, judging whether a BLRD.csv file exists, if yes, executing step S250, and if not, executing step S260.
Similar to step S220, the blrd.csv file is a test file written by a tester, and its file name indicates that the test file is used for performing a block read disturb test. The test file may include addresses of the objects to be tested, such as addresses of logical units, logical blocks, logical pages, logical columns, etc. where the memory units to be tested are located. The test sequence of a plurality of memory cells to be tested, the applied voltage for performing the block read disturb, and the like can also be included.
Step S250, executing other operations. May be an end.
After the test execution in step S230 and step S250 is completed, the program may be ended, or the test file may be continuously read, and the next test may be performed.
According to the testing method, the pin formats (pin formats) can be uniformly coded according to the set address rules for different semiconductor products, and the pin correspondence is unified, so that one testing program can be applied to a plurality of different semiconductor products. Moreover, the test program has strong expansibility, and reduces development cost and development period of different products and tests of the same type.
While the application has been described with reference to the specific embodiments presently, it will be appreciated by those skilled in the art that the foregoing embodiments are merely illustrative of the application, and various equivalent changes and substitutions may be made without departing from the spirit of the application, and therefore, all changes and modifications to the embodiments are intended to be within the scope of the appended claims.
Claims (10)
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