JPH08263035A - Pixel cache circuit - Google Patents

Abstract

PURPOSE: To improve the bandwidth of a picture memory by providing a FIFO in between a cache and the picture memory. CONSTITUTION: A vector or an interpolation point coordinate value are outputted in a DDA 1 and pixels consisting of color information are added to the coordinated point. The pixels are temporarily stored in a pixel cache 2 by the low- order address of the DDA. When the cache is overflown with the operation of the DDA, m×n pixels are loaded into a FIFO 3 with one operation. Outputs of the FIFO 3 are connected to a picture memory 5 via ordinary logical arithmetic circuits 4. Pixels and block addresses of the cache are respectively stored in a FIFO 3a and FIFO 3b. When data (pixels and addresses) are sequentially loaded from the side of the DDA 1, the look-ahead of the FIFO is continuously performed in a page detecting circuit 6.

Description

Detailed Description of the Invention

The present invention relates to a structure for writing pixels to a high-speed image memory in a computer graphics processor, and the pixels are stored in a cache memory and FI.
The data is temporarily stored in an FO (First In First Out), and continuous in-page data accumulated in the FIFO is written in the image memory by using the page mode.

[Prior Art] Geometrical information such as coordinate values and its attributes is converted into pixels as screen information,
Further, in the rendering process of writing the pixels to the image memory, in order to equivalently increase the bandwidth of the image memory bus, the conventional pixel cache (Pixel) is used.
A buffer called Cache) for pixel conversion
DA (Digital Differential A)
It is provided between an image memory and an image memory, a predetermined amount of pixels are stored in the image memory at high speed, and then these are collectively transferred to the image memory. When drawing with different slopes such as vector line display, the cache hit rate (the rate at which a straight line passes through the cache) differs depending on the slope, and the cache size is m × n.
In the two-dimensional array, the amount of pixels stored in the cache is from 1 pixel at the minimum to m pixels at the maximum (m ≧ n). On the other hand, as the image memory, a DRAM is usually used, but the access time for each of them is constant regardless of the pixel amount. As a result, the bandwidth has been determined by the amount that can be collectively transferred to the image memory. Further, there is a conventional structure in which a FIFO is provided between the image memory and the DDA. However, compared with the combination of the two-dimensional array cache and the FIFO of the present invention, in the vector drawing using only the FIFO, the DDA and the FIFO have one. Dimensional writing is used, and the performance is poor due to the occurrence of waiting time in the transfer method. Also DDA
If the cache overflow rate from the memory exceeds the transfer rate to the image memory, the FIFO will eventually become full and a long vector will not have a significant effect. The present invention has been made in view of the above problems, and improves the writing speed of pixels to the image memory, that is, the bandwidth is equivalently improved under the condition that the physical bus width is constant. is there.

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a FIFO (First In First Ore) between a cache and an image memory.
ut), not only the pixels are stored in this FIFO, but also the address of the image memory generated by the DDA is stored at the same time. When the cache overflows into the FIFO, its contents are immediately loaded and this operation is repeated until a predetermined capacity is reached. On the other hand, when the cache block (all contents stored in the cache) is loaded, it is detected at the output of the FIFO and transferred to the image memory to complete the writing. The most preferable condition is to send the loaded data to the image memory before the FIFO becomes full. The role of the FIFO in this structure is to expand the cache size equivalently by the capacity of the FIFO. For this reason, in the present invention, a FIFO storing an address is used as a pixel FIFO.
By prefetching independently of O, it is detected whether the address is an address within a continuous page corresponding to the page mode of the image memory and the number of continuous addresses. If the address has page-mode accessible continuity (usually graphic data has locality)
The page mode access timing by the column address is requested to the image memory, and the pixel FIFO
O is read continuously in synchronization with this. The image memory is usually composed of DRAM, and this element has two address designations, a row address and a column address, and has a page mode in which a plurality of column addresses are designated for one row addressing. The X-axis and Y-axis addresses from the DDA belong to either the row or column address. Therefore, the address of the FIFO is read in advance,
Whether or not the address is within the page can be easily determined because only the column address is changed and the row address is not changed. If there is a change in row address,
When this data is written to the image memory as if it has gone out of the page area, row addressing is required again. The page address detection circuit counts the number of blocks belonging to a page, dynamically sets the number of page modes, and generates timing in the image memory based on the number to perform access. In the case of discontinuity, a row address is given for each access. The method of the present invention improves the bandwidth of the image memory by 20-40%.

[Embodiment] FIG. 1 shows a pixel cache structure according to the present invention. The DDA 1 outputs an interpolated point coordinate value for filling a vector or polygon, and a pixel having preset color information is attached to this coordinate point. This pixel is called a pixel, but this pixel is temporarily stored in the pixel cache 2 by the lower address of the DDA address. The upper address is the address of the image memory. Pixel cache is a two-dimensional array buffer m (X address)
It is composed of a RAM that can store pixels of × n (Y address) and that can access the image memory at high speed by one digit or more. When the cache overflows due to the operation of the DDA, usually m × n is batched or m bits are n.
Interleaved and transferred to image memory 5,
In the present invention, m × n pixels are collectively loaded into the FIFO 3. The FIFO is a memory that outputs its data in the order that it is loaded. The output of the FIFO is normally connected to the image memory 5 via the logical operation circuit 4. The FIFO is divided into two FIFOs 3a and 3b, 3a
The pixel stores a block address of the cache (the upper address generated by the DDA) in 3b. Circuit 6 shows a page address detection circuit. When data (pixels and addresses) are sequentially loaded into the FIFO3 from the DDA side, the page detection circuit continuously prefetches the FIFO3b. This is as shown in FIG.
The IFO3b output address is applied to register 7 and comparator 8. The register 7 is composed of a plurality of multi-stage registers connected in a pipeline. The number of columns is equal to the maximum number of page settings. For example, if the number of pages can be dynamically selected up to a maximum of 8, the number of registers will be 7 stages. The comparator 8 is a DRAM (Dynamic) that constitutes an image memory.
Since the page mode function of Random Access Memory) is used as a data write access, the address contained in the column address of this memory is detected. For this, the input and output of the register 7 are compared by the comparator 8, and when there is no change in the row address, the cache block address is regarded as within the same row address, and the page mode is possible. The comparator 8 sequentially reads the addresses from the FIFO 3b until the row address changes, and the counter 9 counts the number of continuous readings. In this way, the number of addresses in which the row address does not change is counted until the row address changes (or when the count value reaches a certain number). Request several page mode accesses to the sequencer 10 with timing generation function. As a result, the address A and the control timing T are output to the image memory in FIG. When the image memory enters the page mode, the pixel FIFO shown in FIG. 1 is read in synchronization with the page access cycle and the pixels are written in the image memory. Therefore, according to the present invention, the number of pages within one memory cycle time dynamically changes depending on the number of consecutive addresses in the page. As a result, even if the image memory is a low-speed DRAM, it is possible to improve the bandwidth between the image memory and the rendering processor by using the page mode.

[Effect] According to the present invention, the bandwidth of the image memory, which has hitherto been the biggest obstacle to speeding up the computer graphic system, has been improved, and high-speed drawing of 1 million polygons / second has become possible.

[Brief description of drawings]

FIG. 1 Pixel cache circuit of the present invention [Explanation of symbols] 1 DDA 2 Pixel cache 3a Image FIFO 3b Address FIFO 4 Logical operation circuit 5 Image memory 6 Page address detection circuit

FIG. 2 is a page address detection circuit of the present invention [Explanation of symbols] 3b address FIFO 7 register 8 comparator 9 counter 10 timing sequencer

Claims (1)

[Claims] Regarding a structure for transferring pixels generated by a graphics processor to an image memory, a pixel cache (P) consisting of a two-dimensional array is provided between the image memory and the processor.
and an image cache address (FIFO) that simultaneously stores the image memory address together with the pixels stored in the cache memory.
ut) and a DRAM (Dynamic Random A) that constitutes an image memory.
access memory to access the page memory in order to execute the page addressing mode.
When data is loaded into O, FI for address buffer
Second means for providing a circuit for prefetching FO and counting the number of consecutive in-page addresses to determine the number of page accesses; and, when the number of in-page addresses is determined, the FI for image
Pixel cache circuit having third means for reading out pixels in the FO in synchronization with page access and writing the same in the image memory