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CN114417781B - PCB wiring crosstalk evaluation method, system, device, equipment and storage medium - Google Patents

PCB wiring crosstalk evaluation method, system, device, equipment and storage medium Download PDF

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CN114417781B
CN114417781B CN202210333970.8A CN202210333970A CN114417781B CN 114417781 B CN114417781 B CN 114417781B CN 202210333970 A CN202210333970 A CN 202210333970A CN 114417781 B CN114417781 B CN 114417781B
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CN114417781A (en
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彭鹏亮
蔡怡君
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Suzhou Inspur Intelligent Technology Co Ltd
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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/398Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00Computer-aided design [CAD]
    • G06F30/30Circuit design
    • G06F30/39Circuit design at the physical level
    • G06F30/394Routing
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00Details relating to the type of the circuit
    • G06F2115/12Printed circuit boards [PCB] or multi-chip modules [MCM]

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Abstract

The application relates to the field of printed circuit board design, and discloses a PCB wiring crosstalk evaluation method, a system, a device, equipment and a storage medium. The modeling simulation workload of an engineer is reduced, the influence of the PCB glass fiber effect and the PCB lamination on the crosstalk value between the wires is comprehensively considered, the quick and accurate assessment on the crosstalk between the PCB wires is realized, the risk that the engineer selects a wiring scheme causing the unconventional crosstalk value in the PCB design process can be greatly reduced, and the wiring area planning can be quickly calculated, so that the product development quality is improved.

Description

PCB走线串扰评估方法、系统、装置、设备及存储介质PCB trace crosstalk evaluation method, system, device, equipment and storage medium

技术领域technical field

本申请涉及印制电路板设计领域,特别是涉及一种PCB走线串扰评估方法、系统、装置、设备及存储介质。The present application relates to the field of printed circuit board design, and in particular, to a method, system, device, device and storage medium for evaluating crosstalk of PCB traces.

背景技术Background technique

串扰是两条信号线之间的耦合、信号线之间的互感和互容引起线上的噪声,讯号在动态线(active line)或称攻击走线(aggressor line),会将一部份的讯号传到无讯号的静态线(又称受害走线,victim line)上,而造成耦合干扰问题。在PCB(Printed CircuitBoard,印刷电路板)设计和集成电路设计中,串扰是一个比较棘手的问题,PCB板层的参数、信号线间距、驱动端和接收端的电气特性及线端接方式对串扰都有一定的影响。因应现今电子产品轻薄短小伴随追求更高讯号传输质量发展趋势,使得电路板尺寸愈来愈小,各层走线密度也愈来愈大,特别当讯号传输速度持续加快时,串扰问题也愈趋严重,如何降低噪声干扰成了PCB设计团队需面对的重要课题。Crosstalk is the coupling between two signal lines, the mutual inductance and mutual capacitance between the signal lines causing noise on the line. The signal on the active line or the aggressive line will cause a part of the noise. The signal is transmitted to the static line with no signal (also known as the victim line, the victim line), which causes the problem of coupling interference. In PCB (Printed Circuit Board, printed circuit board) design and integrated circuit design, crosstalk is a relatively difficult problem. The parameters of the PCB layer, signal line spacing, electrical characteristics of the driving end and the receiving end, and line termination methods are all related to crosstalk. have a certain impact. In response to the development trend of today's electronic products being light, thin, and short, along with the pursuit of higher signal transmission quality, the size of the circuit board is getting smaller and smaller, and the wiring density of each layer is also increasing. Especially when the signal transmission speed continues to increase, the problem of crosstalk becomes more and more. Seriously, how to reduce noise interference has become an important issue for the PCB design team to face.

通常,信号完整性工程师会依照芯片厂所提供的设计指南,来定义走线距离等布线参数。但是当设计需求超出了设计指南,信号完整性工程师就必须自行进行建模仿真,以确定走线设计造成的串扰值对高速信号的影响是否在允许范围内。这使得在设计过程中,工程师需要花费大量时间在建模仿真上,不仅导致工程师的工作量较大、产品开发周期较长,且对工程师的建模仿真能力有很高的要求。若工程师在仿真过程中考虑因素不全面,仿真模型不准确,则会进一步导致仿真结果不准确,将给PCB设计以错误指导,最终影响到产品开发质量。Usually, signal integrity engineers define routing parameters such as trace distances in accordance with the design guidelines provided by chip manufacturers. However, when the design requirements exceed the design guidelines, the signal integrity engineer must perform modeling and simulation on their own to determine whether the impact of the crosstalk value caused by the trace design on the high-speed signal is within the allowable range. This makes it necessary for engineers to spend a lot of time on modeling and simulation during the design process, which not only results in a large workload for engineers and a longer product development cycle, but also places high demands on engineers' modeling and simulation capabilities. If the engineer does not consider the factors comprehensively in the simulation process and the simulation model is inaccurate, it will further lead to inaccurate simulation results, which will give wrong guidance to the PCB design, and ultimately affect the quality of product development.

如何准确评估PCB走线设计带来的串扰结果,是本领域技术人员需要解决的技术问题。How to accurately evaluate the crosstalk result brought by the PCB trace design is a technical problem to be solved by those skilled in the art.

发明内容SUMMARY OF THE INVENTION

本申请的目的是提供一种PCB走线串扰评估方法、系统、装置、设备及存储介质,用于准确评估PCB走线设计带来的串扰结果的同时,减轻PCB工程师的工作压力,缩短电子产品开发周期,提升电子产品质量。The purpose of this application is to provide a PCB trace crosstalk evaluation method, system, device, equipment and storage medium, which can be used to accurately evaluate the crosstalk results brought by PCB trace design, reduce the work pressure of PCB engineers, and shorten the time of electronic products. Development cycle, improve the quality of electronic products.

为解决上述技术问题,本申请提供一种PCB走线串扰评估方法,包括:In order to solve the above-mentioned technical problems, the present application provides a method for evaluating PCB trace crosstalk, including:

接收输入的目标PCB板材迭层的迭层信息、目标PCB玻纤布参数和目标布线参数;Receive the input lamination information of the target PCB board laminate, target PCB glass fiber cloth parameters and target wiring parameters;

基于所述目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块,基于所述目标PCB玻纤布参数生成目标PCB玻纤布仿真模块;Generate a target PCB board laminate simulation module based on the lamination information of the target PCB board laminate, and generate a target PCB glass fiber cloth simulation module based on the target PCB glass fiber cloth parameters;

结合所述目标PCB板材迭层仿真模块、所述目标PCB玻纤布仿真模块和所述目标布线参数,搭建PCB信号线串扰仿真计算模型;Combined with the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters, build a PCB signal line crosstalk simulation calculation model;

对所述PCB信号线串扰仿真计算模型进行串扰仿真模拟,得到串扰仿真结果;Crosstalk simulation is performed on the PCB signal line crosstalk simulation calculation model to obtain a crosstalk simulation result;

输出所述串扰仿真结果。The crosstalk simulation result is output.

可选的,还包括:Optionally, also include:

预先根据不同PCB板材的PCB物料电气特性参数,建立子迭层数据库;Establish a sub-layer database in advance according to the electrical characteristic parameters of PCB materials of different PCB boards;

接收输入的所述目标PCB板材迭层的迭层信息,具体为:Receive the input lamination information of the target PCB board lamination, specifically:

接收输入的对所述目标PCB板材迭层的迭层需求;receiving an input stack-up requirement for the target PCB board stack-up;

所述基于所述目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块,具体包括:The generation of the target PCB board laminate simulation module based on the laminate information of the target PCB board laminate specifically includes:

根据所述迭层需求自所述子迭层数据库中选择目标子迭层;selecting a target sub-stack from the sub-stack database according to the stack requirements;

基于各所述目标子迭层的迭层信息生成满足所述迭层需求的所述目标PCB板材迭层的所述目标PCB板材迭层仿真模块。The target PCB board stack simulation module for the target PCB board stack that meets the stack requirements is generated based on the stack-up information of each of the target sub-stacks.

可选的,所述基于各所述目标子迭层的迭层信息生成满足所述迭层需求的所述目标PCB板材迭层的所述目标PCB板材迭层仿真模块,具体包括:Optionally, generating the target PCB board laminate simulation module for the target PCB board laminate that meets the laminate requirements based on the laminate information of each of the target sub-layers, specifically includes:

当所述目标子迭层仅包括内层PCB结构和外层PCB结构时,基于所述内层PCB结构的迭层信息和所述外层PCB结构的迭层信息生成单层的所述目标PCB板材迭层;When the target sub-layer only includes an inner-layer PCB structure and an outer-layer PCB structure, the single-layer target PCB is generated based on the stack-up information of the inner-layer PCB structure and the stack-up information of the outer-layer PCB structure plate lamination;

当所述目标子迭层包括多层子迭层结构时,基于各所述子迭层结构生成多层的所述目标PCB板材迭层。When the target sub-stack includes multiple layers of sub-stack structures, multiple layers of the target PCB board stack-up are generated based on each of the sub-stack structures.

可选的,所述目标PCB玻纤布参数具体为玻纤布种类。Optionally, the target PCB glass fiber cloth parameter is specifically the type of glass fiber cloth.

可选的,述目标布线参数具体包括:信号线折线角度、信号线总长度、信号线线段长度、信号线线段数量、信号线阻抗值、信号频点和信号线间距。Optionally, the target wiring parameters specifically include: signal line broken line angle, total signal line length, signal line segment length, number of signal line segments, signal line impedance value, signal frequency points, and signal line spacing.

可选的,在所述结合所述目标PCB板材迭层仿真模块、所述目标PCB玻纤布仿真模块和所述目标布线参数,搭建PCB信号线串扰仿真计算模型之前,还包括:Optionally, before building the PCB signal line crosstalk simulation calculation model in combination with the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters, the method further includes:

判断所述目标布线参数对应的走线设计是否受到PCB玻纤效应影响;Determine whether the routing design corresponding to the target routing parameters is affected by the PCB glass fiber effect;

如果是,则进入所述结合所述目标PCB板材迭层仿真模块、所述目标PCB玻纤布仿真模块和所述目标布线参数,搭建PCB信号线串扰仿真计算模型的步骤;If yes, then enter the step of building a PCB signal line crosstalk simulation calculation model in combination with the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters;

如果否,则输出走线设计不合规的信息。If not, output trace design non-compliant information.

可选的,还包括:Optionally, also include:

对比所述串扰仿真结果和所述目标布线参数中的信号频点对应的工业标准串扰值,得到串扰评估结果;Comparing the crosstalk simulation result with the industry standard crosstalk value corresponding to the signal frequency point in the target wiring parameter, the crosstalk evaluation result is obtained;

输出所述串扰评估结果。The crosstalk evaluation result is output.

为解决上述技术问题,本申请还提供一种PCB走线串扰评估系统,包括:In order to solve the above technical problems, the present application also provides a PCB trace crosstalk evaluation system, including:

PCB迭层模块,用于基于输入的目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块;The PCB stack-up module is used to generate the target PCB board stack-up simulation module based on the input stack-up information of the target PCB board stack;

PCB玻纤布模块,用于基于输入的目标PCB玻纤布参数生成目标PCB玻纤布仿真模块;The PCB fiberglass cloth module is used to generate the target PCB fiberglass cloth simulation module based on the input target PCB fiberglass cloth parameters;

串扰仿真计算模块,用于结合所述目标PCB板材迭层仿真模块、所述目标PCB玻纤布仿真模块和输入的目标布线参数,搭建PCB信号线串扰仿真计算模型,对所述PCB信号线串扰仿真计算模型进行串扰仿真模拟,得到并输出串扰仿真结果。The crosstalk simulation calculation module is used to combine the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the input target wiring parameters to build a PCB signal line crosstalk simulation calculation model, and to measure the PCB signal line crosstalk The simulation calculation model performs crosstalk simulation simulation, and obtains and outputs the crosstalk simulation result.

为解决上述技术问题,本申请还提供一种PCB走线串扰评估装置,包括:In order to solve the above technical problems, the present application also provides a PCB trace crosstalk evaluation device, including:

接收单元,用于接收输入的目标PCB板材迭层的迭层信息、目标PCB玻纤布参数和目标布线参数;The receiving unit is used to receive the input lamination information of the target PCB board laminate, target PCB glass fiber cloth parameters and target wiring parameters;

第一建模单元,用于基于所述目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块;a first modeling unit, configured to generate a target PCB board laminate simulation module based on the laminate information of the target PCB board laminate;

第二建模单元,用于基于所述目标PCB玻纤布参数生成目标PCB玻纤布仿真模块;The second modeling unit is used to generate a target PCB glass fiber cloth simulation module based on the target PCB glass fiber cloth parameters;

第三建模单元,用于结合所述目标PCB板材迭层仿真模块、所述目标PCB玻纤布仿真模块和所述目标布线参数,搭建PCB信号线串扰仿真计算模型;The third modeling unit is used for building a simulation calculation model of PCB signal line crosstalk in combination with the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters;

串扰仿真单元,用于对所述PCB信号线串扰仿真计算模型进行串扰仿真模拟,得到串扰仿真结果;a crosstalk simulation unit for performing crosstalk simulation on the PCB signal line crosstalk simulation calculation model to obtain a crosstalk simulation result;

第一输出单元,用于输出所述串扰仿真结果。The first output unit is configured to output the crosstalk simulation result.

为解决上述技术问题,本申请还提供一种PCB走线串扰评估设备,包括:In order to solve the above technical problems, the present application also provides a PCB trace crosstalk evaluation device, including:

存储器,用于存储计算机程序;memory for storing computer programs;

处理器,用于执行所述计算机程序,所述计算机程序被所述处理器执行时实现如上述任意一项所述PCB走线串扰评估方法的步骤。The processor is configured to execute the computer program, and when the computer program is executed by the processor, the steps of the method for evaluating PCB trace crosstalk according to any one of the above are implemented.

为解决上述技术问题,本申请还提供一种存储介质,其上存储有计算机程序,所述计算机程序被处理器执行时实现如上述任意一项所述PCB走线串扰评估方法的步骤。In order to solve the above technical problem, the present application also provides a storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the steps of the method for evaluating PCB trace crosstalk according to any one of the above.

本申请所提供的PCB走线串扰评估方法,接收用户输入的目标PCB板材迭层的迭层信息、目标PCB玻纤布参数和目标布线参数,基于目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块,基于目标PCB玻纤布参数生成目标PCB玻纤布仿真模块,从而结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,自动搭建PCB信号线串扰仿真计算模型,进而对PCB信号线串扰仿真计算模型进行串扰仿真模拟,得到并输出串扰仿真结果。不仅降低了工程师的建模仿真工作量,且综合考虑到PCB玻纤效应及PCB板材迭层对走线间串扰值的影响,实现了对PCB走线间串扰的快速准确的评估,可以大幅度降低工程师在PCB设计过程中选用造成不合规串扰值的走线方案的风险,进而能够快速推算走线面积规划从而提升产品开发质量。The PCB trace crosstalk evaluation method provided by the present application receives the lamination information of the target PCB board laminate, the target PCB glass fiber cloth parameters and the target wiring parameters input by the user, and generates the target PCB based on the laminate information of the target PCB board laminate The board laminate simulation module generates the target PCB glass fiber cloth simulation module based on the target PCB glass fiber cloth parameters, so as to combine the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters to automatically build the PCB signal line crosstalk The simulation calculation model is performed, and then the crosstalk simulation simulation is performed on the PCB signal line crosstalk simulation calculation model, and the crosstalk simulation result is obtained and output. It not only reduces the modeling and simulation workload of engineers, but also comprehensively considers the influence of PCB glass fiber effect and PCB board laminate on the crosstalk value between traces, and realizes a fast and accurate evaluation of crosstalk between PCB traces, which can greatly Reduce the risk of engineers choosing routing solutions that cause non-compliant crosstalk values in the PCB design process, and can quickly calculate routing area planning to improve product development quality.

本申请还提供一种PCB走线串扰评估系统、装置、设备及存储介质,具有上述有益效果,在此不再赘述。The present application also provides a system, device, device and storage medium for evaluating PCB trace crosstalk, which have the above beneficial effects, and are not repeated here.

附图说明Description of drawings

为了更清楚的说明本申请实施例或现有技术的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单的介绍,显而易见地,下面描述中的附图仅仅是本申请的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。In order to illustrate the technical solutions of the embodiments of the present application or the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only For some embodiments of the present application, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

图1为本申请实施例提供的一种PCB走线串扰评估方法的流程图;FIG. 1 is a flowchart of a method for evaluating PCB trace crosstalk provided by an embodiment of the present application;

图2(a)为本申请实施例提供的一种PCB信号线串扰仿真计算模型的内层结构示意图;FIG. 2( a ) is a schematic diagram of the inner layer structure of a simulation calculation model for crosstalk of PCB signal lines according to an embodiment of the present application;

图2(b)本申请实施例提供的一种PCB信号线串扰仿真计算模型的外层结构示意图;FIG. 2(b) is a schematic diagram of the outer layer structure of a simulation calculation model for crosstalk of PCB signal lines provided by an embodiment of the present application;

图3为本申请实施例提供的一种PCB信号线串扰仿真计算模型的平面示意图;3 is a schematic plan view of a crosstalk simulation calculation model of a PCB signal line provided by an embodiment of the present application;

图4(a)为本申请实施例提供的第一例PCB信号线串扰仿真结果示意图;FIG. 4( a ) is a schematic diagram of a first example of PCB signal line crosstalk simulation results provided by an embodiment of the present application;

图4(b)为本申请实施例提供的第二例PCB信号线串扰仿真结果示意图;FIG. 4(b) is a schematic diagram of a second example of PCB signal line crosstalk simulation results provided by the embodiment of the present application;

图4(c)为本申请实施例提供的第三例PCB信号线串扰仿真结果示意图;FIG. 4(c) is a schematic diagram of a third example of a simulation result of PCB signal line crosstalk provided by the embodiment of the present application;

图4(d)为本申请实施例提供的第四例PCB信号线串扰仿真结果示意图;FIG. 4(d) is a schematic diagram of a fourth example of PCB signal line crosstalk simulation results provided by the embodiment of the application;

图5为本申请实施例提供的一种差分走线串扰评估说明示意图;FIG. 5 is a schematic diagram illustrating a differential trace crosstalk evaluation provided by an embodiment of the present application;

图6为本申请实施例提供的一种走线设计示意图;FIG. 6 is a schematic diagram of a wiring design provided by an embodiment of the present application;

图7为本申请实施例提供的一种PCB走线串扰评估系统的结构示意图;7 is a schematic structural diagram of a PCB trace crosstalk assessment system provided by an embodiment of the present application;

图8为本申请实施例提供的一种PCB走线串扰评估装置的结构示意图;FIG. 8 is a schematic structural diagram of a PCB trace crosstalk assessment device provided by an embodiment of the present application;

图9为本申请实施例提供的一种PCB走线串扰评估设备的结构示意图。FIG. 9 is a schematic structural diagram of a device for evaluating PCB trace crosstalk provided by an embodiment of the present application.

具体实施方式Detailed ways

本申请的核心是提供一种PCB走线串扰评估方法、系统、装置、设备及存储介质,用于准确评估PCB走线设计带来的串扰结果的同时,减轻PCB工程师的工作压力,缩短电子产品开发周期,提升电子产品质量。The core of this application is to provide a method, system, device, equipment and storage medium for evaluating PCB trace crosstalk, which can be used to accurately evaluate the crosstalk results brought about by PCB trace design, while reducing the work pressure of PCB engineers and shortening the frequency of electronic products. Development cycle, improve the quality of electronic products.

下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本申请一部分实施例,而不是全部的实施例。基于本申请中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

实施例一Example 1

图1为本申请实施例提供的一种PCB走线串扰评估方法的流程图。FIG. 1 is a flowchart of a method for evaluating PCB trace crosstalk provided by an embodiment of the present application.

如图1所示,本申请实施例提供的PCB走线串扰评估方法包括:As shown in FIG. 1 , the PCB trace crosstalk evaluation method provided by the embodiment of the present application includes:

S101:接收输入的目标PCB板材迭层的迭层信息、目标PCB玻纤布参数和目标布线参数。S101: Receive the input lamination information of the target PCB board laminate, target PCB glass fiber cloth parameters, and target wiring parameters.

S102:基于目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块,基于目标PCB玻纤布参数生成目标PCB玻纤布仿真模块。S102: Generate a target PCB board laminate simulation module based on the lamination information of the target PCB board laminate, and generate a target PCB glass fiber cloth simulation module based on the target PCB glass fiber cloth parameters.

S103:结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,搭建PCB信号线串扰仿真计算模型。S103: Combine the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters to build a PCB signal line crosstalk simulation calculation model.

S104:对PCB信号线串扰仿真计算模型进行串扰仿真模拟,得到串扰仿真结果。S104: Perform crosstalk simulation on the PCB signal line crosstalk simulation calculation model to obtain a crosstalk simulation result.

S105:输出串扰仿真结果。S105: Output the crosstalk simulation result.

现今的PCB基材大多由铜箔层(Copper Foil)、补强材(Reinforcement)、树脂(Epoxy)、填充材料(Fillers)等四种主要成分所构成。其中,铜箔层用于导电、传送讯号以及散热。补强材用于使PCB具刚性不易变形,并防止内部线路接点因热涨冷缩而脱离,主要材料包含牛皮纸、玻纤纸以及玻纤布。树脂与吸水率高低、耐热性等基础物理特性有关,主要材料包含环氧树脂、酚醛树脂、聚脂树脂、聚苯醚、碳氢化合物以及聚四氟乙烯等。填充材料用于加强PCB焊接时耐高温的特性。Most of today's PCB substrates are composed of four main components: Copper Foil, Reinforcement, Epoxy, and Fillers. Among them, the copper foil layer is used for conducting electricity, transmitting signals and dissipating heat. The reinforcing material is used to make the PCB rigid and not easily deformed, and to prevent the internal circuit contacts from being detached due to thermal expansion and contraction. The main materials include kraft paper, glass fiber paper and glass fiber cloth. Resin is related to basic physical properties such as water absorption, heat resistance, etc. The main materials include epoxy resin, phenolic resin, polyester resin, polyphenylene ether, hydrocarbon and polytetrafluoroethylene. Filler material is used to enhance the high temperature resistance of PCB soldering.

PCB物料电气特性参数中,在高速电路中信号的传播速度与讯号的衰减是两个相当重要的参数。信号的传播延迟取决于介电常数

Figure 390560DEST_PATH_IMAGE001
(DielectricConstant;Dk)的大小和传输线结构。由于传播时间与介电常数开根号成正比,若使用低介电常数的基板材料可以减少讯号的传播延迟,并可降低导线之间的耦合电容值,进而降低讯号之间的串扰。而信号衰减包含导体损耗与介质损耗,其中导体损耗又包含直流电阻损耗、肌肤效应造成的交流电阻损耗,以及导体粗糙度(Roughness)造成的损耗;而介电损耗则表示讯号在材料中的损耗,通常以Loss Tangent或Df (Dissipation Factor)来描述,使用具有低损耗的介质材料可以降低讯号的衰减而提高信号完整性。Among the electrical characteristics parameters of PCB materials, the propagation speed of signals and the attenuation of signals in high-speed circuits are two very important parameters. The propagation delay of a signal depends on the dielectric constant
Figure 390560DEST_PATH_IMAGE001
(DielectricConstant; Dk) size and transmission line structure. Since the propagation time is proportional to the square root of the dielectric constant, using a substrate material with a low dielectric constant can reduce the propagation delay of the signal and reduce the coupling capacitance between the wires, thereby reducing the crosstalk between the signals. The signal attenuation includes conductor loss and dielectric loss, of which conductor loss includes DC resistance loss, AC resistance loss caused by skin effect, and loss caused by conductor roughness; while dielectric loss represents the loss of the signal in the material , usually described by Loss Tangent or Df (Dissipation Factor), the use of dielectric materials with low loss can reduce signal attenuation and improve signal integrity.

由于PCB物料的选用和信号线走线方式是影响信号线间串扰值的主要因素,本申请提供一种能够自动执行搭建PCB信号线串扰仿真计算模型并进行串扰仿真模拟的评估系统,需用户提供搭建PCB信号线串扰仿真计算模型所必须的目标PCB板材迭层的迭层(也称“叠层”)信息、目标PCB玻纤布参数和目标布线参数输入该评估系统,由评估系统自动执行建模、串扰仿真计算工作,输出串扰仿真结果给用户参考。应用本申请实施例提供的PCB走线串扰评估方法,当用户的设计需求超出芯片厂的设计指南时,可以帮助用户快速确定当前PCB设计的合理性,方便用户进行参数调试,从而快速获得理想的PCB设计方案。Since the selection of PCB materials and the routing method of signal lines are the main factors affecting the value of crosstalk between signal lines, the present application provides an evaluation system that can automatically build a crosstalk simulation calculation model of PCB signal lines and perform crosstalk simulation. The information of the target PCB board stack-up (also called "stack-up"), the target PCB glass fiber cloth parameters and the target wiring parameters, which are necessary to build the PCB signal line crosstalk simulation calculation model, are input into the evaluation system, and the evaluation system automatically executes the construction. Mode and crosstalk simulation calculation work, output crosstalk simulation results for user reference. By applying the PCB trace crosstalk evaluation method provided in the embodiment of the present application, when the user's design requirement exceeds the design guideline of the chip factory, it can help the user to quickly determine the rationality of the current PCB design, and facilitate the user to perform parameter debugging, so as to quickly obtain the ideal value. PCB design scheme.

在具体实施中,对于步骤S101来说,预先根据构建PCB信号线串扰仿真计算模型所需的参数设定目标PCB板材迭层的迭层信息、目标PCB玻纤布参数和目标布线参数中各项参数的类型,为用户提供各项参数的输入界面,输入界面上设有用于输入目标PCB板材迭层的迭层信息、目标PCB玻纤布参数和目标布线参数的输入框或选项。In the specific implementation, for step S101, each of the lamination information of the target PCB board laminate, the target PCB glass fiber cloth parameters and the target wiring parameters are set in advance according to the parameters required for constructing the PCB signal line crosstalk simulation calculation model. The parameter type provides the user with an input interface for various parameters. The input interface is provided with input boxes or options for inputting the lamination information of the target PCB board laminate, the target PCB glass fiber cloth parameters, and the target wiring parameters.

对于步骤S102和步骤S103来说,为搭建PCB信号线串扰仿真计算模型,需先建立目标PCB板材迭层仿真模块和目标PCB玻纤布仿真模块。基于目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块和基于目标PCB玻纤布参数生成目标PCB玻纤布仿真模块的步骤可以同时进行,也可以先后进行,而后执行结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,搭建PCB信号线串扰仿真计算模型的工作。For step S102 and step S103, in order to build a simulation calculation model of PCB signal line crosstalk, it is necessary to first establish a target PCB board laminate simulation module and a target PCB glass fiber cloth simulation module. The steps of generating the target PCB board laminate simulation module based on the laminate information of the target PCB board laminate and generating the target PCB glass fiber cloth simulation module based on the target PCB glass fiber cloth parameters can be performed at the same time, or can be performed sequentially, and then combined with the target PCB. The board lamination simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters are used to build the PCB signal line crosstalk simulation calculation model.

为实现根据各项参数搭建PCB信号线串扰仿真计算模型,预先可以通过Python程序编写建模脚本,以运行建模脚本将用户选择的各项参数通过Python程序输出建立为HFSS仿真项目,并调用Python程控HFSS仿真软件自动执行仿真,输出PCB信号线串扰仿真计算模型。In order to build a simulation calculation model of PCB signal line crosstalk according to various parameters, a modeling script can be written in advance through the Python program, and the parameters selected by the user can be output through the Python program to create an HFSS simulation project by running the modeling script, and call Python. The program-controlled HFSS simulation software automatically executes the simulation and outputs the simulation calculation model of PCB signal line crosstalk.

对于步骤S104和步骤S105来说,具体可以执行ADS仿真软件,利用AEL程控汇集所有仿真数据后,回传至上文所述的评估系统,整合得到串扰仿真结果输出给用户查看,以使用户判断串扰仿真结果是否符合工业规范,若符合则可以根据PCB信号线串扰仿真计算模型的各项参数设置PCB走线,若不符合则重新进行仿真评估。For step S104 and step S105, ADS simulation software can be executed, and all simulation data can be collected by AEL program control, and then sent back to the evaluation system described above, and the crosstalk simulation result obtained by integration is output to the user for viewing, so that the user can judge the crosstalk Whether the simulation results conform to the industrial specifications, if so, the PCB traces can be set according to various parameters of the PCB signal line crosstalk simulation calculation model, and if not, the simulation evaluation is performed again.

在实际应用中,也可以采用其他编程语言或仿真软件,本申请实施例在此不作限定。In practical applications, other programming languages or simulation software may also be used, which are not limited in this embodiment of the present application.

本申请实施例提供的PCB走线串扰评估方法,接收用户输入的目标PCB板材迭层的迭层信息、目标PCB玻纤布参数和目标布线参数,基于目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块,基于目标PCB玻纤布参数生成目标PCB玻纤布仿真模块,从而结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,自动搭建PCB信号线串扰仿真计算模型,进而对PCB信号线串扰仿真计算模型进行串扰仿真模拟,得到并输出串扰仿真结果。不仅降低了工程师的建模仿真工作量,且综合考虑到PCB玻纤效应及PCB板材迭层对走线间串扰值的影响,实现了对PCB走线间串扰的快速准确的评估,可以大幅度降低工程师在PCB设计过程中选用造成不合规串扰值的走线方案的风险,进而能够快速推算走线面积规划从而提升产品开发质量。The PCB trace crosstalk evaluation method provided by the embodiment of the present application receives the lamination information of the target PCB board laminate, the target PCB glass fiber cloth parameters, and the target wiring parameters input by the user, and generates a target based on the laminate information of the target PCB board laminate. PCB board laminate simulation module, based on the target PCB glass fiber cloth parameters to generate the target PCB glass fiber cloth simulation module, so as to combine the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters to automatically build PCB signal lines Crosstalk simulation calculation model, and then carry out crosstalk simulation simulation on the PCB signal line crosstalk simulation calculation model, and obtain and output the crosstalk simulation result. It not only reduces the modeling and simulation workload of engineers, but also comprehensively considers the influence of PCB glass fiber effect and PCB board laminate on the crosstalk value between traces, and realizes a fast and accurate evaluation of crosstalk between PCB traces, which can greatly Reduce the risk of engineers choosing routing solutions that cause non-compliant crosstalk values in the PCB design process, and can quickly calculate routing area planning to improve product development quality.

实施例二Embodiment 2

图2(a)为本申请实施例提供的一种PCB信号线串扰仿真计算模型的内层结构示意图;图2(b)本申请实施例提供的一种PCB信号线串扰仿真计算模型的外层结构示意图。Figure 2(a) is a schematic diagram of the inner layer structure of a simulation calculation model for crosstalk of PCB signal lines provided by an embodiment of the present application; Schematic.

在上述实施例的基础上,为适于实际应用,本申请实施例对步骤S101~S103进行进一步说明。On the basis of the above embodiments, in order to be suitable for practical applications, steps S101 to S103 are further described in this embodiment of the present application.

在步骤S101中,用户提供目标PCB板材迭层的迭层信息,具体可以为用户输入设计好的目标PCB板材迭层的迭层信息,也可以通过预先建立迭层数据库供用户选择目标PCB板材迭层,或预先建立子迭层数据库供用户输入迭层需求后自动筛选子迭层并生成满足迭层需求的目标PCB板材迭层。In step S101, the user provides the stack-up information of the target PCB sheet stack, specifically, the user can input the designed stack-up information of the target PCB sheet stack, or a stack database can be pre-established for the user to select the target PCB sheet stack layer, or pre-establish a sub-layer database for users to input the requirements of the layers and automatically filter the sub-layers and generate the target PCB board layers that meet the requirements of the layers.

则本申请实施例提供的PCB走线串扰评估方法具体还可以包括:Then, the PCB trace crosstalk evaluation method provided in the embodiment of the present application may further include:

预先根据不同PCB板材的PCB物料电气特性参数,建立子迭层数据库;Establish a sub-layer database in advance according to the electrical characteristic parameters of PCB materials of different PCB boards;

则步骤S101中接收输入的目标PCB板材迭层的迭层信息,具体为:Then in step S101, the input lamination information of the target PCB board lamination is received, specifically:

接收输入的对目标PCB板材迭层的迭层需求;Receive the input stackup requirements for the target PCB board stackup;

步骤S102中基于目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块,具体包括:In step S102, a target PCB board laminate simulation module is generated based on the laminate information of the target PCB board laminate, which specifically includes:

根据迭层需求自子迭层数据库中选择目标子迭层;Select the target sub-layer from the sub-layer database according to the layer requirements;

基于各目标子迭层的迭层信息生成满足迭层需求的目标PCB板材迭层的目标PCB板材迭层仿真模块。Based on the stack-up information of each target sub-layer, a target PCB board stack-up simulation module that meets the stack-up requirements of the target PCB board stack-up is generated.

不同的PCB板材有不同的PCB物料电气特性参数。PCB迭层结构通常包括铜箔层(copper)、半固化片层(PP,Preprg),芯板层(core)。则涉及到的PCB物料电气特性参数具体可以包括半固化片层PP类型、芯板层Core类型、介电常数Dk、介电损耗Df等,这些数据决定了PCB走线的阻抗、线宽及线距。为方便用户提供目标PCB板材迭层的迭层信息,预先可以将不同的PCB物料对应的电气特性参数分别经过对应的子迭层关系式进行计算,得到不同子迭层的迭层信息,而后根据不同子迭层的迭层信息建立不同子迭层的子迭层数据库,从而当用户提供迭层需求后,评估系统可以自动从子迭层数据库中选择得到目标子迭层,并根据目标子迭层的迭层信息生成满足迭层需求的目标PCB板材迭层的目标PCB板材迭层仿真模块。迭层需求可以包括需求厚度、需求线宽、需求线距等,评估系统自动从子迭层数据库中筛选得到满足各目标子迭层生成的目标PCB板材迭层满足各迭层需求。Different PCB materials have different electrical characteristics of PCB materials. The PCB laminate structure usually includes a copper foil layer (copper), a prepreg layer (PP, Preprg), and a core layer (core). The electrical characteristic parameters of the PCB material involved can specifically include the PP type of the prepreg layer, the Core type of the core layer, the dielectric constant Dk, the dielectric loss Df, etc. These data determine the impedance, line width and line spacing of the PCB traces. In order to facilitate the user to provide the laminate information of the target PCB board laminate, the electrical characteristic parameters corresponding to different PCB materials can be calculated in advance through the corresponding sub-lamination relational expressions to obtain the laminate information of different sub-layers, and then according to The stack information of different sub-stacks establishes sub-stack databases of different sub-stacks, so that when the user provides stack requirements, the evaluation system can automatically select and obtain the target sub-stack from the sub-stack database, and according to the target sub-stack The stack-up information of the layers generates a target PCB board stack-up simulation module for the target PCB board stack-up that meets the stack-up requirements. Lamination requirements can include required thickness, required line width, required line spacing, etc. The evaluation system automatically selects the target PCB board laminate generated by each target sub-layer from the sub-layer database to meet the requirements of each layer.

子迭层数据库的形式可以参考表1。The form of the sub-layer database can refer to Table 1.

表1 子迭层数据库数据表Table 1 Sub-stack database data table

Figure 104438DEST_PATH_IMAGE002
Figure 104438DEST_PATH_IMAGE002

其中,“oz”为基材铜厚重量单位。“RTF”为双面粗化铜箔。Among them, "oz" is the weight unit of base copper thickness. "RTF" is double-sided roughened copper foil.

需要说明的是,表1只是列举子迭层数据库的一种可选形式,还可以采用其他的形式进行表示,同时可以包括更多类型的板材以及选用的信号线类型。It should be noted that Table 1 is only an optional form of enumerating the sub-layer database, and other forms can also be used to represent, and at the same time, it can include more types of boards and selected signal line types.

可选的,用户可以自主从子迭层数据库中选择目标子迭层,则目标PCB板材迭层的迭层信息具体可以包括迭层板材(Stackup Material)(如采用S7040G)和迭层类型(Stackup Type)(如采用微带线)。Optionally, the user can independently select the target sub-layer from the sub-layer database, and the stack-up information of the target PCB sheet stack may specifically include the stack-up material (for example, S7040G) and the stack-up type (Stackup). Type) (such as using a microstrip line).

进一步的,基于各目标子迭层的迭层信息生成满足迭层需求的目标PCB板材迭层的目标PCB板材迭层仿真模块,具体可以包括:Further, a target PCB board laminate simulation module for generating a target PCB board laminate that meets the laminate requirements based on the laminate information of each target sub-layer may specifically include:

当目标子迭层仅包括内层PCB结构和外层PCB结构时,基于内层PCB结构的迭层信息和外层PCB结构的迭层信息生成单层的目标PCB板材迭层;When the target sub-layer only includes the inner-layer PCB structure and the outer-layer PCB structure, a single-layer target PCB board stack is generated based on the stack-up information of the inner-layer PCB structure and the stack-up information of the outer-layer PCB structure;

当目标子迭层包括多层子迭层结构时,基于各子迭层结构生成多层的目标PCB板材迭层。When the target sub-stack includes multiple sub-stack structures, a multi-layer target PCB board stack is generated based on each sub-stack structure.

由于高速信号线通常采用差分线,差分线走线通常仅在PCB的单层上进行走线,少数情况下,差分线通过过孔跨层走线。则本申请实施例给用户提供的对目标PCB板材迭层的迭层信息的输入界面可以包括用于选择所需单层PCB的内层PCB结构和外层PCB结构的常用界面,以及选择多个目标子迭层以生成信号线走线的多层PCB迭层结构的扩展界面。Since high-speed signal lines usually use differential lines, differential lines are usually routed only on a single layer of the PCB. In a few cases, differential lines are routed across layers through vias. Then, the input interface for the stacking information of the target PCB board stacking provided to the user by the embodiment of the present application may include a common interface for selecting the inner-layer PCB structure and the outer-layer PCB structure of the desired single-layer PCB, and selecting multiple The target sub-stack to generate the extended interface of the multi-layer PCB stack-up of the signal line traces.

为方便用户输入目标PCB玻纤布参数,本申请实施例还可以包括预先建立PCB玻纤布数据库,在输入界面列出PCB玻纤布数据库中可选的PCB玻纤布参数以供用户选择。由于不同型号(种类)的玻纤布对应有相应的规格,即玻纤布种类(Glass Type)对应有玻纤密度(Weave Density)、玻璃树脂比(Glass/Resin Ratio)、相对介电常数(RelativePermittivity)等参数,目标PCB玻纤布参数具体可以仅为玻纤布种类。现今常用的玻纤布种类有1078、1080、1086、2116、1506、7628等型号。In order to facilitate the user to input the target PCB glass fiber cloth parameters, the embodiment of the present application may further include pre-establishing a PCB glass fiber cloth database, and listing the optional PCB glass fiber cloth parameters in the PCB glass fiber cloth database on the input interface for the user to select. Because different types (types) of glass fiber cloth correspond to corresponding specifications, that is, glass fiber cloth types (Glass Type) correspond to glass fiber density (Weave Density), glass resin ratio (Glass/Resin Ratio), relative dielectric constant ( RelativePermittivity) and other parameters, the target PCB glass fiber cloth parameters can only be the type of glass fiber cloth. The types of glass fiber cloth commonly used today are 1078, 1080, 1086, 2116, 1506, 7628 and other models.

则在步骤S102中,可以以表2的形式给用户提供PCB玻纤布参数以供用户选择目标PCB玻纤布参数,并基于目标PCB玻纤布参数生成对应的目标PCB玻纤布仿真模块。Then in step S102, the PCB glass fiber cloth parameters may be provided to the user in the form of Table 2 for the user to select the target PCB glass fiber cloth parameters, and a corresponding target PCB glass fiber cloth simulation module is generated based on the target PCB glass fiber cloth parameters.

表2 目标PCB玻纤布参数表Table 2 Target PCB glass fiber cloth parameter table

Figure 149755DEST_PATH_IMAGE003
Figure 149755DEST_PATH_IMAGE003

步骤S101中需用户输入的目标布线参数具体可以包括:信号线折线角度、信号线总长度、信号线线段长度、信号线线段数量、信号线阻抗值、信号频点和信号线间距。针对差分信号,则目标布线参数具体可以包括:差分线折线角度(Differential Trace Angle)、差分线总长度(Differential Trace Length)、差分线线段长度(Differential TraceSegment Length)、差分线线段数量(Differential Trace Segment Number)、差分线阻抗值(Differential Trace Ohm)、差分线频点(Differential Trace Frequecy)和差分线间距(Spacing for Pair to Pair)。The target wiring parameters to be input by the user in step S101 may specifically include: signal line broken line angle, total signal line length, signal line segment length, number of signal line segments, signal line impedance value, signal frequency point and signal line spacing. For differential signals, the target wiring parameters may specifically include: Differential Trace Angle, Differential Trace Length, Differential TraceSegment Length, and Differential Trace Segment Number), Differential Trace Ohm, Differential Trace Frequecy and Spacing for Pair to Pair.

在针对差分线的串扰值进行测试时,采用现有建立3对差分走线的串扰仿真计算模型的常规方式构建PCB信号线串扰仿真计算模型,可以参考图2(a)、图2(b)所示,其对应的参数分别如表3、4所示。When testing the crosstalk value of the differential line, the crosstalk simulation calculation model of the PCB signal line is constructed by the conventional method of establishing the crosstalk simulation calculation model of the three pairs of differential traces. Please refer to Figure 2(a) and Figure 2(b) The corresponding parameters are shown in Tables 3 and 4, respectively.

表3 PCB信号线串扰仿真计算模型的内层结构参数表Table 3 Inner layer structure parameter table of PCB signal line crosstalk simulation calculation model

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Figure 341702DEST_PATH_IMAGE004

表4 PCB信号线串扰仿真计算模型的外层结构参数表 Table 4. Outer structure parameter table of PCB signal line crosstalk simulation calculation model

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Figure 687232DEST_PATH_IMAGE005

图2(a)、图2(b)中,“TOP_Roughness”为顶部粗糙度,“BOT_Roughness”为底部粗糙度。In Figure 2(a) and Figure 2(b), "TOP_Roughness" is the top roughness, and "BOT_Roughness" is the bottom roughness.

以表3、表4所示的目标PCB板材迭层的迭层信息的相关参数为例,结合上一步骤生成的目标PCB玻纤布仿真模块,生成如图2(a)、图2(b)所示的PCB信号线串扰仿真计算模型。Taking the relevant parameters of the lamination information of the target PCB board laminate shown in Table 3 and Table 4 as an example, combined with the target PCB glass fiber cloth simulation module generated in the previous step, Figure 2(a) and Figure 2(b) are generated. ) of the PCB signal line crosstalk simulation calculation model.

基于本申请实施例提供的PCB走线串扰评估方法,用户需输入目标PCB板材迭层的迭层信息、信号线折线角度、信号线总长度、信号线线段长度、信号线线段数量、信号线阻抗值、信号频点、信号线间距和玻纤布种类,评估系统即可自动搭建PCB信号线串扰仿真计算模型,而后对PCB信号线串扰仿真计算模型进行串扰仿真测试,得到一系列用于进行仿真评估的仿真数据,进而可以按照与目标PCB板材迭层的迭层信息、目标PCB玻纤布参数和目标布线参数等参数对应的串扰值计算公式得到与PCB信号线串扰仿真计算模型对应的串扰仿真结果并输出给用户参考。Based on the PCB trace crosstalk evaluation method provided by the embodiment of the present application, the user needs to input the stacking information of the target PCB board laminate, the signal line broken line angle, the total length of the signal line, the length of the signal line segment, the number of signal line segments, and the impedance of the signal line. Value, signal frequency point, signal line spacing and glass fiber cloth type, the evaluation system can automatically build a PCB signal line crosstalk simulation calculation model, and then conduct a crosstalk simulation test on the PCB signal line crosstalk simulation calculation model to obtain a series of simulations. The evaluated simulation data, and then the crosstalk simulation corresponding to the PCB signal line crosstalk simulation calculation model can be obtained according to the crosstalk value calculation formula corresponding to the lamination information of the target PCB board laminate, the target PCB glass fiber cloth parameters, and the target wiring parameters. The result is output to the user for reference.

需要说明的是,本申请实施例提供的PCB走线串扰评估方法仅以用户输入的目标布线参数为一组固定参数为例进行说明,如针对差分线,此时生成3对规则的差分线进行串扰仿真。而在实际应用中,工程师往往需要根据设计需求而选择不规则的走线设计,例如每段信号线线段的长度(如图3所示的L1、L2、L3、L4、L5、L6)、每段信号线线段的折线角度(

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)均可以不同,即支持由用户定制各段折线段的走线参数。It should be noted that the PCB trace crosstalk evaluation method provided in the embodiment of the present application is only described by taking the target wiring parameters input by the user as a set of fixed parameters as an example. Crosstalk simulation. In practical applications, engineers often need to choose irregular routing designs according to design requirements, such as the length of each signal line segment (L1, L2, L3, L4, L5, L6 as shown in Figure 3), each The polyline angle of the segment signal line segment (
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,
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,
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,
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,
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,
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) can be different, that is, users can customize the routing parameters of each polyline segment.

实施例三Embodiment 3

图3为本申请实施例提供的一种PCB信号线串扰仿真计算模型的平面示意图;图4(a)为本申请实施例提供的第一例PCB信号线串扰仿真结果示意图;图4(b)为本申请实施例提供的第二例PCB信号线串扰仿真结果示意图;图4(c)为本申请实施例提供的第三例PCB信号线串扰仿真结果示意图;图4(d)为本申请实施例提供的第四例PCB信号线串扰仿真结果示意图;图5为本申请实施例提供的一种差分走线串扰评估说明示意图。3 is a schematic plan view of a simulation calculation model for crosstalk of PCB signal lines provided by an embodiment of the present application; Figure 4(c) is a schematic diagram of a third example of PCB signal line crosstalk simulation results provided by the embodiment of the application; Figure 4(d) is a schematic diagram of the implementation of the application Example 4 is a schematic diagram of a simulation result of PCB signal line crosstalk; FIG. 5 is a schematic diagram illustrating an evaluation of differential line crosstalk provided by an embodiment of the present application.

在上述实施例的基础上,为适于实际应用,本申请实施例以信号线为差分线为例,对步骤S104中对PCB信号线串扰仿真计算模型进行串扰仿真模拟,得到串扰仿真结果的具体实施方式进行进一步说明。On the basis of the above embodiments, in order to be suitable for practical applications, the embodiment of the present application takes the signal line as a differential line as an example, and performs crosstalk simulation on the crosstalk simulation calculation model of the PCB signal line in step S104 to obtain the specific crosstalk simulation result. Embodiments are further described.

采用现有建立3对差分走线的串扰仿真计算模型的常规方式构建PCB信号线串扰仿真计算模型,如图3所示,生成3对差分走线D1、D2、D3,控制差分线间距分别为10 miles、20 miles、30 miles、40 miles分别进行四次串扰仿真评估,其他参数可参照表5所示。The crosstalk simulation calculation model of the PCB signal line is constructed by the conventional method of establishing the crosstalk simulation calculation model of the three pairs of differential traces. As shown in Figure 3, three pairs of differential traces D1, D2, and D3 are generated, and the distance between the control differential traces is 10 miles, 20 miles, 30 miles, and 40 miles, respectively, carry out four crosstalk simulation evaluations. For other parameters, please refer to Table 5.

表5 差分线串扰仿真评估参数表Table 5 Differential line crosstalk simulation evaluation parameter table

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Figure 112900DEST_PATH_IMAGE012

基于如表5所示的输入参数,分别得到如图4(a)、图4(b)、图4(c)、图4(d)所示的串扰仿真结果,分别为不同信号频点下根据串扰数据计算得到的串扰仿真结果。Based on the input parameters shown in Table 5, the crosstalk simulation results shown in Fig. 4(a), Fig. 4(b), Fig. 4(c), and Fig. 4(d) are obtained respectively. Crosstalk simulation results calculated from crosstalk data.

参照图5所示,根据差分线隔各端的串扰数据计算得到如图4(a)、图4(b)、图4(c)、图4(d)所示的串扰仿真结果的具体计算过程具体如下:Referring to Figure 5, the specific calculation process of the crosstalk simulation results shown in Figure 4(a), Figure 4(b), Figure 4(c), and Figure 4(d) is calculated according to the crosstalk data at each end of the differential line. details as follows:

对差分线D1有:For differential line D1:

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;

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;

对差分线D2有:For differential line D2 there are:

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;

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;

对差分线D3有:For differential line D3 there are:

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;

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;

则在当前输入参数下,差分线的远端线外串扰(Far End X-Talk)为:Then under the current input parameters, the far end alien crosstalk (Far End X-Talk) of the differential line is:

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Figure 73794DEST_PATH_IMAGE019
;

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;

差分线的近端线外串扰(Near End X-Talk)为:The Near End X-Talk of the differential line is:

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;

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;

最终得到综合线外串扰(Power Sum Differential Crosstalk,PSXTalk)为:Finally, the integrated alien crosstalk (Power Sum Differential Crosstalk, PSXTalk) is obtained as:

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.

在步骤S105中,可以输出如图4(a)、图4(b)、图4(c)、图4(d)所示的计算得到的综合线外串扰的波形作为串扰仿真结果。In step S105 , the calculated integrated alien crosstalk waveforms as shown in FIG. 4( a ), FIG. 4( b ), FIG. 4( c ), and FIG. 4( d ) may be output as the crosstalk simulation result.

进一步的,为方便用户直观得到当前的走线设计是否符合工业规范、即串扰值是否满足设计要求,本申请实施例提供的PCB走线串扰评估方法还可以包括:Further, in order to facilitate the user to intuitively obtain whether the current routing design conforms to industrial specifications, that is, whether the crosstalk value meets the design requirements, the PCB routing crosstalk evaluation method provided in the embodiment of the present application may further include:

对比串扰仿真结果和目标布线参数中的信号频点对应的工业标准串扰值,得到串扰评估结果;Compare the crosstalk simulation result with the industry standard crosstalk value corresponding to the signal frequency point in the target wiring parameters, and obtain the crosstalk evaluation result;

输出串扰评估结果。The crosstalk evaluation result is output.

在实际应用中,差分线的线外串扰的允许值与信号频点对应,根据上述步骤中输入的差分线频点,确定对应的工业标准串扰值。若串扰仿真结果大于工业标准串扰值,则输出走线设计不合格的串扰评估结果;若串扰仿真结果小于工业标准串扰值,则输出走线设计合格的串扰评估结果。In practical applications, the allowable value of the alien crosstalk of the differential line corresponds to the signal frequency point, and the corresponding industry standard crosstalk value is determined according to the differential line frequency point input in the above steps. If the crosstalk simulation result is greater than the industry standard crosstalk value, output the crosstalk evaluation result of unqualified trace design; if the crosstalk simulation result is less than the industry standard crosstalk value, output the crosstalk evaluation result of qualified trace design.

需要说明的是,本申请实施例提供的PCB走线串扰评估方法仅以对差分线的串扰仿真方式进行说明,若针对其他类型的信号线,可以采用与信号线类型对应的生成仿真用的布线方式以及对应的串扰值计算公式。It should be noted that the PCB trace crosstalk evaluation method provided in the embodiment of the present application is only described in the crosstalk simulation mode of the differential line. For other types of signal lines, the wiring corresponding to the signal line type can be used to generate simulation. method and the corresponding crosstalk value calculation formula.

实施例四Embodiment 4

图6为本申请实施例提供的一种走线设计示意图。FIG. 6 is a schematic diagram of a wiring design according to an embodiment of the present application.

在上述实施例的基础上,考虑到信号速率不断提高的现状下,PCB玻纤效应对高速信号的串扰影响越来越明显。PCB玻纤效应即当信号线走线是沿着玻璃纤维编织方向的0°或90°时,差分线上个别正负讯号的特性阻抗会因为电场流动的路径上,在微观所感受到介质结构(特性)不同而不同。例如会造成一对差分线中,其中一条信号线经过的玻纤布区域仅为玻璃纤维编织,而另一条信号线经过的玻纤布区域除了玻璃纤维编织还包括环氧树脂,则前者受玻璃纤维的介电系数影响为主,后者还会收到环氧树脂的介电系数的影响,二者的介电系数完全不同,这会造成一对差分线彼此间的特性阻抗与传递时间延迟不匹配,进而影响到眼图。为避免该影响,在设计PCB走线时,应当避免信号线与PCB玻纤布的编织方向呈平行或垂直的情形。On the basis of the above-mentioned embodiment, considering the current situation that the signal rate is constantly increasing, the influence of the PCB glass fiber effect on the crosstalk of the high-speed signal is becoming more and more obvious. PCB glass fiber effect means that when the signal line is 0° or 90° along the direction of glass fiber weaving, the characteristic impedance of the individual positive and negative signals on the differential line will be felt in the microscopic medium structure ( characteristics) vary. For example, in a pair of differential lines, the glass fiber cloth area that one signal line passes through is only glass fiber weaving, and the glass fiber cloth area that the other signal line passes through includes epoxy resin in addition to glass fiber weaving, then the former is affected by glass fiber. The dielectric coefficient of the fiber is mainly affected, and the latter is also affected by the dielectric coefficient of the epoxy resin. The dielectric coefficients of the two are completely different, which will cause the characteristic impedance and transfer time delay between a pair of differential lines. mismatch, which in turn affects the eye diagram. To avoid this effect, when designing PCB traces, avoid the situation where the signal line is parallel or perpendicular to the weaving direction of the PCB fiberglass cloth.

故在本申请实施例提供的PCB走线串扰评估方法中,在步骤S103:结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,搭建PCB信号线串扰仿真计算模型之前,还包括:Therefore, in the PCB trace crosstalk evaluation method provided by the embodiment of the present application, in step S103: before building the PCB signal line crosstalk simulation calculation model in combination with the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters ,Also includes:

判断目标布线参数对应的走线设计是否受到PCB玻纤效应影响;Determine whether the routing design corresponding to the target routing parameters is affected by the PCB glass fiber effect;

如果是,则进入步骤S103,结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,搭建PCB信号线串扰仿真计算模型的步骤;If yes, then enter step S103, combine the target PCB board laminate simulation module, target PCB glass fiber cloth simulation module and target wiring parameters, build the step of PCB signal line crosstalk simulation calculation model;

如果否,则输出走线设计不合规的信息。If not, output trace design non-compliant information.

在具体实施中,请参考图6,对于不同的信号频点,有不同的标准来定义信号线走线的角度及长度,与玻纤编织平行垂直走线长度和水平走线长度总和长度的平方根,加上全段走线总长度统计平方公差法(Root-Sum-Squares),定义出各频点全段走线总长度。In the specific implementation, please refer to Figure 6, for different signal frequency points, there are different standards to define the angle and length of the signal line, the square root of the sum of the length of the vertical line parallel to the glass fiber braid and the length of the horizontal line , plus the statistical square tolerance method (Root-Sum-Squares) of the total length of the entire line, to define the total length of the entire line at each frequency point.

其中,玻纤编织平行垂直走线长度和水平走线长度总和长度的平方根如下式所示:Among them, the square root of the sum of the length of the glass fiber braided parallel vertical traces and horizontal traces is as follows:

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;

其中,H 1 、H 2 、H 3 ……为信号线线段垂直长度,V 1 、V 2 、V 3 ……为信号线线段水平长度。Among them, H 1 , H 2 , H 3 ...... are the vertical lengths of the signal line segments, and V 1 , V 2 , V 3 ...... are the horizontal lengths of the signal line segments.

全段走线总长度统计平方公差如下式所示:The statistical square tolerance of the total length of the entire route is shown in the following formula:

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;

其中,L 1 、L 2 、L 3 、L 4 、L 5 、L 6 ……为信号线线段长度。Wherein, L 1 , L 2 , L 3 , L 4 , L 5 , L 6 . . . are the lengths of the signal line segments.

各信号频点下对应的最大全段走线总长度统计平方公差可以参考表6。Refer to Table 6 for the statistical square tolerance of the total length of the maximum full-length trace corresponding to each signal frequency point.

表6 各信号频点下对应的最大全段走线总长度统计平方公差表Table 6 Statistical square tolerance table of the total length of the maximum full-section trace corresponding to each signal frequency point

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Figure 330835DEST_PATH_IMAGE026

在搭建PCB信号线串扰仿真计算模型之前,根据上述公式计算用户输入的目标布线参数对应的全段走线总长度统计平方公差,进而评估该全段走线总长度统计平方公差是否不超出用户输入的信号频点下对应的最大全段走线总长度统计平方公差,如果是,则确认目标布线参数对应的走线设计不受PCB玻纤效应影响,可以进入搭建PCB信号线串扰仿真计算模型的步骤;如果否,则确认目标布线参数对应的走线设计会受到PCB玻纤效应影响,输出走线设计不合规的信息,提示用户更改目标布线参数。Before building the PCB signal line crosstalk simulation calculation model, calculate the statistical square tolerance of the total length of the entire line corresponding to the target wiring parameters input by the user according to the above formula, and then evaluate whether the statistical square tolerance of the total length of the entire line does not exceed the user input. Statistical square tolerance of the maximum total length of the entire length of the trace corresponding to the signal frequency point of Step; if not, confirm that the routing design corresponding to the target routing parameters will be affected by the PCB glass fiber effect, output the information that the routing design is not compliant, and prompt the user to change the target routing parameters.

需要说明的是,本申请实施例提供的PCB走线串扰评估方法仅以对差分线的串扰仿真方式进行说明,若针对其他类型的信号线,可以采用对应的PCB玻纤效应影响的评估方式,或直接评估确认所有的信号线折线角度(即信号线与PCB玻纤布编织方向所成的角度)不为0°或90°即可。It should be noted that the PCB trace crosstalk evaluation method provided in the embodiment of the present application is only described in the crosstalk simulation mode of the differential line. For other types of signal lines, the corresponding evaluation method of PCB glass fiber effect can be used. Or directly evaluate and confirm that all signal line folding angles (that is, the angle between the signal line and the weaving direction of the PCB glass fiber cloth) are not 0° or 90°.

本申请实施例提供的PCB走线串扰评估方法通过在搭建PCB信号线串扰仿真计算模型之前进行走线设计是否受PCB玻纤效应影响的评估,以保证走线设计的合理性,提高仿真成功率。The PCB trace crosstalk evaluation method provided by the embodiment of the present application ensures the rationality of the trace design and improves the simulation success rate by evaluating whether the trace design is affected by the PCB glass fiber effect before building a simulation calculation model of PCB signal trace crosstalk. .

上文详述了PCB走线串扰评估方法对应的各个实施例,在此基础上,本申请还公开了与上述方法对应的PCB走线串扰评估系统、装置、设备及存储介质。Various embodiments corresponding to the PCB trace crosstalk evaluation method are described in detail above. On this basis, the present application also discloses a PCB trace crosstalk evaluation system, device, equipment and storage medium corresponding to the above method.

实施例五Embodiment 5

图7为本申请实施例提供的一种PCB走线串扰评估系统的结构示意图。FIG. 7 is a schematic structural diagram of a PCB trace crosstalk evaluation system provided by an embodiment of the present application.

如图7所示,本申请实施例提供的PCB走线串扰评估系统包括:As shown in FIG. 7 , the PCB trace crosstalk evaluation system provided by the embodiment of the present application includes:

PCB迭层模块701,用于基于输入的目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块;The PCB stacking module 701 is used to generate a target PCB stacking simulation module based on the input stacking information of the target PCB stacking;

PCB玻纤布模块702,用于基于输入的目标PCB玻纤布参数生成目标PCB玻纤布仿真模块;The PCB glass fiber cloth module 702 is used to generate a target PCB glass fiber cloth simulation module based on the input target PCB glass fiber cloth parameters;

串扰仿真计算模块703,用于结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和输入的目标布线参数,搭建PCB信号线串扰仿真计算模型,对PCB信号线串扰仿真计算模型进行串扰仿真模拟,得到并输出串扰仿真结果。The crosstalk simulation calculation module 703 is used to combine the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the input target wiring parameters to build a PCB signal line crosstalk simulation calculation model, and perform crosstalk on the PCB signal line crosstalk simulation calculation model. Simulate the simulation, get and output the crosstalk simulation result.

进一步的,本申请实施例提供的PCB走线串扰评估系统还包括:Further, the PCB trace crosstalk evaluation system provided in the embodiment of the present application further includes:

子迭层数据库模块,用于预先根据不同PCB板材的PCB物料电气特性参数,建立子迭层数据库;The sub-layer database module is used to establish a sub-layer database in advance according to the electrical characteristic parameters of PCB materials of different PCB boards;

相应的,PCB迭层模块701基于输入的目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块,具体包括:Correspondingly, the PCB stacking module 701 generates a target PCB sheet stacking simulation module based on the input stacking information of the target PCB sheet stacking, which specifically includes:

基于输入的对目标PCB板材迭层的迭层需求自子迭层数据库模块的子迭层数据库中选择目标子迭层;Select the target sub-stack from the sub-stack database of the sub-stack database module based on the input stack-up requirements for the target PCB board stack;

基于各目标子迭层的迭层信息生成满足迭层需求的目标PCB板材迭层的目标PCB板材迭层仿真模块。Based on the stack-up information of each target sub-layer, a target PCB board stack-up simulation module that meets the stack-up requirements of the target PCB board stack-up is generated.

进一步的,本申请实施例提供的PCB走线串扰评估系统还包括:Further, the PCB trace crosstalk evaluation system provided in the embodiment of the present application further includes:

走线设计评估模块,用于在串扰仿真计算模块703结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,搭建PCB信号线串扰仿真计算模型之前, 判断目标布线参数对应的走线设计是否受到PCB玻纤效应影响;如果是,则由串扰仿真计算模块703执行结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,搭建PCB信号线串扰仿真计算模型的步骤;如果否,则输出走线设计不合规的信息。The trace design evaluation module is used to determine the corresponding parameters of the target wiring before building the crosstalk simulation calculation model of the PCB signal line before the crosstalk simulation calculation module 703 combines the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters. Whether the routing design is affected by the PCB glass fiber effect; if so, the crosstalk simulation calculation module 703 will perform the crosstalk simulation of the PCB signal line by combining the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters. Steps to compute the model; if not, output the trace design non-compliance message.

进一步的,本申请实施例提供的PCB走线串扰评估系统还包括:Further, the PCB trace crosstalk evaluation system provided in the embodiment of the present application further includes:

串扰评估模块,用于对比串扰仿真结果和目标布线参数中的信号频点对应的工业标准串扰值,得到并输出串扰评估结果。The crosstalk evaluation module is used to compare the crosstalk simulation result with the industry standard crosstalk value corresponding to the signal frequency point in the target wiring parameters, and obtain and output the crosstalk evaluation result.

由于系统部分的实施例与方法部分的实施例相互对应,因此系统部分的实施例请参见方法部分的实施例的描述,这里暂不赘述。Since the embodiments of the system part correspond to the embodiments of the method part, for the embodiments of the system part, please refer to the description of the embodiments of the method part, which will not be repeated here.

实施例六Embodiment 6

图8为本申请实施例提供的一种PCB走线串扰评估装置的结构示意图。FIG. 8 is a schematic structural diagram of an apparatus for evaluating crosstalk of PCB traces provided by an embodiment of the present application.

如图8所示,本申请实施例提供的PCB走线串扰评估装置包括:As shown in FIG. 8 , the PCB trace crosstalk evaluation device provided by the embodiment of the present application includes:

接收单元801,用于接收输入的目标PCB板材迭层的迭层信息、目标PCB玻纤布参数和目标布线参数;The receiving unit 801 is used to receive the input lamination information of the target PCB board laminate, target PCB glass fiber cloth parameters and target wiring parameters;

第一建模单元802,用于基于目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块;The first modeling unit 802 is configured to generate a target PCB board laminate simulation module based on the laminate information of the target PCB board laminate;

第二建模单元803,用于基于目标PCB玻纤布参数生成目标PCB玻纤布仿真模块;The second modeling unit 803 is configured to generate a target PCB glass fiber cloth simulation module based on the target PCB glass fiber cloth parameters;

第三建模单元804,用于结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,搭建PCB信号线串扰仿真计算模型;The third modeling unit 804 is used for building a simulation calculation model of PCB signal line crosstalk in combination with the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters;

串扰仿真单元805,用于对PCB信号线串扰仿真计算模型进行串扰仿真模拟,得到串扰仿真结果;A crosstalk simulation unit 805, configured to perform crosstalk simulation simulation on the PCB signal line crosstalk simulation calculation model to obtain a crosstalk simulation result;

第一输出单元806,用于输出串扰仿真结果。The first output unit 806 is configured to output the crosstalk simulation result.

进一步的,本申请实施例提供的PCB走线串扰评估装置还可以包括:Further, the PCB trace crosstalk evaluation device provided in the embodiment of the present application may further include:

子迭层数据单元,用于预先根据不同PCB板材的PCB物料电气特性参数,建立子迭层数据库;The sub-layer data unit is used to establish a sub-layer database in advance according to the electrical characteristic parameters of the PCB materials of different PCB boards;

则接收单元801接收输入的目标PCB板材迭层的迭层信息,具体为:Then the receiving unit 801 receives the input lamination information of the target PCB board lamination, specifically:

接收输入的对目标PCB板材迭层的迭层需求;Receive the input stackup requirements for the target PCB board stackup;

第一建模单元802基于目标PCB板材迭层的迭层信息生成目标PCB板材迭层仿真模块,具体包括:The first modeling unit 802 generates a target PCB board laminate simulation module based on the laminate information of the target PCB board laminate, which specifically includes:

根据迭层需求自子迭层数据库中选择目标子迭层;Select the target sub-layer from the sub-layer database according to the layer requirements;

基于各目标子迭层的迭层信息生成满足迭层需求的目标PCB板材迭层的目标PCB板材迭层仿真模块。Based on the stack-up information of each target sub-layer, a target PCB board stack-up simulation module that meets the stack-up requirements of the target PCB board stack-up is generated.

进一步的,本申请实施例提供的PCB走线串扰评估装置还可以包括:Further, the PCB trace crosstalk evaluation device provided in the embodiment of the present application may further include:

判断单元,用于在第三建模单元804结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,搭建PCB信号线串扰仿真计算模型之前,判断目标布线参数对应的走线设计是否受到PCB玻纤效应影响,如果是,则进入第三建模单元804执行结合目标PCB板材迭层仿真模块、目标PCB玻纤布仿真模块和目标布线参数,搭建PCB信号线串扰仿真计算模型的步骤;如果否,则进入第二输出单元;The judgment unit is used for judging the path corresponding to the target wiring parameters before the third modeling unit 804 combines the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters to build the PCB signal line crosstalk simulation calculation model. Whether the line design is affected by the PCB glass fiber effect, if so, enter the third modeling unit 804 to execute the combination of the target PCB board laminate simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters to build a PCB signal line crosstalk simulation calculation the steps of the model; if not, enter the second output unit;

第二输出单元,用于输出走线设计不合规的信息。The second output unit is used to output the information that the design of the trace is not compliant.

进一步的,本申请实施例提供的PCB走线串扰评估装置还可以包括:Further, the PCB trace crosstalk evaluation device provided in the embodiment of the present application may further include:

对比单元,用于对比串扰仿真结果和目标布线参数中的信号频点对应的工业标准串扰值,得到串扰评估结果;The comparison unit is used to compare the crosstalk simulation result with the industry standard crosstalk value corresponding to the signal frequency point in the target wiring parameters, and obtain the crosstalk evaluation result;

第三输出单元,用于输出串扰评估结果。The third output unit is used for outputting the crosstalk evaluation result.

由于装置部分的实施例与方法部分的实施例相互对应,因此装置部分的实施例请参见方法部分的实施例的描述,这里暂不赘述。Since the embodiment of the apparatus part corresponds to the embodiment of the method part, for the embodiment of the apparatus part, please refer to the description of the embodiment of the method part, which will not be repeated here.

实施例七Embodiment 7

图9为本申请实施例提供的一种PCB走线串扰评估设备的结构示意图。FIG. 9 is a schematic structural diagram of a device for evaluating PCB trace crosstalk provided by an embodiment of the present application.

如图9所示,本申请实施例提供的PCB走线串扰评估设备包括:As shown in FIG. 9 , the PCB trace crosstalk evaluation device provided in the embodiment of the present application includes:

存储器910,用于存储计算机程序911;memory 910 for storing computer programs 911;

处理器920,用于执行计算机程序911,该计算机程序911被处理器920执行时实现如上述任意一项实施例所述PCB走线串扰评估方法的步骤。The processor 920 is configured to execute the computer program 911. When the computer program 911 is executed by the processor 920, the steps of the PCB trace crosstalk assessment method described in any one of the foregoing embodiments are implemented.

其中,处理器920可以包括一个或多个处理核心,比如3核心处理器、8核心处理器等。处理器920可以采用数字信号处理DSP(Digital Signal Processing)、现场可编程门阵列FPGA(Field-Programmable Gate Array)、可编程逻辑阵列PLA(Programmable LogicArray)中的至少一种硬件形式来实现。处理器920也可以包括主处理器和协处理器,主处理器是用于对在唤醒状态下的数据进行处理的处理器,也称中央处理器CPU(CentralProcessing Unit);协处理器是用于对在待机状态下的数据进行处理的低功耗处理器。在一些实施例中,处理器920可以集成有图像处理器GPU(Graphics Processing Unit),GPU用于负责显示屏所需要显示的内容的渲染和绘制。一些实施例中,处理器920还可以包括人工智能AI(Artificial Intelligence)处理器,该AI处理器用于处理有关机器学习的计算操作。The processor 920 may include one or more processing cores, such as a 3-core processor, an 8-core processor, and the like. The processor 920 may be implemented in at least one hardware form among digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 920 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake-up state, also called a central processing unit (CPU); the coprocessor is used for processing data in the wake-up state. A low-power processor that processes data in a standby state. In some embodiments, the processor 920 may be integrated with a graphics processing unit (GPU), and the GPU is used for rendering and drawing the content that needs to be displayed on the display screen. In some embodiments, the processor 920 may further include an artificial intelligence (Artificial Intelligence) processor for processing computing operations related to machine learning.

存储器910可以包括一个或多个存储介质,该存储介质可以是非暂态的。存储器910还可包括高速随机存取存储器,以及非易失性存储器,比如一个或多个磁盘存储设备、闪存存储设备。本实施例中,存储器910至少用于存储以下计算机程序911,其中,该计算机程序911被处理器920加载并执行之后,能够实现前述任一实施例公开的PCB走线串扰评估方法中的相关步骤。另外,存储器910所存储的资源还可以包括操作系统912和数据913等,存储方式可以是短暂存储或者永久存储。其中,操作系统912可以为Windows。数据913可以包括但不限于上述方法所涉及到的数据。Memory 910 may include one or more storage media, which may be non-transitory. Memory 910 may also include high-speed random access memory, as well as non-volatile memory, such as one or more disk storage devices, flash storage devices. In this embodiment, the memory 910 is at least used to store the following computer program 911, where, after the computer program 911 is loaded and executed by the processor 920, it can implement the relevant steps in the PCB trace crosstalk assessment method disclosed in any of the foregoing embodiments . In addition, the resources stored in the memory 910 may also include an operating system 912 and data 913, etc., and the storage mode may be short-term storage or permanent storage. The operating system 912 may be Windows. The data 913 may include, but is not limited to, the data involved in the above methods.

在一些实施例中,PCB走线串扰评估设备还可包括有显示屏930、电源940、通信接口950、输入输出接口960、传感器970以及通信总线980。In some embodiments, the PCB trace crosstalk evaluation device may further include a display screen 930 , a power supply 940 , a communication interface 950 , an input and output interface 960 , a sensor 970 and a communication bus 980 .

本领域技术人员可以理解,图9中示出的结构并不构成对PCB走线串扰评估设备的限定,可以包括比图示更多或更少的组件。Those skilled in the art can understand that the structure shown in FIG. 9 does not constitute a limitation to the PCB trace crosstalk evaluation equipment, and may include more or less components than those shown.

本申请实施例提供的PCB走线串扰评估设备,包括存储器和处理器,处理器在执行存储器存储的程序时,能够实现如上所述的PCB走线串扰评估方法,效果同上。The PCB trace crosstalk evaluation device provided by the embodiment of the present application includes a memory and a processor. When the processor executes a program stored in the memory, the above-mentioned PCB trace crosstalk evaluation method can be implemented, and the effect is the same as above.

实施例八Embodiment 8

需要说明的是,以上所描述的系统、装置、设备实施例仅仅是示意性的,例如,模块的划分,仅仅为一种逻辑功能划分,实际实现时可以有另外的划分方式,例如多个模块或组件可以结合或者可以集成到另一个系统,或一些特征可以忽略,或不执行。另一点,所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口,装置或模块的间接耦合或通信连接,可以是电性,机械或其它的形式。作为分离部件说明的模块可以是或者也可以不是物理上分开的,作为模块显示的部件可以是或者也可以不是物理模块,即可以位于一个地方,或者也可以分布到多个网络模块上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。It should be noted that the above-described system, apparatus, and device embodiments are only illustrative. For example, the division of modules is only a logical function division. In actual implementation, there may be other division methods, such as multiple modules. Or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or modules, and may be in electrical, mechanical or other forms. Modules described as separate components may or may not be physically separated, and components shown as modules may or may not be physical modules, that is, they may be located in one place, or may be distributed to multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

另外,在本申请各个实施例中的各功能模块可以集成在一个处理模块中,也可以是各个模块单独物理存在,也可以两个或两个以上模块集成在一个模块中。上述集成的模块既可以采用硬件的形式实现,也可以采用软件功能模块的形式实现。In addition, each functional module in each embodiment of the present application may be integrated into one processing module, or each module may exist physically alone, or two or more modules may be integrated into one module. The above-mentioned integrated modules can be implemented in the form of hardware, and can also be implemented in the form of software function modules.

集成的模块如果以软件功能模块的形式实现并作为独立的产品销售或使用时,可以存储在一个存储介质中。基于这样的理解,本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来,该计算机软件产品存储在一个存储介质中,执行本申请各个实施例所述方法的全部或部分步骤。If the integrated modules are implemented in the form of software functional modules and sold or used as independent products, they may be stored in a storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of software products in essence, or the parts that contribute to the prior art, or all or part of the technical solutions, and the computer software products are stored in a storage medium , execute all or part of the steps of the methods described in the various embodiments of the present application.

为此,本申请实施例还提供一种存储介质,该存储介质上存储有计算机程序,计算机程序被处理器执行时实现如PCB走线串扰评估方法的步骤。To this end, an embodiment of the present application further provides a storage medium, where a computer program is stored on the storage medium, and when the computer program is executed by a processor, steps such as a method for evaluating PCB trace crosstalk are implemented.

该存储介质可以包括:U盘、移动硬盘、只读存储器ROM(Read-Only Memory)、随机存取存储器RAM(Random Access Memory)、磁碟或者光盘等各种可以存储程序代码的介质。The storage medium may include: a U disk, a removable hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and other mediums that can store program codes.

本实施例中提供的存储介质所包含的计算机程序能够在被处理器执行时实现如上所述的PCB走线串扰评估方法的步骤,效果同上。The computer program included in the storage medium provided in this embodiment can, when executed by the processor, implement the steps of the above-described method for evaluating PCB trace crosstalk, and the effects are the same as above.

以上对本申请所提供的一种PCB走线串扰评估方法、系统、装置、设备及存储介质进行了详细介绍。说明书中各个实施例采用递进的方式描述,每个实施例重点说明的都是与其他实施例的不同之处,各个实施例之间相同相似部分互相参见即可。对于实施例公开的系统、装置、设备及存储介质而言,由于其与实施例公开的方法相对应,所以描述的比较简单,相关之处参见方法部分说明即可。应当指出,对于本技术领域的普通技术人员来说,在不脱离本申请原理的前提下,还可以对本申请进行若干改进和修饰,这些改进和修饰也落入本申请权利要求的保护范围内。A method, system, device, device and storage medium for evaluating PCB trace crosstalk provided by the present application have been described above in detail. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same and similar parts between the various embodiments can be referred to each other. As for the system, device, device and storage medium disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and for related parts, please refer to the description of the method section. It should be pointed out that for those of ordinary skill in the art, without departing from the principles of the present application, several improvements and modifications can also be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

还需要说明的是,在本说明书中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。It should also be noted that, in this specification, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or operations. There is no such actual relationship or sequence between operations. Moreover, the terms "comprising", "comprising" or any other variation thereof are intended to encompass a non-exclusive inclusion such that a process, method, article or device that includes a list of elements includes not only those elements, but also includes not explicitly listed or other elements inherent to such a process, method, article or apparatus. Without further limitation, an element qualified by the phrase "comprising a..." does not preclude the presence of additional identical elements in a process, method, article or apparatus that includes the element.

Claims (9)

1. A PCB trace crosstalk evaluation method is characterized by comprising the following steps:
receiving input lamination information of target PCB lamination, target PCB glass fiber cloth parameters and target wiring parameters;
generating a target PCB laminated simulation module based on the laminated information of the target PCB, and generating a target PCB fiberglass cloth simulation module based on the target PCB fiberglass cloth parameters;
combining the target PCB plate lamination simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters to build a PCB signal line crosstalk simulation calculation model;
carrying out crosstalk simulation on the PCB signal wire crosstalk simulation calculation model to obtain a crosstalk simulation result;
outputting the crosstalk simulation result;
the target PCB glass fiber cloth parameter is the type of the glass fiber cloth specifically;
before the combining the target PCB plate lamination simulation module, the target PCB fiberglass cloth simulation module and the target wiring parameters and building a PCB signal line crosstalk simulation calculation model, the method further comprises the following steps:
judging whether the routing design corresponding to the target routing parameters is influenced by the PCB glass fiber effect; if so, the step of building a PCB signal wire crosstalk simulation calculation model by combining the target PCB plate lamination simulation module, the target PCB fiberglass cloth simulation module and the target wiring parameters is carried out; if not, outputting the information that the routing design is not compliant;
wherein, judge whether the line design that the target wiring parameter corresponds receives the fine effect influence of PCB glass, specifically include:
according to
Figure DEST_PATH_IMAGE002
Calculating the total length statistical square tolerance of the whole-section routing corresponding to the target wiring parameter;
if the total length statistical square tolerance of the full-section wiring is larger than the maximum total length statistical square tolerance of the full-section wiring corresponding to the input signal frequency point, determining that the wiring design corresponding to the target wiring parameter is influenced by the PCB glass fiber effect;
if the total length statistical square tolerance of the full-section wiring is not greater than the maximum total length statistical square tolerance of the full-section wiring corresponding to the input signal frequency point, determining that the wiring design corresponding to the target wiring parameter is not influenced by the PCB glass fiber effect;
wherein,L 1 、L 2 、L 3 、L 4 、L 5 、L 6 … … is the length of signal line segment。
2. The PCB trace crosstalk evaluation method of claim 1, further comprising:
establishing a sub-laminated database in advance according to the PCB material electrical characteristic parameters of different PCB plates;
receiving input lamination information of the target PCB lamination, specifically:
receiving input lamination requirements for lamination of the target PCB plate;
the generating of the target PCB lamination simulation module based on the lamination information of the target PCB lamination specifically includes:
selecting a target sub-lamination from the sub-lamination database according to the lamination requirement;
and generating the target PCB lamination simulation module of the target PCB lamination meeting the lamination requirement based on the lamination information of each target sub lamination.
3. The method for evaluating crosstalk between PCB traces according to claim 2, wherein the generating the target PCB board lamination simulation module of the target PCB board lamination that meets the lamination requirement based on the lamination information of each target sub-lamination specifically comprises:
when the target sub-lamination only comprises an inner layer PCB structure and an outer layer PCB structure, generating a single-layer target PCB lamination based on lamination information of the inner layer PCB structure and lamination information of the outer layer PCB structure;
when the target sub-laminate includes a multi-layer sub-laminate structure, generating a multi-layer target PCB board laminate based on each of the sub-laminate structures.
4. The PCB trace crosstalk evaluation method of claim 1, wherein the target routing parameters specifically include: the device comprises a signal line broken line angle, a total signal line length, a signal line segment number, a signal line impedance value, a signal frequency point and a signal line interval.
5. The PCB trace crosstalk evaluation method of claim 1, further comprising:
comparing the crosstalk simulation result with an industrial standard crosstalk value corresponding to the signal frequency point in the target wiring parameter to obtain a crosstalk evaluation result;
and outputting the crosstalk evaluation result.
6. A PCB trace crosstalk evaluation device, comprising:
the receiving unit is used for receiving input lamination information of target PCB lamination, target PCB glass fiber cloth parameters and target wiring parameters;
the first modeling unit is used for generating a target PCB lamination simulation module based on lamination information of the target PCB lamination;
the second modeling unit is used for generating a target PCB glass fiber cloth simulation module based on the target PCB glass fiber cloth parameters;
the third modeling unit is used for building a PCB signal line crosstalk simulation calculation model by combining the target PCB plate lamination simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameters;
the crosstalk simulation unit is used for carrying out crosstalk simulation on the PCB signal wire crosstalk simulation calculation model to obtain a crosstalk simulation result;
the first output unit is used for outputting the crosstalk simulation result;
a judging unit, configured to judge whether a routing design corresponding to a target wiring parameter is affected by a PCB glass fiber effect before the third modeling unit combines the target PCB board lamination simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameter to build a PCB signal line crosstalk simulation calculation model, and if so, enter the third modeling unit to execute the step of combining the target PCB board lamination simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameter to build a PCB signal line crosstalk simulation calculation model; if not, entering a second output unit;
the second output unit is used for outputting information that the wiring design is not compliant;
wherein, judge whether the line design that the target wiring parameter corresponds receives the fine effect influence of PCB glass, specifically include:
according to
Figure 930671DEST_PATH_IMAGE002
Calculating the total length statistical square tolerance of the whole-section routing corresponding to the target wiring parameter;
if the total length statistical square tolerance of the full-section wiring is larger than the maximum total length statistical square tolerance of the full-section wiring corresponding to the input signal frequency point, determining that the wiring design corresponding to the target wiring parameter is influenced by the PCB glass fiber effect;
if the total length statistical square tolerance of the full-section wiring is not greater than the maximum total length statistical square tolerance of the full-section wiring corresponding to the input signal frequency point, determining that the wiring design corresponding to the target wiring parameter is not influenced by the PCB glass fiber effect;
wherein,L 1 、L 2 、L 3 、L 4 、L 5 、L 6 … … is the length of signal line segment; the target PCB glass fiber cloth parameters are the types of the glass fiber cloth.
7. A PCB trace crosstalk evaluation system, comprising:
the PCB lamination module is used for generating a target PCB lamination simulation module based on the input lamination information of the target PCB lamination;
the PCB glass fiber cloth module is used for generating a target PCB glass fiber cloth simulation module based on the input target PCB glass fiber cloth parameters;
the crosstalk simulation calculation module is used for combining the target PCB plate lamination simulation module, the target PCB glass fiber cloth simulation module and input target wiring parameters to build a PCB signal wire crosstalk simulation calculation model, and performing crosstalk simulation on the PCB signal wire crosstalk simulation calculation model to obtain and output a crosstalk simulation result;
the wiring design evaluation module is used for judging whether the wiring design corresponding to the target wiring parameter is influenced by the PCB glass fiber effect or not before the crosstalk simulation calculation module is combined with the target PCB laminated simulation module, the target PCB glass fiber cloth simulation module and the target wiring parameter to build a PCB signal wire crosstalk simulation calculation model; if yes, the crosstalk simulation calculation module executes the combination target PCB plate lamination simulation module, the target PCB fiberglass cloth simulation module and the target wiring parameters to build a PCB signal wire crosstalk simulation calculation model; if not, outputting the information that the wiring design is not in compliance;
wherein, judge whether the line design that the target wiring parameter corresponds receives the fine effect influence of PCB glass, specifically include:
according to
Figure 303884DEST_PATH_IMAGE002
Calculating the total length statistical square tolerance of the whole-section routing corresponding to the target wiring parameter;
if the total length statistical square tolerance of the full-section wiring is larger than the maximum total length statistical square tolerance of the full-section wiring corresponding to the input signal frequency point, determining that the wiring design corresponding to the target wiring parameter is influenced by the PCB glass fiber effect;
if the total length statistical square tolerance of the full-section wires is not greater than the maximum total length statistical square tolerance of the full-section wires corresponding to the input signal frequency points, determining that the wire design corresponding to the target wiring parameters is not influenced by the PCB glass fiber effect;
wherein,L 1 、L 2 、L 3 、L 4 、L 5 、L 6 … … is the length of signal line segment; the target PCB glass fiber cloth parameters are the types of the glass fiber cloth.
8. A PCB trace crosstalk evaluation device, comprising:
a memory for storing a computer program;
a processor for executing the computer program, wherein the computer program when executed by the processor implements the steps of the PCB trace crosstalk evaluation method according to any one of claims 1 to 5.
9. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the PCB trace crosstalk evaluation method according to any one of claims 1 to 5.
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115062578B (en) * 2022-07-11 2025-02-07 华兴通信技术有限公司 A method for evaluating inter-stage decoupling of millimeter wave integrated circuits
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CN115361787B (en) * 2022-09-16 2024-01-23 苏州浪潮智能科技有限公司 PCB wiring design method, PCB wiring design processing method and PCB
CN116709634B (en) * 2023-07-31 2023-11-03 苏州浪潮智能科技有限公司 a circuit board
CN117545191B (en) * 2023-11-10 2024-05-24 东莞明瑾电子科技有限公司 Method, device, equipment and medium for controlling assembly of PCB router
TWI866809B (en) * 2024-03-13 2024-12-11 英業達股份有限公司 Circuit board line crosstalk inspection method and non-tansitory computer readable medium
CN118395908B (en) * 2024-06-28 2024-09-17 中茵微电子(南京)有限公司 High-speed circuit performance evaluation method and system based on 3DIC design
CN118711625B (en) * 2024-08-29 2024-11-15 苏州元脑智能科技有限公司 Memory signal transmission system, signal line layout method, product, device and medium

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111475355A (en) * 2020-03-20 2020-07-31 苏州浪潮智能科技有限公司 High-speed link signal integrity assessment method, system, terminal and storage medium
CN112769507A (en) * 2020-12-30 2021-05-07 苏州浪潮智能科技有限公司 High-speed signal link transmission quality evaluation method and related equipment

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105704931B (en) * 2014-11-28 2021-01-22 中兴通讯股份有限公司 Wiring method of differential signal line and PCB
CN108303635B (en) * 2017-12-29 2020-08-11 中科曙光信息产业成都有限公司 Test board for verifying electrical performance of PCB material
CN112307705A (en) * 2020-10-15 2021-02-02 苏州浪潮智能科技有限公司 Method and system for rapidly evaluating crosstalk of parallel differential lines of printed circuit board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111475355A (en) * 2020-03-20 2020-07-31 苏州浪潮智能科技有限公司 High-speed link signal integrity assessment method, system, terminal and storage medium
CN112769507A (en) * 2020-12-30 2021-05-07 苏州浪潮智能科技有限公司 High-speed signal link transmission quality evaluation method and related equipment

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