CN114415773B - High-precision current source circuit - Google Patents
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Abstract
The invention provides a high-precision current source circuit, which comprises: a first current source circuit including a first operational amplifier, a first transistor, a second transistor, and a first resistor, wherein a positive input terminal of the first operational amplifier is connected to a first node, a negative input terminal of the first operational amplifier is connected to a reference voltage node, and an output terminal of the first operational amplifier is connected to a gate of the first transistor and a gate of the second transistor; a source of the first transistor is connected to a power supply voltage, and a drain thereof is connected to the first resistor through a first node; the source electrode of the second transistor is connected to the power supply voltage, and the drain electrode of the second transistor is connected with the output node through a fourth node; one end of the first resistor is connected to the first node, and the other end of the first resistor is connected to a ground node; and a voltage clamping module configured to provide a fixed source-drain voltage to the first transistor and the second transistor of the first current source circuit.
Description
Technical Field
The present invention relates to the field of analog integrated circuit design, and more particularly to a high precision current source circuit.
Background
In analog integrated circuits, a current source is a very important module. The current source is used as a reference source of the circuit, provides accurate bias current for other modules of the circuit, and is widely applied to circuits such as operational amplifiers, comparators, phase-locked loops, digital-to-analog converters and the like.
The accuracy of the current source determines the performance of the overall analog circuitry. The requirement for a current source is to be able to output a stable current value that does not vary with temperature and supply voltage. Conventionally, a current source circuit includes an operational amplifier, a PMOS transistor, and a resistor. The reference voltage VREF of the operational amplifier is a stable voltage which is generated by the band gap reference source and does not change with temperature and power supply voltage. In the conventional current source structure, since the output current Iref of the current source is theoretically proportional to the reference voltage VREF, and since the reference voltage VREF does not vary with the temperature and the power supply voltage VDD, the output current Iref is also theoretically stable from varying with the temperature and the power supply voltage VDD.
However, the relationship between the output current Iref and the reference voltage VREF is too ideal. In practical applications, the output current Iref is affected by variations in the supply voltage VDD due to the channel length modulation effect. Specifically, during the variation of the supply voltage, the source-drain voltage VDS of the transistor varies and the actual value of the output current Iref of the current source deviates from the ideal value, and increases slowly with the increase of the supply voltage VDD. The above situation makes conventional current sources unsatisfactory for constant current output.
In view of the above technical problems, a high-precision current source circuit is needed to provide a reliable solution, so as to keep the output current of the current source constant during the change of the power supply voltage and under the condition of temperature change, and further obtain high-precision current output.
Disclosure of Invention
Technical problem to be solved
In practical application, the current source is affected by the channel length modulation effect, the actual value of the output current Iref deviates from the ideal value under the influence of the change of the supply voltage VDD, and increases slowly with the increase of the supply voltage VDD, which makes it difficult to meet the requirement of constant output high-precision current.
Technical proposal
In order to solve the above problems, the present invention provides a high-precision current source circuit.
According to an aspect of the present invention, there is provided a high-precision current source circuit including: the first current source circuit comprises a first operational amplifier, a first transistor, a second transistor and a first resistor, wherein the positive input end of the first operational amplifier is connected with a first node, the negative input end of the first operational amplifier is connected with a reference voltage node, and the output end of the first operational amplifier is connected with the grid electrode of the first transistor and the grid electrode of the second transistor; a source of the first transistor is connected to a power supply voltage, and a drain thereof is connected to the first resistor through a first node; the source electrode of the second transistor is connected to the power supply voltage, and the drain electrode of the second transistor is connected with the output node through a fourth node; one end of the first resistor is connected to the first node, and the other end of the first resistor is connected to a ground node; and a voltage clamping module configured to provide a fixed source-drain voltage for the first transistor and the second transistor of the first current source circuit.
According to another aspect of the present invention, there is provided a high precision current source circuit, wherein the first current source circuit further comprises a third transistor, and the voltage clamping module comprises a second operational amplifier, wherein a source of the third transistor is connected to a third node connected to a drain of the first transistor, a drain of the third transistor is connected to the first node, and a gate of the third transistor is connected to an output of the second operational amplifier, wherein a positive input of the second operational amplifier is connected to a first bias voltage node, and a negative input of the second operational amplifier is connected to the third node.
According to another aspect of the present invention, there is provided a high precision current source circuit, wherein the first current source circuit further comprises a fourth transistor, and the voltage clamping module further comprises a third operational amplifier, wherein a source of the fourth transistor is connected to a fourth node connected to a drain of the second transistor, a drain of the fourth transistor is connected to an output node, and a gate of the fourth transistor is connected to an output of the third operational amplifier, wherein a positive input of the third operational amplifier is connected to a second bias voltage node, and a negative input of the third operational amplifier is connected to the fourth node.
According to another aspect of the present invention, there is provided a high precision current source circuit, wherein the second bias voltage node is connected to the third node.
According to another aspect of the present invention, there is provided a high precision current source circuit, wherein the first bias voltage node is connected to the second bias voltage node.
According to another aspect of the present invention, there is provided a high precision current source circuit, wherein the voltage clamp module further comprises a bias circuit module, the first bias circuit module being configured to provide a bias voltage to the high precision current source circuit through a bias voltage output node.
According to another aspect of the present invention, there is provided a high-precision current source circuit, wherein a bias circuit module includes a first bias current source, a second resistor, a fifth transistor, and a sixth transistor, wherein one end of the first bias current source is connected to a power supply node, and the other end thereof is connected to a drain of the fifth transistor; one end of the second resistor is connected with a power supply node, and the other end of the second resistor is connected to a bias voltage output node; a gate of the fifth transistor is connected with a gate of the sixth transistor, a source of the fifth transistor is grounded, and a drain of the fifth transistor is connected with the gate; and a drain of the sixth transistor is connected to the bias voltage output node, and a source of the sixth transistor is grounded.
According to another aspect of the present invention, there is provided a high precision current source circuit, wherein the bias voltage output node is connected to the first bias voltage node.
According to another aspect of the present invention, there is provided a high precision current source circuit, wherein the bias voltage output node is connected to the first bias voltage node and the second bias voltage node.
Advantageous effects
Compared with the prior art, the invention provides a high-precision current source circuit, which has the following beneficial effects: the voltage clamping circuit is formed through the operational amplifier, so that the source-drain voltage VDS of the transistor in the current source is kept constant and does not change along with the change of the power supply voltage, and the output current of the current source is kept constant in the process of changing the power supply voltage and under the condition of changing the temperature; in addition, the influence of the channel length modulation effect on the output current is eliminated, so that the high-precision output current can be obtained, and the high-precision current output is realized.
Drawings
FIG. 1 is a schematic diagram of a conventional current source structure;
FIG. 2 is a schematic diagram of the I/V characteristics of a transistor with channel length modulation effects;
FIG. 3 is a schematic diagram of the output current Iref versus supply voltage VDD for a conventional current source implementation;
FIG. 4 is a schematic diagram of a high precision current source circuit according to an embodiment of the invention; and
fig. 5 is a schematic diagram of the output current Iref according to the power supply voltage VDD according to the embodiment of the present invention.
Detailed Description
Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "coupled," "connected," and derivatives thereof, refer to any direct or indirect communication or connection between two or more elements, whether or not those elements are in physical contact with one another. The terms "transmit," "receive," and "communicate," and derivatives thereof, encompass both direct and indirect communication. The terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation. The term "or" is inclusive, meaning and/or. The phrase "associated with … …" and its derivatives are intended to include, be included in, interconnect with, contain within … …, connect or connect with … …, couple or couple with … …, communicate with … …, mate, interleave, juxtapose, approximate, bind or bind with … …, have attributes, have relationships or have relationships with … …, etc. The term "controller" refers to any device, system, or portion thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and/or firmware. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. The phrase "at least one," when used with a list of items, means that different combinations of one or more of the listed items may be used, and that only one item in the list may be required. For example, "at least one of A, B, C" includes any one of the following combinations: A. b, C, A and B, A and C, B and C, A and B and C.
Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior as well as future uses of such defined words and phrases.
In this patent document, the application combinations of modules and the division levels of sub-modules are for illustration only, and the application combinations of modules and the division levels of sub-modules may have different manners without departing from the scope of the disclosure.
Fig. 1 is a schematic diagram of a conventional current source structure.
As shown in fig. 1, the current source circuit realized by the conventional method is composed of an operational amplifier OP101, a PMOS transistor MP102, a PMOS transistor MP103, and a resistor R104. Wherein the reference voltage VREF is formed by a bandThe bandgap reference source produces a regulated voltage that does not vary with temperature and supply voltage. The operational amplifier OP101 and the transistor MP102 constitute an operational amplifier loop that equalizes the voltages at the two inputs of the operational amplifier OP101, i.e. v1=vref. Current I of transistor MP102 1 ＝V REF /R 104 . Transistor MP102 and transistor MP103 form a set of current mirror structures, and assuming that the size ratio of transistor MP103 to transistor MP102 is M:1, the output current Iref is I REF ＝M×I 1 ＝M×V REF /R 104 . Since the reference voltage VREF does not vary with temperature and the power supply voltage VDD, the output current Iref is also stable from varying with temperature and the power supply voltage VDD in theory.
However, the output current Iref expression of the current source circuit shown in fig. 1 is too idealized. In practical applications, the output current Iref of the transistor MP103 is affected by the variation of the power supply voltage VDD. The transistor MP103 operates in the saturation region, and the output current Iref expression of the transistor MP103 can be expressed as
Wherein mu p Represents mobility, C ox Represents the gate oxide capacitance per unit area, W is the transistor width, L is the transistor length, V GS Is the voltage difference between the gate and source of the transistor, V TH Is the threshold voltage of the transistor, V DS Is the voltage difference between the drain and source of the transistor and λ is the channel length modulation factor.
Fig. 2 is a schematic diagram of the I/V characteristic of a transistor in the case of channel length modulation effect.
As shown in fig. 2, the abscissa represents the source-drain voltage VDS and the ordinate represents the drain current I D . Drain current I of transistor MP103 D As the source-drain voltage VDS varies as shown by the solid line in fig. 2, it can be seen that in the saturation region, the drain current I D As the source-drain voltage VDS increases. The above-mentioned case will be described in detail,in the saturation region, the output current Iref of the current source shown in fig. 1 increases with the increase of the power supply voltage VDD.
Fig. 3 is a schematic diagram of the output current Iref versus supply voltage VDD for a conventional current source implementation.
As shown in fig. 3, the abscissa represents the power supply voltage VDD, and the ordinate represents the output current Iref. The actual value of the output current Iref of the conventional current source deviates from the ideal value during the change of the power supply voltage VDD from 3V to 5V, and increases slowly with the increase of the power supply voltage VDD.
Fig. 4 is a schematic diagram of a high precision current source circuit according to an embodiment of the invention.
Fig. 5 is a schematic diagram of the output current Iref according to the power supply voltage VDD according to the embodiment of the present invention.
As shown in fig. 4 and 5, the high precision current source circuit according to one embodiment of the present invention includes a first current source circuit and a voltage clamping module.
The first current source circuit includes a first operational amplifier OP401, a first transistor MP404, a second transistor MP405, a third transistor MP406, a fourth transistor MP407, and a first resistor R410. Wherein, the negative input end of the first operational amplifier OP401 is connected to the reference voltage VREF, the positive input end of the first operational amplifier OP401 is connected to the first node V1, and the output end of the first operational amplifier OP401 is connected to the gate of the first transistor MP 404; the first transistor MP404 is a PMOS transistor, a source of the first transistor MP404 is connected to the power supply VDD, a drain of the first transistor MP404 is connected to the third node V3, and a gate of the first transistor MP404 is connected to the output terminal of the first operational amplifier OP 401; the second transistor MP405 is a PMOS transistor, a source of the second transistor MP405 is connected to the power supply VDD, a drain of the second transistor MP405 is connected to the fourth node V4, and a gate of the second transistor MP405 is connected to the output terminal of the first operational amplifier OP 401; the third transistor MP406 is a PMOS transistor, a source of the third transistor MP406 is connected to the third node V3, a drain of the third transistor MP406 is connected to the first node V1, and a gate of the third transistor MP406 is connected to the output terminal of the second operational amplifier OP 402; the fourth transistor MP407 is a PMOS transistor, a source of the fourth transistor MP407 is connected to a fourth node V4, and a gate of the fourth transistor MP407 is connected to the output end of the third operational amplifier OP 403; one end of the first resistor R410 is grounded, and the other end of the first resistor R410 is connected to the first node V1. The first operational amplifier OP401, the first transistor MP404, and the third transistor MP406 form a first loop.
Specifically, the reference voltage VREF is configured as a reference voltage that does not vary with the power supply voltage and temperature, and may be implemented by a bandgap reference source circuit. The drain of the fourth transistor MP407 is configured to output the output current Iref of the current source. The voltage at the positive input end of the first operational amplifier OP401 is a first voltage V1, the voltage at the negative input end of the first operational amplifier OP401 is a reference voltage VREF, and the voltage at the positive input end of the first operational amplifier OP401 is equal to the voltage at the negative input end thereof, that is, v1=vref. First current I 1 Can be calculated by using the reference voltage VREF and the first resistor R410, i.e. 1 ＝V REF /R 410 。
The voltage clamping module includes a second operational amplifier OP402, a third operational amplifier OP403, a second resistor R411, a current source 412, a fifth transistor MN408, and a sixth transistor MN409 for providing a clamped source-drain voltage for the first current source circuit. Wherein the negative input terminal of the second operational amplifier OP402 is connected to the third node V3, the positive input terminal of the second operational amplifier OP402 is connected to the second node V2, and the output terminal of the second operational amplifier is connected to the gate of the third transistor MP 406; a negative input end of the third operational amplifier OP403 is connected to a fourth node V4, a positive input end of the third operational amplifier OP403 is connected to a third node V3, and an output end of the third operational amplifier OP403 is connected to a gate of the fourth transistor MP 407; one end of the second resistor R411 is connected to the power supply VDD, and the other end of the second resistor R411 is connected to the second node V2; one end of the current source 412 is connected to the power supply VDD and the second resistor R411, and the other end of the current source 412 is connected to the drain of the fifth transistor MN 408; the fifth transistor MN408 is an NMOS transistor, the gate of the fifth transistor MN408 is connected to the drain thereof and the gate of the sixth transistor MN409, and the source of the fifth transistor MN408 is grounded; the sixth transistor MN409 is an NMOS transistor, the source of the sixth transistor MN409 is grounded, the drain of the sixth transistor MN409 is connected to the second node V2, and the gate of the sixth transistor MN409 is connected to the gate of the fifth transistor MN 408. The second operational amplifier OP402 and the third transistor MP406 form a second loop. The third operational amplifier OP403 and the fourth transistor MP407 form a third loop.
Specifically, the current source 412 is configured to output a second current Ib. And the voltage clamping module provides the voltage of the second node V2 by selecting the value of the second resistor R411 and the value of the second current Ib output by the current source 412, thereby fixing the source-drain voltage VDS1 of the first transistor MP404 and the source-drain voltage VDS2 of the second transistor MP 405. Specifically, the voltage at the positive input end of the second operational amplifier OP402 is the second voltage V2, the voltage at the negative input end of the second operational amplifier OP402 is the third voltage V3, and the voltage at the positive input end of the second operational amplifier OP402 is equal to the voltage at the negative input end thereof, that is, v2=v3. The voltage at the positive input end of the third operational amplifier OP403 is a third voltage V3, the voltage at the negative input end of the third operational amplifier OP403 is a fourth voltage V4, and the voltage at the positive input end of the third operational amplifier OP403 is equal to the voltage at the negative input end thereof, that is, v4=v3; further, v2=v3=v4 is obtained. Based on the above, the source-drain voltage VDS1 of the first transistor MP404 is equal to the source-drain voltage VDS2 of the second transistor MP405, i.e., V DS1 ＝V DS2 ＝VDD-V 2 。
The first transistor MP404 and the second transistor MP405 form a first current mirror module for providing a first current I 1 . Wherein the method comprises the steps ofIn the case where the ratio of the size of the second transistor MP405 to the size of the first transistor MP404 is M:1, the output current Iref is I REF ＝M×I 1 ＝M×V REF /R 410 。
The fifth transistor MN408 and the sixth transistor MN409 constitute a second current mirror module. Wherein VDD-V 2 ＝I b ·R 411 Further, V DS1 ＝V DS2 ＝I b ·R 411 。
Based on the above, the source-drain voltage VDS (the source-drain voltage VDS1 of the first transistor MP404 and the source-drain voltage VDS2 of the second transistor MP 405) is a fixed value, and thus the output current Iref is:
the output current Iref is not affected by the variation of the source drain voltage VDS, i.e. the output current Iref remains constant in case of a variation of the supply voltage VDD.
As shown in fig. 5, the abscissa represents the power supply voltage VDD, and the ordinate represents the output current Iref of the current source. The solid line representing the actual value of the output current Iref coincides with the solid line representing the ideal value of the output current Iref in fig. 5, which illustrates that the actual value of the output current Iref remains equal to the ideal value of the output current Iref and the output current Iref remains constant with the change of the supply voltage VDD, when the supply voltage VDD is changed from 3V to 5V.
Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. The disclosure is intended to embrace such alterations and modifications that fall within the scope of the appended claims.
Any description of the present invention should not be construed as implying that any particular element, step, or function is a necessary element to be included in the scope of the claims. The scope of patented subject matter is defined only by the claims.
Claims (9)
1. A high precision current source circuit comprising:
the first current source circuit comprises a first operational amplifier, a first transistor, a second transistor and a first resistor, wherein the positive input end of the first operational amplifier is connected with a first node, the negative input end of the first operational amplifier is connected with a reference voltage node, and the output end of the first operational amplifier is connected with the grid electrode of the first transistor and the grid electrode of the second transistor; a source of the first transistor is connected to a power supply voltage, and a drain thereof is connected to the first resistor through a first node; the source electrode of the second transistor is connected to the power supply voltage, and the drain electrode of the second transistor is connected with the output node through a fourth node; one end of the first resistor is connected to the first node, and the other end of the first resistor is connected to a ground node; and
a voltage clamping module configured to provide a fixed source-drain voltage to the first transistor and the second transistor of the first current source circuit,
wherein the first current source circuit further comprises a third transistor, and the voltage clamp module comprises a second operational amplifier,
wherein the source of the third transistor is connected to a third node connected to the drain of the first transistor, the drain of the third transistor is connected to the first node, the gate of the third transistor is connected to the output of the second operational amplifier,
the positive input end of the second operational amplifier is connected with the first bias voltage node, and the negative input end of the second operational amplifier is connected with the third node.
2. The high precision current source circuit of claim 1, wherein the voltage clamp module further comprises a bias circuit module configured to provide a bias voltage to the high precision current source circuit through a bias voltage output node.
3. The high precision current source circuit of claim 2, wherein the bias circuit module comprises a first bias current source, a second resistor, a fifth transistor, and a sixth transistor,
wherein one end of the first bias current source is connected to a power supply node, and the other end thereof is connected to a drain of the fifth transistor; one end of the second resistor is connected with a power supply node, and the other end of the second resistor is connected to a bias voltage output node; a gate of the fifth transistor is connected with a gate of the sixth transistor, a source of the fifth transistor is grounded, and a drain of the fifth transistor is connected with the gate; and a drain of the sixth transistor is connected to the bias voltage output node, and a source of the sixth transistor is grounded.
4. The high precision current source circuit of claim 3 wherein the bias voltage output node is connected to the first bias voltage node.
5. A high precision current source circuit comprising:
the first current source circuit comprises a first operational amplifier, a first transistor, a second transistor and a first resistor, wherein the positive input end of the first operational amplifier is connected with a first node, the negative input end of the first operational amplifier is connected with a reference voltage node, and the output end of the first operational amplifier is connected with the grid electrode of the first transistor and the grid electrode of the second transistor; a source of the first transistor is connected to a power supply voltage, and a drain thereof is connected to the first resistor through a first node; the source electrode of the second transistor is connected to the power supply voltage, and the drain electrode of the second transistor is connected with the output node through a fourth node; one end of the first resistor is connected to the first node, and the other end of the first resistor is connected to a ground node; and
a voltage clamping module configured to provide a fixed source-drain voltage to the first transistor and the second transistor of the first current source circuit,
wherein the first current source circuit further comprises a fourth transistor, and the voltage clamp module further comprises a third operational amplifier,
wherein the source of the fourth transistor is connected to a fourth node connected to the drain of the second transistor, the drain of the fourth transistor is connected to an output node, the gate of the fourth transistor is connected to the output of the third operational amplifier,
the positive input end of the third operational amplifier is connected with the second bias voltage node, and the negative input end of the third operational amplifier is connected with the fourth node.
6. The high precision current source circuit of claim 5, wherein the second bias voltage node is connected to a drain of the first transistor.
7. The high precision current source circuit of claim 5, wherein the voltage clamp module further comprises a bias circuit module configured to provide a bias voltage to the high precision current source circuit through a bias voltage output node.
8. The high precision current source circuit of claim 7, wherein the bias circuit module comprises a first bias current source, a second resistor, a fifth transistor, and a sixth transistor,
wherein one end of the first bias current source is connected to a power supply node, and the other end thereof is connected to a drain of the fifth transistor; one end of the second resistor is connected with a power supply node, and the other end of the second resistor is connected to a bias voltage output node; a gate of the fifth transistor is connected with a gate of the sixth transistor, a source of the fifth transistor is grounded, and a drain of the fifth transistor is connected with the gate; and a drain of the sixth transistor is connected to the bias voltage output node, and a source of the sixth transistor is grounded.
9. The high precision current source circuit of claim 8, wherein the bias voltage output node is connected to the second bias voltage node.
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| Title |
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| 一种具有高稳定性的带隙基准电路;宋晶;刘诗斌;张勇;谭慧宇;;微电子学(第03期);444-447 * |
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| Publication number | Publication date |
|---|---|
| CN114415773A (en) | 2022-04-29 |
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