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CN114415773A - High-precision current source circuit - Google Patents

High-precision current source circuit Download PDF

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Publication number
CN114415773A
CN114415773A CN202210068239.7A CN202210068239A CN114415773A CN 114415773 A CN114415773 A CN 114415773A CN 202210068239 A CN202210068239 A CN 202210068239A CN 114415773 A CN114415773 A CN 114415773A
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transistor
node
current source
operational amplifier
voltage
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CN114415773B (en
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路宁
王佩瑶
孙鹏林
党艳杰
李孟
段连成
亓巧云
李侃
孟浩
钱永学
蔡光杰
黄鑫
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Guangzhou Aung Rui Microelectronics Technology Co ltd
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Guangzhou Aung Rui Microelectronics Technology Co ltd
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    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current 
    • G05F1/46Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices

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Abstract

The invention provides a high-precision current source circuit, which comprises: a first current source circuit including a first operational amplifier, a first transistor, a second transistor, and a first resistor, wherein a positive input terminal of the first operational amplifier is connected to a first node, a negative input terminal of the first operational amplifier is connected to a reference voltage node, and an output terminal of the first operational amplifier is connected to a gate of the first transistor and a gate of the second transistor; the source of the first transistor is connected to a power supply voltage, and the drain of the first transistor is connected to the first resistor through a first node; the source of the second transistor is connected to a power supply voltage, and the drain of the second transistor is connected with the output node through a fourth node; one end of the first resistor is connected to the first node, and the other end of the first resistor is connected to a ground node; and a voltage clamping module configured to provide a fixed source-drain voltage to the first transistor and the second transistor of the first current source circuit.

Description

High-precision current source circuit
Technical Field
The invention relates to the field of analog integrated circuit design, in particular to a high-precision current source circuit.
Background
In analog integrated circuits, current sources are a very important module. The current source is used as a reference source of the circuit, provides accurate bias current for other modules of the circuit, and is widely applied to circuits such as an operational amplifier, a comparator, a phase-locked loop, a digital-to-analog converter and the like.
The accuracy of the current source determines the performance of the entire analog circuitry. The current source is required to be able to output a stable current value that does not vary with temperature and power supply voltage. Conventionally, a current source circuit includes an operational amplifier, a PMOS transistor, and a resistor. The reference voltage VREF of the operational amplifier is a stable voltage which is generated by a band-gap reference source and does not change along with temperature and power supply voltage. In the conventional current source structure, since the output current Iref of the current source is theoretically proportional to the reference voltage VREF, and since the reference voltage VREF does not vary with the temperature and the power supply voltage VDD, the output current Iref is also theoretically stable against the temperature and the power supply voltage VDD.
However, the relationship between the output current Iref and the reference voltage VREF is too ideal. In practical applications, the output current Iref may be affected by variations in the supply voltage VDD due to channel length modulation effects. Specifically, during the variation of the power supply voltage, the source-drain voltage VDS of the transistor will vary accordingly and the actual value of the output current Iref of the current source will deviate from the ideal value and increase slowly with the increase of the power supply voltage VDD. This causes the conventional current source to fail to meet the requirement for a constant current output.
In view of the above technical problems, a high-precision current source circuit is needed to provide a reliable solution, so as to keep the output current of the current source constant during the variation of the power supply voltage and under the condition of temperature variation, thereby obtaining a high-precision current output.
Disclosure of Invention
Solves the technical problem
In practical applications, under the influence of the channel length modulation effect, the actual value of the output current Iref of the current source deviates from the ideal value under the influence of the variation of the power supply voltage VDD, and slowly increases with the increase of the power supply voltage VDD, which makes it difficult to meet the requirement of constant output high-precision current.
Technical scheme
In order to solve the above problems, the present invention provides a high-precision current source circuit.
According to an aspect of the present invention, there is provided a high-precision current source circuit including: a first current source circuit including a first operational amplifier, a first transistor, a second transistor, and a first resistor, wherein a positive input terminal of the first operational amplifier is connected to a first node, a negative input terminal of the first operational amplifier is connected to a reference voltage node, and an output terminal of the first operational amplifier is connected to a gate of the first transistor and a gate of the second transistor; the source of the first transistor is connected to a power supply voltage, and the drain of the first transistor is connected to the first resistor through a first node; the source of the second transistor is connected to a power supply voltage, and the drain of the second transistor is connected with the output node through a fourth node; one end of the first resistor is connected to the first node, and the other end of the first resistor is connected to a ground node; and a voltage clamping module configured to provide a fixed source-drain voltage to the first transistor and the second transistor of the first current source circuit.
According to another aspect of the present invention, there is provided a high-precision current source circuit, wherein the first current source circuit further comprises a third transistor, and the voltage clamping module comprises a second operational amplifier, wherein a source of the third transistor is connected to a third node connected to a drain of the first transistor, a drain of the third transistor is connected to the first node, and a gate of the third transistor is connected to an output terminal of the second operational amplifier, wherein a positive input terminal of the second operational amplifier is connected to the first bias voltage node, and a negative input terminal of the second operational amplifier is connected to the third node.
According to another aspect of the present invention, there is provided a high-precision current source circuit, wherein the first current source circuit further comprises a fourth transistor, and the voltage clamp module further comprises a third operational amplifier, wherein a source of the fourth transistor is connected to a fourth node connected to a drain of the second transistor, a drain of the fourth transistor is connected to an output node, and a gate of the fourth transistor is connected to an output terminal of the third operational amplifier, wherein a positive input terminal of the third operational amplifier is connected to a second bias voltage node, and a negative input terminal of the third operational amplifier is connected to the fourth node.
According to another aspect of the present invention, there is provided a high-precision current source circuit, wherein the second bias voltage node is connected to the third node.
According to another aspect of the present invention, there is provided a high-precision current source circuit, wherein the first bias voltage node is connected to the second bias voltage node.
According to another aspect of the present invention, there is provided a high-precision current source circuit, wherein the voltage clamping module further comprises a bias circuit module, and the first bias circuit module is configured to provide a bias voltage to the high-precision current source circuit through a bias voltage output node.
According to another aspect of the present invention, there is provided a high-precision current source circuit, wherein a bias circuit block includes a first bias current source, a second resistor, a fifth transistor, and a sixth transistor, wherein one end of the first bias current source is connected to a power supply node, and the other end thereof is connected to a drain of the fifth transistor; one end of the second resistor is connected with a power supply node, and the other end of the second resistor is connected with a bias voltage output node; a gate of the fifth transistor is connected to a gate of the sixth transistor, a source of the fifth transistor is grounded, and a drain of the fifth transistor is connected to the gate; and the drain of the sixth transistor is connected to the bias voltage output node, and the source of the sixth transistor is grounded.
According to another aspect of the present invention, there is provided a high-precision current source circuit, wherein the bias voltage output node is connected to the first bias voltage node.
According to another aspect of the present invention, there is provided a high-precision current source circuit, wherein the bias voltage output node is connected to the first bias voltage node and the second bias voltage node.
Advantageous effects
Compared with the prior art, the invention provides a high-precision current source circuit, which has the following beneficial effects: a voltage clamping circuit is formed by the operational amplifier, so that the source-drain voltage VDS of the transistor in the current source is kept constant and does not change along with the power supply voltage, and the output current of the current source is kept constant in the change process of the power supply voltage and under the condition of temperature change; in addition, the influence of the channel length modulation effect on the output current is eliminated, so that the high-precision output current can be obtained, and the high-precision current output is realized.
Drawings
FIG. 1 is a schematic diagram of a conventional current source configuration;
FIG. 2 is a schematic diagram of the I/V characteristic of a transistor for channel length modulation effects;
FIG. 3 is a graph of output current Iref versus supply voltage VDD for a conventional current source implementation;
FIG. 4 is a schematic diagram of a high precision current source circuit according to an embodiment of the present invention; and
fig. 5 is a diagram illustrating a variation curve of the output current Iref with the power supply voltage VDD according to an embodiment of the present invention.
Detailed Description
Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "couple," "connect," and derivatives thereof refer to any direct or indirect communication or connection between two or more elements, whether or not those elements are in physical contact with one another. The terms "transmit," "receive," and "communicate," as well as derivatives thereof, encompass both direct and indirect communication. The terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation. The term "or" is inclusive, meaning and/or. The phrase "associated with … …" and derivatives thereof means including, included within … …, interconnected, contained within … …, connected or connected with … …, coupled or coupled with … …, in communication with … …, mated, interwoven, juxtaposed, proximate, bound or bound with … …, having an attribute, having a relationship or having a relationship with … …, and the like. The term "controller" refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and/or firmware. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. The phrase "at least one of, when used with a list of items, means that a different combination of one or more of the listed items can be used and only one item in the list may be required. For example, "at least one of A, B, C" includes any one of the following combinations: A. b, C, A and B, A and C, B and C, A and B and C.
Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.
In this patent document, the application combination of modules and the division levels of sub-modules are only used for illustration, and the application combination of modules and the division levels of sub-modules may have different manners without departing from the scope of the present disclosure.
Fig. 1 is a schematic diagram of a conventional current source structure.
As shown in fig. 1, the current source circuit implemented by the conventional method is composed of an operational amplifier OP101, a PMOS transistor MP102, a PMOS transistor MP103, and a resistor R104. The reference voltage VREF is a stable voltage which is generated by a band-gap reference source and does not change along with the temperature and the power supply voltage. The operational amplifier OP101 and the transistor MP102 constitute an operational amplifier loop, which makes the voltages at the two input terminals of the operational amplifier OP101 equal, i.e., V1 equals VREF. Current I of transistor MP1021=VREF/R104. The transistor MP102 and the transistor MP103 form a current mirror structure, and assuming that the size ratio of the transistor MP103 to the transistor MP102 is M:1, the output current Iref is IREF=M×I1=M×VREF/R104. Since the reference voltage VREF does not vary with temperature and the power supply voltage VDD, the output current Iref is also stable theoretically against temperature and the power supply voltage VDD.
However, the output current Iref expression of the current source circuit shown in fig. 1 is too idealized. In practical applications, the output current Iref of the transistor MP103 is affected by the variation of the power supply voltage VDD. The transistor MP103 operates in the saturation region, and the output current Iref of the transistor MP103 can be expressed as the expression of
Figure BDA0003481062000000051
Wherein, mupDenotes mobility, CoxTo representGate oxide capacitance per unit area, W is transistor width, L is transistor length, VGSIs the voltage difference between the gate and the source of the transistor, VTHIs the threshold voltage, V, of the transistorDSIs the voltage difference between the drain and source of the transistor and λ is the channel length modulation factor.
Fig. 2 is a schematic diagram of the I/V characteristic of a transistor in the case of channel length modulation effects.
As shown in fig. 2, the source-drain voltage VDS is plotted on the abscissa, and the drain current I is plotted on the ordinateD. Drain current I of transistor MP103DAs the variation of the source-drain voltage VDS is shown as a solid line in fig. 2, it can be seen that the drain current I is in a saturation regionDIncreases as the source-drain voltage VDS increases. The above situation illustrates that in the saturation region, the output current Iref of the current source shown in fig. 1 increases with the increase of the power supply voltage VDD.
Fig. 3 is a diagram of the output current Iref versus supply voltage VDD for a conventional current source implementation.
As shown in fig. 3, the abscissa is the power supply voltage VDD and the ordinate is the output current Iref. During the variation of the power supply voltage VDD from 3V to 5V, the actual value of the output current Iref of the conventional current source deviates from the ideal value and slowly increases as the power supply voltage VDD increases.
Fig. 4 is a schematic diagram of a high-precision current source circuit according to an embodiment of the invention.
Fig. 5 is a diagram illustrating a variation curve of the output current Iref with the power supply voltage VDD according to an embodiment of the present invention.
As shown in fig. 4 and 5, a high-precision current source circuit according to an embodiment of the present invention includes a first current source circuit and a voltage clamping module.
The first current source circuit includes a first operational amplifier OP401, a first transistor MP404, a second transistor MP405, a third transistor MP406, a fourth transistor MP407, and a first resistor R410. Wherein a negative input terminal of the first operational amplifier OP401 is connected to a reference voltage VREF, a positive input terminal of the first operational amplifier OP401 is connected to a first node V1, and an output terminal of the first operational amplifier OP401 is connected to a gate of the first transistor MP 404; the first transistor MP404 is a PMOS transistor, a source of the first transistor MP404 is connected to a power supply VDD, a drain of the first transistor MP404 is connected to a third node V3, and a gate of the first transistor MP404 is connected to an output terminal of the first operational amplifier OP 401; the second transistor MP405 is a PMOS transistor, a source of the second transistor MP405 is connected to a power supply VDD, a drain of the second transistor MP405 is connected to a fourth node V4, and a gate of the second transistor MP405 is connected to an output terminal of the first operational amplifier OP 401; the third transistor MP406 is a PMOS transistor, the source of the third transistor MP406 is connected to the third node V3, the drain of the third transistor MP406 is connected to the first node V1, and the gate of the third transistor MP406 is connected to the output terminal of the second operational amplifier OP 402; the fourth transistor MP407 is a PMOS transistor, the source of the fourth transistor MP407 is connected to a fourth node V4, and the gate of the fourth transistor MP407 is connected to the output terminal of the third operational amplifier OP 403; one end of the first resistor R410 is grounded, and the other end of the first resistor R410 is connected to a first node V1. The first operational amplifier OP401, the first transistor MP404, and the third transistor MP406 form a first loop.
Specifically, the reference voltage VREF is configured as a reference voltage that does not vary with the power supply voltage and temperature, and may be implemented by a bandgap reference source circuit. The drain of the fourth transistor MP407 is configured to output the output current Iref of the current source. The voltage of the positive input end of the first operational amplifier OP401 is a first voltage V1, the voltage of the negative input end of the first operational amplifier OP401 is a reference voltage VREF, and the voltage of the positive input end of the first operational amplifier OP401 is equal to the voltage of the negative input end thereof, that is, V1 is equal to VREF. A first current I1Can be calculated by using a reference voltage VREF and the first resistor R410, i.e. I1=VREF/R410
The voltage clamping module includes a second operational amplifier OP402, a third operational amplifier OP403, a second resistor R411, a current source 412, a fifth transistor MN408, and a sixth transistor MN409, and is configured to provide a clamped source-drain voltage for the first current source circuit. Wherein a negative input terminal of the second operational amplifier OP402 is connected to a third node V3, a positive input terminal of the second operational amplifier OP402 is connected to a second node V2, and an output terminal of the second operational amplifier is connected to a gate of the third transistor MP 406; a negative input terminal of the third operational amplifier OP403 is connected to a fourth node V4, a positive input terminal of the third operational amplifier OP403 is connected to a third node V3, and an output terminal of the third operational amplifier OP403 is connected to a gate of the fourth transistor MP 407; one end of the second resistor R411 is connected to a power supply VDD, and the other end of the second resistor R411 is connected to a second node V2; one end of the current source 412 is connected to the power supply VDD and the second resistor R411, and the other end of the current source 412 is connected to the drain of the fifth transistor MN 408; the fifth transistor MN408 is an NMOS transistor, a gate of the fifth transistor MN408 is connected to a drain thereof and a gate of the sixth transistor MN409, and a source of the fifth transistor MN408 is grounded; the sixth transistor MN409 is an NMOS transistor, a source of the sixth transistor MN409 is grounded, a drain of the sixth transistor MN409 is connected to the second node V2, and a gate of the sixth transistor MN409 is connected to a gate of the fifth transistor MN 408. The second operational amplifier OP402 and the third transistor MP406 constitute a second loop circuit. The third operational amplifier OP403 and the fourth transistor MP407 form a third loop.
Specifically, the current source 412 is configured to output a second current Ib. And the voltage clamping module provides the voltage of the second node V2 by selecting the value of the second resistor R411 and the value of the second current Ib output by the current source 412, so as to fix the source-drain voltage VDS1 of the first transistor MP404 and the source-drain voltage VDS2 of the second transistor MP 405. Specifically, the voltage at the positive input end of the second operational amplifier OP402 is a second voltage V2, the voltage at the negative input end of the second operational amplifier OP402 is a third voltage V3, and the second operational amplifier OP402 is a third voltage V3The voltage at the positive input of OP402 is equal to the voltage at its negative input, i.e., V2-V3. The voltage at the positive input end of the third operational amplifier OP403 is a third voltage V3, the voltage at the negative input end of the third operational amplifier OP403 is a fourth voltage V4, and the voltage at the positive input end of the third operational amplifier OP403 is equal to the voltage at the negative input end thereof, that is, V4 is equal to V3; further, V2 ═ V3 ═ V4 was obtained. Based on the above situation, the source-drain voltage VDS1 of the first transistor MP404 is equal to the source-drain voltage VDS2 of the second transistor MP405, i.e. VDS1=VDS2=VDD-V2
The first transistor MP404 and the second transistor MP405 form a first current mirror module for providing a first current I1. Wherein, when the ratio of the size of the second transistor MP405 to the size of the first transistor MP404 is M:1, the output current Iref is IREF=M×I1=M×VREF/R410
The fifth transistor MN408 and the sixth transistor MN409 constitute a second current mirror block. Wherein, VDD-V2=Ib·R411Further, VDS1=VDS2=Ib·R411
Based on the above situation, the source-drain voltage VDS (the source-drain voltage VDS1 of the first transistor MP404 and the source-drain voltage VDS2 of the second transistor MP 405) is a fixed value, so the output current Iref is:
Figure BDA0003481062000000081
the output current Iref is not affected by variations in the source-drain voltage VDS, i.e. the output current Iref remains constant in case of variations in the supply voltage VDD.
As shown in fig. 5, the abscissa is the power supply voltage VDD and the ordinate is the output current Iref of the current source. The solid line in fig. 5 representing the actual value of the output current Iref coincides with the solid line representing the ideal value of the output current Iref, which means that the actual value of the output current Iref and the ideal value of the output current Iref remain equal and the output current Iref remains constant with changes in the supply voltage VDD during changes in the supply voltage VDD from 3V to 5V.
Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. The present disclosure is intended to embrace such alterations and modifications as fall within the scope of the appended claims.
None of the description in this specification should be read as implying that any particular element, step, or function is an essential element which must be included in the claim scope. The scope of patented subject matter is defined only by the claims.

Claims (9)

1. A high-precision current source circuit comprising:
a first current source circuit including a first operational amplifier, a first transistor, a second transistor, and a first resistor, wherein a positive input terminal of the first operational amplifier is connected to a first node, a negative input terminal of the first operational amplifier is connected to a reference voltage node, and an output terminal of the first operational amplifier is connected to a gate of the first transistor and a gate of the second transistor; the source of the first transistor is connected to a power supply voltage, and the drain of the first transistor is connected to the first resistor through a first node; the source of the second transistor is connected to a power supply voltage, and the drain of the second transistor is connected with the output node through a fourth node; one end of the first resistor is connected to the first node, and the other end of the first resistor is connected to a ground node; and
a voltage clamping module configured to provide a fixed source-drain voltage to the first transistor and the second transistor of the first current source circuit.
2. The high accuracy current source circuit of claim 1, wherein the first current source circuit further comprises a third transistor and the voltage clamping module comprises a second operational amplifier,
wherein a source of the third transistor is connected to a third node connected to a drain of the first transistor, a drain of the third transistor is connected to the first node, a gate of the third transistor is connected to an output terminal of the second operational amplifier,
and a positive input end of the second operational amplifier is connected with a first bias voltage node, and a negative input end of the second operational amplifier is connected with the third node.
3. The high accuracy current source circuit of claim 1, wherein the first current source circuit further comprises a fourth transistor and the voltage clamp module further comprises a third operational amplifier,
wherein a source of the fourth transistor is connected to a fourth node connected to a drain of the second transistor, a drain of the fourth transistor is connected to an output node, a gate of the fourth transistor is connected to an output terminal of the third operational amplifier,
and a positive input end of the third operational amplifier is connected with a second bias voltage node, and a negative input end of the third operational amplifier is connected with the fourth node.
4. A high accuracy current source circuit according to claim 3, wherein said second bias voltage node is connected to said third node.
5. A high accuracy current source circuit according to claim 2 or 3, wherein the first bias voltage node is connected to the second bias voltage node.
6. The high accuracy current source circuit of claim 1, wherein the voltage clamping module further comprises a bias circuit module, the first bias circuit module configured to provide a bias voltage to the high accuracy current source circuit through a bias voltage output node.
7. The high accuracy current source circuit of claim 6, wherein the bias circuit block comprises a first bias current source, a second resistor, a fifth transistor, and a sixth transistor,
wherein one end of the first bias current source is connected to a power supply node, and the other end thereof is connected to a drain of the fifth transistor; one end of the second resistor is connected with a power supply node, and the other end of the second resistor is connected with a bias voltage output node; a gate of the fifth transistor is connected to a gate of the sixth transistor, a source of the fifth transistor is grounded, and a drain of the fifth transistor is connected to the gate; and the drain of the sixth transistor is connected to the bias voltage output node, and the source of the sixth transistor is grounded.
8. A high accuracy current source circuit according to claim 4 or 7 wherein the bias voltage output node is connected to the first bias voltage node.
9. A high accuracy current source circuit according to claim 5 or 7 wherein the bias voltage output node is connected to the first and second bias voltage nodes.
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