CN114389592A - Level shift circuit - Google Patents

Abstract

A level shifting circuit. The level conversion circuit includes: an input sub-circuit, an isolation sub-circuit and an output sub-circuit; wherein, the input sub-circuit includes: a first NMOS transistor, a second NMOS transistor, and an inverter; the output sub-circuit includes: a first PMOS transistor and a second PMOS transistor; the first NMOS transistor and the second NMOS transistor, the source is grounded, and the drain is connected to the isolation sub-circuit; the isolation sub-circuit is connected to the first PMOS transistor and the second NMOS transistor. The drains of the two PMOS transistors are connected; the threshold voltages of the first NMOS transistor and the second NMOS transistor are smaller than the threshold voltages of the first PMOS transistor and the second PMOS transistor; the isolation sub-circuit is used to connect the The input sub-circuit and the output sub-circuit provide suitable drain voltages for the first NMOS transistor and the second NMOS transistor. By applying the above solution, the level conversion speed of the level conversion circuit can be improved.

Description

Level shift circuit

technical field

The invention relates to the field of electronic circuits, in particular to a level conversion circuit.

Background technique

Semiconductor memories usually have level shifting circuits for converting logic levels to desired high or low voltages.

In the existing level conversion circuit, the used complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) transistors are all high voltage CMOS transistors. The so-called high-voltage CMOS tube is a CMOS tube that can be used to transmit high voltage, and the high voltage is at least greater than the input logic level value. The typical value (Vt) of the threshold voltage of the high-voltage CMOS transistor is about 1.0V, and some may even be higher than 1.0V.

Since the saturation current value of the CMOS tube is inversely proportional to the threshold voltage of the MOS tube, the higher the threshold voltage of the CMOS tube, the smaller the saturation current value of the CMOS tube, and the smaller the current flowing through the CMOS tube during the level conversion process. , which results in a longer inversion time and a slower level conversion speed of the existing level conversion circuit.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is to improve the level conversion speed of the level conversion circuit.

In order to solve the above technical problem, an embodiment of the present invention provides a level conversion circuit, the level conversion circuit includes: an input sub-circuit, an isolation sub-circuit and an output sub-circuit; wherein, the input sub-circuit includes: a first NMOS circuit tube, a second NMOS tube, and an inverter; the output sub-circuit includes: a first PMOS tube and a second PMOS tube;

The gate of the first NMOS transistor is connected to the logic signal output terminal and the input terminal of the inverter; the output terminal of the inverter is connected to the gate of the second NMOS transistor; the first NMOS transistor tube and the second NMOS tube, the source is grounded, and the drain is connected to the isolator circuit; the isolator circuit is connected to the drain of the first PMOS tube and the second PMOS tube; the first PMOS tube The gate is connected to the drain of the second PMOS tube, and the gate of the second PMOS tube is connected to the drain of the first PMOS tube; the sources of the first PMOS tube and the second PMOS tube are connected to Power supply voltage output connection;

The threshold voltages of the first NMOS transistor and the second NMOS transistor are smaller than the threshold voltages of the first PMOS transistor and the second PMOS transistor; the isolation sub-circuit is used to connect the input sub-circuit and the output sub-circuit, And provide a suitable drain voltage for the first NMOS transistor and the second NMOS transistor.

Optionally, the isolation sub-circuit includes: a third NMOS transistor and a fourth NMOS transistor; wherein:

The gates of the third NMOS transistor and the fourth NMOS transistor are both connected to the power supply voltage output terminal; the source of the third NMOS transistor is connected to the drain of the first NMOS transistor; the fourth NMOS transistor The source of the NMOS transistor is connected to the drain of the second NMOS transistor; the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor; the drain of the fourth NMOS transistor is connected to the drain of the second NMOS transistor The drain connection of the PMOS tube;

The threshold voltages of the third NMOS transistor and the fourth NMOS transistor are lower than the threshold voltages of the first NMOS transistor and the second NMOS transistor.

Optionally, the typical values of the threshold voltages of the third NMOS transistor and the fourth NMOS transistor are greater than or equal to 0V and less than or equal to 0.2V.

Optionally, the level conversion circuit further includes: a fifth NMOS transistor, the fifth NMOS transistor is connected in parallel with the first PMOS transistor, and the gate of the fifth NMOS transistor is connected to the output of the inverter end connection.

Optionally, the level conversion circuit further includes: a sixth NMOS transistor, the sixth NMOS transistor is connected in parallel with the second PMOS transistor, and the gate of the sixth NMOS transistor is connected to the logic signal output terminal .

Optionally, the typical values of the threshold voltages of the fifth NMOS transistor and the sixth NMOS transistor are greater than or equal to 1V.

Optionally, the typical values of the threshold voltages of the first PMOS transistor and the second PMOS transistor are greater than or equal to 1.

Optionally, the typical values of the threshold voltages of the first NMOS transistor and the second NMOS transistor are greater than or equal to 0.7V and less than or equal to 0.8V.

Optionally, the inverter is composed of CMOS transistors.

Optionally, the typical value of the threshold voltage of the CMOS transistor in the inverter is greater than or equal to 0.7V and less than or equal to 0.8V.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

With the above solution, one end of the isolation sub-circuit is connected to the drains of the first NMOS transistor and the second NMOS transistor, and the other end is connected to the drains of the first PMOS transistor and the second PMOS transistor, and the isolation sub-circuit can be connected The input sub-circuit and the output sub-circuit can enable the isolation sub-circuit to convert the drain voltage of the first PMOS tube and the second PMOS tube into a drain voltage suitable for the first NMOS tube and the second NMOS tube, Furthermore, when the threshold voltages of the first NMOS transistor and the second NMOS transistor are smaller than the threshold voltages of the first PMOS transistor and the second PMOS transistor, the threshold voltage of the first NMOS transistor and the second NMOS transistor is the same as the threshold voltage of the first NMOS transistor and the second NMOS transistor. When the threshold voltages of the first PMOS transistor and the second PMOS transistor are equal, the solution of the present invention can make the current flowing from the input sub-circuit to the output sub-circuit larger, thereby improving the level conversion speed.

Further, by setting the fifth NMOS tube or the sixth NMOS tube, both the fifth NMOS tube and the sixth NMOS tube are connected to the input sub-circuit, so that the speed of charging and discharging of the output terminal can be further improved, and the level conversion speed can be further improved. .

Description of drawings

1 is a schematic structural diagram of a level conversion circuit;

2 is a schematic structural diagram of a level conversion circuit in an embodiment of the present invention;

3 is a schematic structural diagram of another level conversion circuit in an embodiment of the present invention;

FIG. 4 is a schematic diagram showing the comparison of the simulation results of the level conversion speed between the level conversion circuit in FIG. 1 and the level conversion circuit in the present invention.

Detailed ways

FIG. 1 is a schematic structural diagram of a conventional level conversion circuit. Referring to FIG. 1 , the circuit conversion circuit 10 may include: an inverter 11 , a first MOS transistor P1 , a second MOS transistor P2 , a third MOS transistor N1 and a fourth MOS transistor N2 . The first MOS transistor P1 and the second MOS transistor P2 are PMOS transistors, and the third MOS transistor N1 and the fourth MOS transistor N2 are NMOS transistors.

The input terminal of the inverter 11 and the gate of the third MOS transistor N1 are connected to the logic signal output terminal IN. The drain of the third MOS transistor N1 is connected to the drain of the first MOS transistor P1. The gate of the fourth MOS transistor N2 is connected to the output end of the inverter 11 . The source of the fourth MOS transistor N2 and the source of the third MOS transistor N1 are both connected to the ground line VSS. The sources of the first MOS transistor P1 and the second MOS transistor P2 are both connected to the power supply voltage output terminal VDD. The gate of the first MOS transistor P1 is connected to the drain of the second MOS transistor P2 and the drain of the fourth MOS transistor N2. The gate of the second MOS transistor P2 is connected to the drain of the first MOS transistor P1.

When the voltage of the logic signal output by the logic signal output terminal IN is at a high level, the third MOS transistor N1 is turned on, and the fourth MOS transistor N2 is turned off, so that the gate voltage of the second MOS transistor P2 is at a low level, thereby making The second MOS transistor P2 is turned on, and the output voltage value of the output terminal out is close to the voltage output by the power supply voltage output terminal VDD, which is a high level.

When the voltage of the logic signal output by the logic signal output terminal IN is at a low level, the third MOS transistor N1 is turned off, and the fourth MOS transistor N2 is turned on, so that the gate voltage of the first MOS transistor P1 is at a low level, thereby making the The first MOS transistor P1 is turned on, and at this time, the output voltage value of the output terminal out is a low level.

In the above-mentioned circuit conversion circuit 10, the first MOS transistor P1 and the second MOS transistor P2 are both directly connected to the power supply voltage output terminal VDD, so the first MOS transistor P1 and the second MOS transistor P2 need to be high-voltage transistors, so that they can operate at a high voltage. normal working conditions.

Because the third MOS transistor N1 is directly connected to the first MOS transistor P1, and the fourth MOS transistor N2 is directly connected to the second MOS transistor P2, so that the third MOS transistor N1 and the fourth MOS transistor N2 also work under high pressure, so The third MOS transistor N1 and the fourth MOS transistor N2 should also be high-voltage transistors.

In a specific implementation, the thickness of the gate oxide layer inside the CMOS tube and the process conditions can be adjusted to make the CMOS tube a high-voltage CMOS tube. Under normal circumstances, the threshold voltage of high-voltage CMOS tubes is relatively high, and its typical value is about 1.0V. In severe cases, it can reach more than 1.0V.

The saturation current value of the CMOS tube is inversely proportional to the threshold voltage of the CMOS tube. Due to the high threshold voltage of the high-voltage CMOS tube, during the level conversion process, the current flowing through the high-voltage CMOS tube is very small, resulting in level conversion. The circuit 10 needs a long time to charge the output terminal so that the output terminal out can reach the required conversion voltage, that is, the switching time of the level conversion circuit is long, so the level conversion speed is slow.

In order to solve the above problem, an embodiment of the present invention provides a level conversion circuit, wherein an isolation subcircuit is provided in the level conversion circuit, one end of the isolation subcircuit is connected to the input subcircuit, and the other end is connected to the output subcircuit , and the isolator sub-circuit can be connected to the input sub-circuit and the output sub-circuit, so that the isolator sub-circuit can isolate the high voltage output by the power supply voltage output terminal, and the input sub-circuit can work at a lower voltage, thus, For the NMOS transistor in the input sub-circuit, an NMOS transistor whose threshold voltage is lower than the threshold voltage of the PMOS transistor in the output sub-circuit can be selected. The decrease of the threshold voltage of the NMOS tube in the input sub-circuit can increase the current flowing through the NMOS tube in the input sub-circuit, thereby increasing the current output by the output sub-circuit, improving the speed of charging the input terminal, and finally Increased level shifting speed.

In order to make the above objects, features and beneficial effects of the present invention more clearly understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Referring to FIG. 2 , an embodiment of the present invention provides a level conversion circuit 20 for converting a voltage value of an input logic signal into a required voltage value. In the embodiment of the present invention, the voltage value of the input logic signal is smaller than the converted voltage value, that is, the level conversion circuit 20 is used to convert the low voltage logic signal into a high voltage logic signal.

Specifically, the level conversion circuit 20 may include: an input sub-circuit 21 , an isolation sub-circuit 22 and an output sub-circuit 23 .

The input sub-circuit 21 may include: a first NMOS transistor K1 , a second NMOS transistor K2 , and an inverter 211 . The output sub-circuit 23 may include: a first PMOS transistor M1 and a second PMOS transistor M2.

The gate of the first NMOS transistor K1 is connected to the logic signal output terminal IN and the input terminal C of the inverter 211; the output terminal D of the inverter 211 is connected to the gate of the second NMOS transistor K2 connect. The source of the first NMOS transistor K1 and the second NMOS transistor K2 is grounded, and the drain is connected to the isolator circuit 22 . The isolator circuit 22 is connected to the drains of the first PMOS transistor M1 and the second PMOS transistor M2. The gate of the first PMOS transistor M1 is connected to the drain of the second PMOS transistor M2, and the gate of the second PMOS transistor M2 is connected to the drain of the first PMOS transistor M1. The sources of the first PMOS transistor M1 and the second PMOS transistor M2 are connected to the power supply voltage output terminal VDD.

The threshold voltages of the first NMOS transistor K1 and the second NMOS transistor K2 are lower than the threshold voltages of the first PMOS transistor M1 and the second PMOS transistor M2. The isolation sub-circuit 22 is used to connect the input sub-circuit 21 and the output sub-circuit 23, and provide a suitable drain voltage for the first NMOS transistor K1 and the second NMOS transistor K2.

Since the isolation sub-circuit 22 can communicate with the input sub-circuit 21 and the output sub-circuit 23, and can provide a suitable drain voltage for the first NMOS transistor K1 and the second NMOS transistor K2, the level conversion circuit 20 can be Level shifting is possible. The threshold voltages of the first NMOS transistor K1 and the second NMOS transistor K2 are smaller than the threshold voltages of the first PMOS transistor M1 and the second PMOS transistor M2, so the current value flowing through the input sub-circuit 21 can be made larger, Therefore, the output terminal out can be quickly charged, so that the voltage value of the output terminal out can reach the required conversion voltage as soon as possible, thereby effectively improving the level conversion speed.

In a specific implementation, the voltage value output by the power supply voltage output terminal VDD is greater than 1.2V, and may be 3.3V, 5V, or 10V, etc., which may be set according to the actual converted voltage value to be obtained.

In a specific implementation, the threshold voltages of the first NMOS transistor K1 and the second NMOS transistor K2 are lower than the threshold voltages of the first PMOS transistor M1 and the second PMOS transistor M2.

The threshold voltage of the first PMOS transistor M1 and the threshold voltage of the second PMOS transistor M2 may be the same or different. The threshold voltage of the first NMOS transistor K1 and the threshold voltage of the second NMOS transistor K2 may be the same or different, but as long as they are smaller than the threshold voltage of the first PMOS transistor M1 and the threshold voltage of the second PMOS transistor M2 That's it.

Wherein, the threshold voltages of the first PMOS transistor M1 and the second PMOS transistor M2 are high-voltage CMOS transistors, and the typical value of the threshold voltages is about 1.0V, and may be greater than 1.0V. Correspondingly, the first NMOS transistor K1 and the second NMOS transistor K2 can be selected as low-voltage CMOS transistors, that is, MOS transistors that can work normally under a lower operating voltage, and the low voltage can be 0.8V or even lower. Typical values of the threshold voltages of the first NMOS transistor K1 and the second NMOS transistor K2 may be greater than or equal to 0.7V and less than or equal to 0.8V.

In a specific implementation, the thickness of the gate oxide layer in the MOS and the corresponding process conditions can be adjusted, so that the formed MOS transistor is a low-voltage CMOS transistor or a high-voltage CMOS transistor.

In specific implementation, the isolation sub-circuit 22 can be implemented by various circuit structures, which is not specifically limited, as long as the input sub-circuit 21 and the output sub-circuit 23 can be isolated from the operating voltages.

In an embodiment of the present invention, the isolation sub-circuit 22 may include: a third NMOS transistor K3 and a fourth NMOS transistor K4. in:

The gates of the third NMOS transistor K3 and the fourth NMOS transistor K4 are both connected to the power supply voltage output terminal VDD. The source of the third NMOS transistor K3 is connected to the drain of the first NMOS transistor K1. The source of the fourth NMOS transistor K4 is connected to the drain of the second NMOS transistor K2. The drain of the third NMOS transistor K3 is connected to the drain of the first PMOS transistor M1. The drain of the fourth NMOS transistor K4 is connected to the drain of the second PMOS transistor M2. The threshold voltages of the third NMOS transistor K3 and the fourth NMOS transistor K4 are lower than the threshold voltages of the first NMOS transistor K1 and the second NMOS transistor K2.

In the embodiment of the present invention, the threshold voltage of the third NMOS transistor K3 and the threshold voltage of the fourth NMOS transistor K4 may be the same or different, as long as they are smaller than the threshold voltage of the first NMOS transistor K1 and the threshold voltage of the second NMOS transistor K4 The threshold voltage of K2 is sufficient.

In a specific implementation, the third NMOS transistor K3 and the fourth NMOS transistor K4 may be intrinsic high-voltage CMOS transistors. Intrinsic high-voltage CMOS transistors can work normally under high voltage, but their threshold voltage is very small. The typical value of the threshold voltage is usually less than or equal to 0.2V and greater than or equal to 0V.

Since the threshold voltages of the third NMOS transistor K3 and the fourth NMOS transistor K4 are smaller than the threshold voltages of the first NMOS transistor K1 and the second NMOS transistor K2, the current flowing through the third NMOS transistor K3 and the fourth NMOS transistor K4 , which may be greater than the current flowing through the first NMOS transistor K1 and the second NMOS transistor K2. Therefore, after the logic signal is input to the input sub-circuit 21, it can completely flow to the output sub-circuit 23 through the isolation sub-circuit 22, thereby improving the level conversion speed.

When the voltage of the logic signal output by the logic signal output terminal IN is at a high level, the first NMOS transistor K1 is turned on, and the second NMOS transistor K2 is turned off. Since the third NMOS transistor K3 is always in an on state, the gate voltage of the second PMOS transistor M2 can be made to be at a low level, so that the second PMOS transistor M2 is turned on, and the output voltage value of the output terminal out is close to the power supply voltage output terminal. The voltage output by VDD is a high level.

When the voltage of the logic signal output by the logic signal output terminal IN is at a low level, the first NMOS transistor K1 is turned off, and the second NMOS transistor K2 is turned on. Since the fourth NMOS transistor K4 is always in an on state, the output voltage value of the output terminal out can be made to be a low level.

In another embodiment of the present invention, referring to FIG. 3 , the level conversion circuit 20 may further include: a fifth NMOS transistor K5. The fifth NMOS transistor K5 is connected in parallel with the first PMOS transistor M1 , and the gate of the fifth NMOS transistor K5 is connected to the output terminal D of the inverter 211 .

When the voltage of the logic signal output from the logic signal output terminal IN is at a low level, the fifth NMOS transistor K5 is turned on. At the same time, the second NMOS transistor K2 is turned on, so that the output voltage value of the output terminal out is a low level. At this time, the first PMOS transistor M1 is turned on, and the first PMOS transistor M1 and the fifth NMOS transistor K5 jointly charge the output end out, so that the output end out reaches the required conversion voltage faster.

In another embodiment of the present invention, referring to FIG. 3 , the level conversion circuit 20 may further include: a sixth NMOS transistor K6. The sixth NMOS transistor K6 is connected in parallel with the second PMOS transistor M2 , and the gate of the sixth NMOS transistor K6 is connected to the logic signal output terminal IN, that is, connected to the input terminal C of the inverter 211 .

When the voltage of the logic signal output from the logic signal output terminal IN is at a high level, the sixth NMOS transistor K6 is turned on. At the same time, the first NMOS transistor K1 is turned on, so that the second PMOS transistor M2 is turned on. At this time, the output voltage value of the output terminal out is a high level. The second PMOS transistor M2 and the sixth NMOS transistor K6 are made to jointly charge the output end out, so that the output end out reaches the required conversion voltage faster.

It can be understood that, in the specific implementation, only the fifth NMOS transistor K5 may be provided, or only the sixth NMOS transistor K6 may be provided, and the fifth NMOS transistor K5 and the sixth NMOS transistor K6 may be provided at the same time, which is not limited here.

In a specific implementation, the fifth NMOS transistor K5 and the sixth NMOS transistor K6 are also high-voltage CMOS transistors, that is, MOS transistors that can work normally under high voltage, and their typical threshold voltage is greater than or equal to 1.0V.

In a specific implementation, the inverter 211 may be composed of CMOS transistors, and the CMOS transistors constituting the inverter 211 may be low-voltage CMOS transistors. The typical value of the threshold voltage is greater than or equal to 0.7V and less than or equal to 0.8 V.

FIG. 4 is a schematic diagram showing the comparison between the simulation results of the level conversion speed of the level conversion circuit 10 in FIG. 1 and the level conversion speed of the level conversion circuit 20 in the embodiment of the present invention.

As shown in FIG. 4 , the curve 41 represents the voltage variation curve of the input logic signal. The curve 42 represents the voltage variation curve of the signal output from the output terminal out of the level conversion circuit 20 . The curve 43 represents the voltage variation curve of the signal output from the output terminal out of the level conversion circuit 10 .

At time t1, as indicated by point a, the voltage value of the input logic signal reaches 0.6V, which is about half of the high level (1.2V). At time t2, as indicated by point b, the voltage value of the signal output from the output terminal out of the level conversion circuit 20 reaches 0.9V, which is about half of the high level (1.8V). At time t3, as indicated by point c, the voltage value of the signal output from the output terminal out of the level conversion circuit 20 reaches 0.9V, which is about half of the high level (1.8V).

( t2 - t1 ) represents the level inversion duration of the level conversion circuit 20 , and ( t3 - t1 ) represents the level inversion duration of the level conversion circuit 10 . Obviously, the level inversion duration required by the level conversion circuit 20 in the embodiment of the present invention is shorter than the level inversion duration required by the level conversion circuit 10 .

As can be seen from the above, in the level conversion circuit 20 in the embodiment of the present invention, due to the setting of the isolation sub-circuit 22, the CMOS transistor in the input sub-circuit 21 can use a low-voltage CMOS transistor, thereby increasing the flow rate through the input sub-circuit The current of the CMOS tube in 21 can effectively improve the level speed.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be based on the scope defined by the claims.

Claims (10)

1. A level conversion circuit, comprising: an input sub-circuit, an isolation sub-circuit and an output sub-circuit; wherein, the input sub-circuit comprises: a first NMOS tube, a second NMOS tube, and an inverter; The output sub-circuit includes: a first PMOS tube and a second PMOS tube; The gate of the first NMOS transistor is connected to the logic signal output terminal and the input terminal of the inverter; the output terminal of the inverter is connected to the gate of the second NMOS transistor; the first NMOS transistor tube and the second NMOS tube, the source is grounded, and the drain is connected to the isolator circuit; the isolator circuit is connected to the drain of the first PMOS tube and the second PMOS tube; the first PMOS tube The gate is connected to the drain of the second PMOS tube, and the gate of the second PMOS tube is connected to the drain of the first PMOS tube; the sources of the first PMOS tube and the second PMOS tube are connected to Power supply voltage output connection; The threshold voltages of the first NMOS transistor and the second NMOS transistor are smaller than the threshold voltages of the first PMOS transistor and the second PMOS transistor; the isolation sub-circuit is used to connect the input sub-circuit and the output sub-circuit, And provide a suitable drain voltage for the first NMOS transistor and the second NMOS transistor. 2. The level conversion circuit of claim 1, wherein the isolation sub-circuit comprises: a third NMOS transistor and a fourth NMOS transistor; wherein: The gates of the third NMOS transistor and the fourth NMOS transistor are both connected to the power supply voltage output terminal; the source of the third NMOS transistor is connected to the drain of the first NMOS transistor; the fourth NMOS transistor The source of the NMOS transistor is connected to the drain of the second NMOS transistor; the drain of the third NMOS transistor is connected to the drain of the first PMOS transistor; the drain of the fourth NMOS transistor is connected to the drain of the second NMOS transistor The drain connection of the PMOS tube; The threshold voltages of the third NMOS transistor and the fourth NMOS transistor are lower than the threshold voltages of the first NMOS transistor and the second NMOS transistor. 3 . The level conversion circuit of claim 2 , wherein the typical values of the threshold voltages of the third NMOS transistor and the fourth NMOS transistor are greater than or equal to 0V and less than or equal to 0.2V. 4 . 4 . The level conversion circuit of claim 1 , further comprising: a fifth NMOS transistor, the fifth NMOS transistor is connected in parallel with the first PMOS transistor, and the gate of the fifth NMOS transistor is connected in parallel. 5 . connected to the output of the inverter. 5 . The level conversion circuit according to claim 4 , further comprising: a sixth NMOS transistor, the sixth NMOS transistor is connected in parallel with the second PMOS transistor, and the gate of the sixth NMOS transistor is connected in parallel. 6 . connected with the logic signal output terminal. 6 . The level conversion circuit of claim 5 , wherein the typical values of the threshold voltages of the fifth NMOS transistor and the sixth NMOS transistor are greater than or equal to 1V. 7 . 7 . The level conversion circuit of claim 1 , wherein the typical values of the threshold voltages of the first PMOS transistor and the second PMOS transistor are greater than or equal to 1V. 8 . 8 . The level conversion circuit of claim 1 , wherein the typical values of the threshold voltages of the first NMOS transistor and the second NMOS transistor are greater than or equal to 0.7V and less than or equal to 0.8V. 9 . 9 . The level conversion circuit of claim 1 , wherein the inverter is composed of CMOS transistors. 10 . 10 . The level conversion circuit according to claim 9 , wherein a typical value of the threshold voltage of the CMOS transistor in the inverter is greater than or equal to 0.7V and less than or equal to 0.8V. 11 .

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