CN114374814B

CN114374814B - Detection circuit and wake-up method

Info

Publication number: CN114374814B
Application number: CN202011104048.9A
Authority: CN
Inventors: 詹钧杰; 吴旻安; 张家豪; 吕建勳
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-10-15
Filing date: 2020-10-15
Publication date: 2025-10-24
Anticipated expiration: 2040-10-15
Also published as: CN114374814A

Abstract

The present disclosure relates to a detection circuit and a wake-up method. The present invention discloses a detection circuit and a wake-up method. The detection circuit is applicable to a high-definition multimedia interface (HDMI) receiver after entering a power saving mode in a fixed rate link (FRL) mode, so as to detect whether the HDMI transmitter starts to transmit image packets through the FRL link, and the detection circuit includes a signal detection circuit and an FRL packet judgment circuit. The signal detection circuit detects whether there is a signal on the FRL link. If there is, it indicates that there is an FRL packet on the FRL link. Then, based on the variable value characteristics of the image packet and/or the fixed value characteristics of the gap packet, the FRL packet judgment circuit determines whether the FRL packet is an image packet. If so, the FRL packet judgment circuit wakes up the HDMI receiver from the power saving mode to parse the image packet and display the image.

Description

Detection circuit and wake-up method

Technical Field

The present invention relates to a detection circuit and a wake-up method, and more particularly, to a detection circuit and a wake-up method suitable for use in a high-definition multimedia interface (High Definition Multimedia Interface, HDMI) receiver after entering a power saving mode in a Fixed Rate Link (FRL) mode.

Background

The FRL mode is a new transmission mode defined by the HDMI 2.1 specification, and the HDMI transmitter and HDMI receiver (or Source and Sink) must perform link training (LINK TRAINING) to confirm the maximum transmission bandwidth between each other before entering the FRL mode. After training via the link, the HDMI transmitter and HDMI receiver may be in the state of the FRL link. Next, the HDMI transmitter transmits a gap packet (GAP PACKETS) before transmitting the video packet so that the HDMI transmitter can prepare the video data during this time. However, the length of time for transmitting the gap packet depends on the time for which the HDMI transmitter prepares the video data, and in order not to miss the video data, the HDMI receiver may remain in the FRL link state and wait for the HDMI transmitter to transmit the video packet.

In addition, since the gap packet does not have image data, when the HDMI receiver has no image to display, in order to avoid consuming unnecessary power consumption, the HDMI receiver may also self-define that after no image packet is received for a period of time, the FRL link is disconnected and enters into the power saving mode, which causes the following problems. 1. If the HDMI transmitter prepares the video data for a long time and the HDMI receiver is in the power saving mode, the HDMI receiver cannot distinguish the video packet transmitted by the HDMI transmitter because the FRL link is disconnected, so that the HDMI receiver will miss the video data and cannot display the video.

The HDMI receiver also stops reporting status to the HDMI transmitter in power saving mode, such as SCDC (Status and Control DATA CHANNEL) and EDID (ENHANCED DISPLAY Identification Data) updates, and the Hot Plug Detect (HPD) pin is not pulled low because the cable is still connected, so that the HDMI transmitter does not know that the HDMI receiver has disconnected the FRL link. Therefore, the HDMI transmitter will transmit video packets without re-performing link training to restart the FRL link. Therefore, unless the cable is plugged in and plugged out again, the HDMI receiver will not always receive the image packet and display the image again because the receiving interface circuit has been restored to the original state (i.e. the set parameters are lost). In order to overcome the above-mentioned problems, the HDMI receiver needs a mechanism for automatically waking up and displaying the video by detecting whether the HDMI transmitter starts transmitting the video packet after entering the power saving mode.

Disclosure of Invention

In view of the above, the embodiment of the invention provides a detection circuit, which is suitable for an HDMI receiver after entering a power saving mode in an FRL mode to detect whether an HDMI transmitter starts transmitting an image packet through an FRL link, and the detection circuit includes a signal detection circuit and an FRL packet determination circuit. The signal detection circuit detects whether a signal is present on the FRL link. If so, it indicates that there is FRL packet on the FRL link. Then, the FRL packet judgment circuit judges whether the FRL packet is an image packet according to the variable value characteristic of the image packet and/or the constant value characteristic of the gap packet. If not, the HDMI receiver remains in the power saving mode. If so, the FRL packet judgment circuit wakes up the HDMI receiver from the power saving mode to analyze the image packet and display the image.

In addition, the embodiment of the invention provides a wake-up method which is suitable for the HDMI receiver after entering the power saving mode in the FRL mode. After entering the power saving mode, the HDMI receiver turns off the main circuit responsible for analyzing the image packet and displaying the image, and the wake-up method comprises the following steps. First, a signal detection circuit is used to detect whether a signal exists on the FRL link. If so, it indicates that there is FRL packet on the FRL link. Then, the FRL packet judging circuit is utilized to judge whether the FRL packet is an image packet according to the variable value characteristic of the image packet and/or the constant value characteristic of the gap packet. If not, the step of detecting whether a signal exists on the FRL link by the signal detection circuit is returned. If yes, the HDMI receiver is awakened from the power saving mode by using the FRL packet judging circuit, so that the main circuit is started to analyze the image packet and display the image.

For a further understanding of the nature and the technical aspects of the present invention, reference should be made to the following detailed description of the invention and to the accompanying drawings, which are provided for purposes of reference only and are not intended to limit the invention.

Drawings

FIG. 1 is a block diagram of a detection circuit according to an embodiment of the present invention.

Fig. 2 is a circuit diagram of a signal detection circuit in the detection circuit of fig. 1.

FIG. 3 is a schematic diagram showing the FRL transmission rate determining circuit in the detecting circuit of FIG. 1, which determines the transmission rate according to the transition density (Transition Density) of the signal in a time interval.

FIG. 4 is a schematic diagram of the character difference between the gap packet and the image packet.

Fig. 5 is a flowchart illustrating steps of a wake-up method according to an embodiment of the present invention.

Detailed Description

The following embodiments of the present invention are described in terms of specific examples, and those skilled in the art will appreciate the advantages and effects of the present invention from the disclosure provided herein. The invention is capable of other and different embodiments and its several details are capable of modifications and various other uses and applications, all of which are obvious from the description, without departing from the spirit of the invention. The drawings of the present invention are merely schematic illustrations, and are not intended to be drawn to actual dimensions. The following embodiments will further illustrate the related art content of the present invention in detail, but the content provided is not intended to limit the scope of the present invention.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements or signals, these elements or signals should not be limited by these terms. These terms are used primarily to distinguish one element from another element or signal from another signal. In addition, the term "or" as used herein shall be taken to include any one or a combination of more of the associated listed items as the case may be.

It should be noted that the specific condition for the HDMI receiver to enter the power saving mode in the FRL mode is not limited by the present invention. For example, when the HDMI transmitter prepares the video data for a long time, the HDMI receiver may enter a power saving mode, and referring to fig. 1, fig. 1 is a block diagram of a detection circuit according to an embodiment of the present invention. The detection circuit 12 is adapted to the HDMI receiver 1 after entering the power saving mode in the FRL mode to detect whether the HDMI transmitter 2 starts transmitting video packets through the FRL link 3 (i.e. transmission channel), and the detection circuit 12 includes a signal detection circuit 120, an FRL transmission rate determination circuit 122 and an FRL packet determination circuit 124.

The signal detection circuit 120, the FRL transmission rate determination circuit 122 and the FRL packet determination circuit 124 may be implemented by pure hardware or by hardware in combination with firmware or software. In addition, the signal detecting circuit 120, the FRL transmission rate determining circuit 122 and the FRL packet determining circuit 124 may be integrated or separately provided. In summary, the invention is not limited to the specific implementation of the detection circuit 12. In this embodiment, the signal detection circuit 120 detects whether a signal is present on the FRL link 3. If so, it indicates that there is an FRL packet on FRL link 3.

Next, the FRL transmission rate determination circuit 122 may determine the transmission rate on the FRL link 3 according to the transition density of the aforementioned signal in a time interval. Since the receiving interface circuit (not shown in fig. 1) of the HDMI receiver 1 also stops receiving signals and returns to the original state in the power saving mode, in order to correctly receive and parse signals on the FRL link 3, the HDMI receiver 1 further has to reset parameters of the receiving interface circuit according to the transmission rate determined by the FRL transmission rate determining circuit 122, so as to successfully convert signals on the FRL link 3 into signals that can be parsed by the HDMI receiver 1.

Then, the FRL packet determination circuit 124 may determine whether the FRL packet is an image packet according to the variable value characteristic of the image packet and/or the constant value characteristic of the gap packet. If not, the HDMI transmitter 2 is still preparing video data, so the HDMI receiver 1 is maintained in the power saving mode. If so, the HDMI transmitter 2 starts transmitting the video packet through the FRL link 3, so the FRL packet judgment circuit 124 wakes up the HDMI receiver 1 from the power saving mode to parse the video packet and display the video.

Specifically, the signal detection circuit 120 may detect whether a signal is present on the FRL link 3 at intervals. If so, it indicates that there is a possibility of image packets on FRL link 3. If not, the HDMI receiver 1 remains in the power saving mode and waits for the next detection by the signal detection circuit 120. In addition, since HDMI is one of high-speed differential signals, the signal detection circuit 120 can determine whether a signal exists on the FRL link 3 by determining whether the magnitude of the differential signal input from the FRL link 3 exceeds a voltage range between an upper limit voltage +vth and a lower limit voltage-Vth.

Referring to fig. 2 together, fig. 2 is a circuit diagram of the signal detection circuit 120 of fig. 1. As shown in fig. 2, the signal detection circuit 120 may include a comparator 1201. The first non-inverting input terminal and the first inverting input terminal of the comparator 1201 receive the differential signal input by the FRL link 3, and the second non-inverting input terminal and the second inverting input terminal of the comparator 1201 receive the upper limit voltage +vth and the lower limit voltage-Vth, respectively, so that the comparator 1201 can determine that a signal exists on the FRL link 3 when the magnitude of the differential signal is higher than the upper limit voltage +vth or lower than the lower limit voltage-Vth. In addition, the transmission rate on the FRL link 3 may include 3Gbps to 12Gbps, so the HDMI receiver 1 must use the FRL transmission rate determination circuit 122 to distinguish the transmission rate on the FRL link 3 in order to set the reception interface circuit of the HDMI receiver 1 according to the transmission rate to receive data.

Referring to fig. 3 together, fig. 3 is a schematic diagram illustrating the FRL transmission rate determining circuit 122 of fig. 1 for determining the transmission rate according to the transition density of the signal in a time interval T. It should be appreciated that the FRL packet is encoded in 16b/18b, which converts 16bits to 18 bits by look-up Table (Lookup Table), and the converted 18 bits will have direct current Balance (DC Balance) characteristics, i.e., the number of 0s and 1 s is the same. Therefore, according to such a coding scheme, the present embodiment can infer that the signal with a higher transmission rate has a higher transition density in the same time interval T.

For example, in the same time interval T, the number of potential transitions of a signal employing 6Gbps may be 2 times that of a signal employing 3 Gbps. Therefore, if the FRL transmission rate determination circuit 122 knows that the number of potential transitions of the signal employing 3Gbps is 12 in the same time period T, then the calculated number of potential transitions of 24 indicates that the transmission rate on the FRL link 3 is 6Gbps. In summary, the above-mentioned number of potential transitions is merely an example, and is not intended to limit the present invention. In addition, referring to fig. 4, fig. 4 is a schematic diagram of the character difference between the gap packet and the image packet.

For convenience of description, fig. 4 shows the scrambler reset (Scrambler Reset), GAP, image, and forward error correction (Forward Error Correction, FEC) check characters with the symbols "SR", "GAP", "Video", and "Parity", respectively, wherein the initial superblock (Start Super Block) Character and the scrambler reset Character are Comma characters (Comma characters) that can be used to achieve Character alignment (CHARACTER ALIGNMENT), and the initial superblock Character is denoted herein by "SSB", but fig. 4 only uses Comma characters as "SR" as an example. According to the HDMI 2.1 specification, the GAP packet is composed of three characters of "SR/SSB", "GAP" and "Parity", and besides the first two characters are constant, the check character calculated by FEC for the GAP character is also constant. In addition, after the break-up and 16b/18b encoding, the three characters of the gap packet will be converted into constant values for the fixed cycle. In contrast, the image character in the image packet will be a variable value according to the image content, and the check character calculated by the FEC for the image character will also be a variable value, and will be a variable value after being scattered and encoded by 16b/18 b. Therefore, by distinguishing these characteristics, the FRL packet determination circuit 124 can determine whether it is an image packet without parsing out the contents of the FRL packet.

For example, the FRL packet judgment circuit 124 may identify whether the plurality of characters in the current FRL packet are a plurality of variations. When these characters are not variable, the FRL packet determination circuit 124 determines that the current FRL packet is not an image packet, so that the HDMI receiver 1 is maintained in the power saving mode. In addition, when the characters are variable values, the FRL packet determination circuit 124 may determine that the current FRL packet is an image packet, so the FRL packet determination circuit 124 wakes up the HDMI receiver 1 to display an image. Alternatively, the FRL packet determination circuit 124 may identify whether the plurality of characters in the FRL packet are constant values for a fixed cycle. When these characters are fixed values of the fixed cycle, the FRL packet determination circuit 124 may determine that the current FRL packet is not an image packet but a gap packet, so that the HDMI receiver 1 is maintained in the power saving mode. In addition, when the characters are not fixed, the FRL packet determination circuit 124 may determine that the current FRL packet is an image packet, so the FRL packet determination circuit 124 wakes up the HDMI receiver 1 to display an image.

Similarly, the FRL packet determination circuit 124 may identify whether the plurality of characters in the current FRL packet are a plurality of variable values or a plurality of constant values for a fixed cycle. When these characters are fixed values of the fixed cycle, the FRL packet determination circuit 124 may determine that the current FRL packet is not an image packet but a gap packet, so that the HDMI receiver 1 is maintained in the power saving mode. In addition, when the characters are variable values, the FRL packet determination circuit 124 may determine that the current FRL packet is an image packet, so the FRL packet determination circuit 124 wakes up the HDMI receiver 1 to display an image. In summary, the present invention is not limited to the implementation manner of determining whether the FRL packet is an image packet according to the variable value characteristic of the image packet and/or the constant value characteristic of the gap packet by the FRL packet determining circuit 124, and one having ordinary skill in the art should design according to the actual requirement or application. In addition, since the identification method only needs a simple value checking circuit, the area and cost of the FRL packet judgment circuit 124 can be greatly reduced, and the power consumption of the detection circuit 12 for detecting whether the HDMI transmitter 2 starts transmitting the video packet through the FRL link 3 in the power saving mode can be reduced.

However, the power consumption of the main circuit 10 of the HDMI receiver 1 for parsing the video packet and displaying the video can be as high as several hundred milliwatts, but the power consumption is only several tens of milliwatts in the normal power saving mode, so after entering the power saving mode, the HDMI receiver 1 turns off the main circuit 10 to save power consumption. In addition, in order to detect whether the HDMI transmitter 2 starts transmitting the video packet without consuming a lot of Power consumption in the Power saving mode, the present invention further can separate the Power Domain (Power Domain) D1 of the detection circuit 12 from the Power Domain D2 of the main circuit 10, so that after entering the Power saving mode, the HDMI receiver 1 turns off the Power Domain D2 of the main circuit 10 to save Power consumption, and turns on only the Power Domain D1 of the detection circuit 12 to detect whether the HDMI transmitter 2 starts transmitting the video packet through the FRL link 3.

Finally, referring to fig. 5, fig. 5 is a flowchart illustrating steps of a wake-up method according to an embodiment of the invention. Since the detailed process flows are as described in the previous embodiments, only the summary is provided herein and no redundancy is added. As shown in fig. 5, in step S510 after entering the power saving mode, the HDMI receiver 1 turns off the main circuit 10 responsible for parsing the video packet and displaying the video to save power, and in step S520, the signal detecting circuit 120 detects whether a signal is present on the FRL link 3. If not, return to step S520. If so, it indicates that there is an FRL packet on the FRL link 3, so the HDMI receiver 1 will execute step S530 to determine the transmission rate on the FRL link 3 according to the transition density of the above signal in a time interval T by the FRL transmission rate determination circuit 122. In addition, the HDMI receiver 1 further has to reset the parameters of the receiving interface circuit according to the transmission rate determined by the FRL transmission rate determining circuit 122 to successfully convert the signal on the FRL link 3 into a signal resolvable by the HDMI receiver 1.

As described above, since the signal detection circuit 120 can detect whether the signal on the FRL link 3 exists at intervals, the HDMI receiver 1 can wait for the next detection of the signal detection circuit 120 in the return step S520. Next, in step S540, the FRL packet determining circuit 124 determines whether the FRL packet is an image packet according to the variable value characteristic of the image packet and/or the constant value characteristic of the gap packet. If not, it means that the HDMI transmitter 2 is still preparing video data, so the HDMI receiver 1 can return to step S520 to wait for the next detection of the signal detection circuit 120. If yes, the HDMI transmitter 2 starts transmitting the video packet through the FRL link 3, so the HDMI receiver 1 may execute step S550, and wake up the HDMI receiver 1 from the power saving mode by using the FRL packet judgment circuit 124, so that the main circuit 10 is turned on to parse the video packet and display the video.

Incidentally, since the present invention is not limited to the specific condition that the HDMI receiver 1 enters the power saving mode in the FRL mode, and the FRL packet judgment circuit 124 can also identify the gap packet according to the constant values of the constant cycles of the characters in the current FRL packet, other embodiments can further utilize the detection circuit 12 to identify the received gap packet or the image packet after the link training. When the received gap packet is identified, the HDMI receiver 1 can be put into a power saving mode, and when the received image packet is identified again, the HDMI receiver 1 leaves the power saving mode, i.e. the HDMI receiver 1 is awakened to parse the image packet and display the image. Since the details of the detection circuit 12 are as described above, further description is omitted here.

In summary, the embodiment of the invention provides a detection circuit and a wake-up method, which are suitable for an HDMI receiver after entering a power saving mode in an FRL mode, to automatically wake-up the HDMI receiver by detecting whether the HDMI transmitter starts transmitting an image packet. The detection circuit and the wake-up method are not too complex, so that not only the circuit area and the cost can be reduced, but also the power consumption can be saved so as not to lose the aim of entering the power-saving mode of the HDMI receiver.

The above disclosure is provided as a preferred embodiment of the present invention and is not intended to limit the scope of the present invention, so that all equivalent technical changes made by the specification and drawings of the present invention are included in the scope of the present invention.

[ Symbolic description ]

HDMI receiver

10 Main circuit

12 Detection circuit

120 Signal detection circuit

1201 Comparator

+Vth, upper limit voltage

Vth lower limit voltage

122 FRL transmission rate judging circuit

FRL packet judgment circuit

D1, D2 Power supply region

HDMI transmitter

3 FRL Link

T is time interval

SR scrambling reset character

GAP GAP character

Video: image character

Party-check character for Forward error correction

S510-S550 flow steps

Claims

1. A detection circuit, adapted for use in a high-definition multimedia interface (HDMI) receiver that enters a power-saving mode in a fixed-rate link (FRL) mode, to detect whether an HDMI transmitter has started transmitting image packets via the FRL link. The detection circuit comprises:

a signal detection circuit for detecting whether a signal exists on the FRL link, and if so, indicating that an FRL packet exists on the FRL link; and

an FRL packet determination circuit, which determines whether the FRL packet is the video packet based on the variable value characteristic of the video packet and/or the constant value characteristic of the interstitial packet; if not, the HDMI receiver remains in the power saving mode; and

If so, the FRL packet determination circuit wakes up the HDMI receiver from the power saving mode to parse the image packet and display the image.

2. The detection circuit according to claim 1, further comprising:

An FRL transmission rate determination circuit determines the transmission rate of the FRL link according to the transition density of the signal within a time interval.

3. The detection circuit according to claim 2 , wherein the HDMI receiver must reset parameters of its receiving interface circuit according to the transmission rate determined by the FRL transmission rate determination circuit so as to successfully convert the signal on the FRL link into a signal that can be interpreted by the HDMI receiver.

4. The detection circuit according to claim 1 , wherein the signal detection circuit detects whether the signal exists on the FRL link at regular intervals; if the signal exists, it indicates that there is a possibility that the image packet exists on the FRL link; if not, the HDMI receiver remains in the power saving mode and waits for the next detection by the signal detection circuit.

5. The detection circuit of claim 1 , wherein the signal detection circuit determines whether the signal exists on the FRL link by judging whether the magnitude of the differential signal input from the FRL link exceeds a voltage range between an upper limit voltage and a lower limit voltage.

6. The detection circuit according to claim 5, wherein the signal detection circuit comprises:

A comparator, wherein the first non-inverting input terminal and the first inverting input terminal of the comparator receive the differential signal input by the FRL link, and the second non-inverting input terminal and the second inverting input terminal of the comparator receive the upper limit voltage and the lower limit voltage respectively, so that when the magnitude of the differential signal is higher than the upper limit voltage or lower than the lower limit voltage, the comparator determines that the signal exists on the FRL link.

7. The detection circuit according to claim 1 , wherein the step of the FRL packet determination circuit determining whether the FRL packet is the image packet according to the variable value characteristic of the image packet and/or the constant value characteristic of the interstitial packet comprises:

Identify whether the multiple characters in the FRL packet are multiple variable values;

When the characters are not the variable values, the FRL packet determination circuit determines that the FRL packet is not the image packet; and

When the characters are the variable values, the FRL packet determination circuit determines that the FRL packet is the image packet.

8. The detection circuit according to claim 1 , wherein the step of the FRL packet determination circuit determining whether the FRL packet is the image packet according to the variable value characteristic of the image packet and/or the constant value characteristic of the interstitial packet comprises:

Identify whether the multiple characters in the FRL packet are multiple fixed values of a fixed cycle;

When the characters are the fixed values of the fixed cycle, the FRL packet determination circuit determines that the FRL packet is not the image packet; and

When the characters are not the fixed values of the fixed cycle, the FRL packet determination circuit determines that the FRL packet is the image packet.

9. The detection circuit according to claim 1 , wherein the step of the FRL packet determination circuit determining whether the FRL packet is the image packet according to the variable value characteristic of the image packet and/or the constant value characteristic of the interstitial packet comprises:

Identify whether the multiple characters in the FRL packet are multiple variable values or multiple fixed values of a fixed cycle;

10. A wake-up method for an HDMI receiver that has entered a power-saving mode in an FRL mode, wherein after entering the power-saving mode, the HDMI receiver shuts down a main circuit responsible for parsing image packets and displaying images, and the wake-up method comprises:

Using a signal detection circuit to detect whether there is a signal on the FRL link, if there is a signal, it means that there is an FRL packet on the FRL link;

Using an FRL packet determination circuit to determine whether the FRL packet is the image packet based on the variable value characteristics of the image packet and/or the constant value characteristics of the gap packet;

If not, returning to the step of using the signal detection circuit to detect whether the signal exists on the FRL link; and

If so, the FRL packet determination circuit is utilized to wake up the HDMI receiver from the power saving mode, so that the main circuit is turned on to parse the image packet and display the image.