CN110675799A - Driving device and transmission method of display data thereof - Google Patents

Abstract

The invention provides a driving device and a transmission method of display data thereof. The driving device is suitable for a display device. The driving device comprises a time schedule controller and a source electrode driving circuit. The time schedule controller is provided with a data transmission circuit for sequentially transmitting a plurality of serial display data. The time schedule controller determines whether to set the first power-saving flag according to a plurality of continuous changing states in the serial display data. The source driving circuit is provided with a data receiving circuit for sequentially receiving the serial display data. The data receiving circuit decodes each serial display data to generate output display data. When the first power-saving flag is set, the data transmission circuit and the data receiving circuit stop transmitting and receiving serial display data.

Description

Driving device and transmission method of display data thereof

technical field

The present invention relates to a driving device and a method for transmitting display data thereof, in particular to a driving device and a method for transmitting display data which can reduce power consumption.

Background technique

With the popularization of electronic devices, it has become an important trend of current technology to provide a good human-machine interface through a display device. Under the requirements of energy saving and carbon reduction, how to provide a display device with high performance and energy saving effect has become an important issue in the field.

In the prior art, the display device can only save power by means of power down in a partial time interval during the display scanning process, and the power saving effect that can be produced is limited.

SUMMARY OF THE INVENTION

The present invention provides a driving device and a method for transmitting display data, which can reduce power consumption.

The drive device of the present invention is suitable for use in a display device. The driving device includes a timing controller and a source driving circuit. The timing controller has a data transmission circuit to transmit a plurality of serial display data in sequence. The timing controller determines whether to set the first power saving flag according to the changing states of a plurality of consecutive serial display data. The source driving circuit has a data receiving circuit to receive serial display data in sequence. The data receiving circuit also performs decoding for each serial display data to generate output display data. When it is detected that the first power saving flag is set, the data transmission circuit and the source driving circuit of the data receiving circuit stop transmitting and receiving serial display data.

The display data transmission method of the present invention includes: providing a data transmission circuit of a timing controller to transmit a plurality of serial display data in sequence, and determining whether to set the first state according to the changing state of a plurality of consecutive serial display data. Power flag; provides the data receiving circuit of the source drive circuit to receive serial display data in sequence, and performs decoding for each serial display data to generate output display data; when it is detected that the first power saving flag is set, The data transmission circuit and the source drive circuit of the data reception circuit stop transmitting and receiving serial display data.

Based on the above, the driving device of the present invention determines the state of change among a plurality of serial display data, and stops the decoding of serial display data according to the judgment result, or stops the receiving operation of serial display data, thereby reducing the required amount of time. power consumption.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, the following embodiments are given and described in detail with the accompanying drawings as follows.

Description of drawings

FIG. 1 shows a schematic diagram of a driving device according to an embodiment of the present invention;

FIG. 2 shows a schematic diagram of the content of serial display data according to an embodiment of the present invention;

3 shows a schematic diagram of a partial circuit of a timing controller according to an embodiment of the present invention;

FIG. 4 shows a schematic diagram of a data receiving circuit of a source driver according to an embodiment of the present invention;

5A shows a schematic diagram of an implementation manner of a data transmission circuit of a timing controller according to an embodiment of the present invention;

5B shows a schematic diagram of an implementation manner of a data receiving circuit of a source driver according to an embodiment of the present invention;

6 shows a schematic diagram of a signal transmitted by a data transmission circuit according to an embodiment of the present invention;

FIG. 7 shows a flowchart of a method for transmitting display data according to an embodiment of the present invention.

Description of reference numbers:

100: Drive

110, 300: Sequence controller

111, 510: Data transmission circuit

120: Source drive circuit

121, 400, 520: data receiving circuit

210～240: Data field

311～31A: Line buffer

320: Comparator

410, 522, 524: clock data recovery circuit

420: deserialization circuit

430: Shift temporary storage circuit

440: Latch circuit

521, 523: Equalizer

CK: clock signal

DS, DS1～DSA, DS1’, DS2’, DS3’: Serial display data

SOL: start signal

S710～S740: Transmission steps of display data

CMD: command signal

DATA, RDS: data signal

EOL: end signal

FG1: The first power saving flag

FG2: The second power saving flag

PD: Display data side by side

DOUT: output display data

TX1～TXA: Transmitter

DP1~DPA, DN1~DNA: Signal

RX1~RXA: Receiver

V1, V2: voltage value

RS: Power saving mode

VREF: reference voltage value

Detailed ways

Please refer to FIG. 1 , which is a schematic diagram of a driving device according to an embodiment of the present invention. The driving device 100 is suitable for a display device. The driving device 100 includes a timing controller 110 and a source driving circuit 120 . The timing controller 110 has a data transmission circuit 111 to transmit a plurality of serial display data DS in sequence. The source driving circuit 120 has a data receiving circuit 121 to sequentially receive the serial display data DS sent by the timing controller 110 .

In the embodiment of the present invention, the timing controller 110 may determine whether to set a first power saving flag and a second power saving flag according to the changing state of a plurality of consecutive serial display data DS. Specifically, the timing controller 110 may determine whether to set the power saving flag according to whether the data content of the multiple serial display data DS to be transmitted has changed. In detail, when the timing controller 110 determines that the data contents of consecutive M of the multiple serial display data DS to be transmitted are the same, the first power saving flag can be set, and when the timing controller 110 determines When the data contents of consecutive N pieces of the multiple serial display data DS to be transmitted are the same, the second power saving flag can be set. Wherein, N is an integer greater than 1, and the value of N can be determined according to the clock data recovery capability of the clock data recovery circuit in the source driving circuit 120 . In addition, M is an integer greater than N.

Take N equal to 2 and M equal to 4 as an example. The timing controller 110 may pre-store a plurality of serial display data in a plurality of line buffers. When the timing controller 110 determines that among the above-mentioned multiple serial display data, the data contents of the four consecutive serial display data DS to be transmitted are the same, the timing controller 110 can set the first power saving flag as The first logic level (eg, a logic high level) causes the driving device 100 to enter a power saving mode. In the power saving mode, the timing controller 110 can stop the data transmission operation of the serial display data DS of its data transmission circuit 111 , and the source driver 120 can stop the data receiving operation of the serial display data DS of its data receiving circuit 121 . On the other hand, after the driving device 100 enters the power saving mode, the timing controller 110 can continue to detect the changing state of the four serial display data DS to be continuously transmitted.

When judging that among the above-mentioned multiple serial display data, there are no four consecutive serial display data with the same data content, but there are still two serial serial display data with the same data content, the timing controller 110 can set the second serial display data. The power-saving flag is set to a first logic level (eg, a logic high level), and the first power-saving flag is set to a cleared state (a second logic level, eg, a logic low level). In this state, since the first serial display data to be continuously transmitted by the timing controller 110 has the same data content as the second serial display data, the driving device 100 can enter the data maintenance mode. In the data maintenance mode, the data receiving circuit 121 of the source driving circuit 120 does not need to decode the newly received second serial display data, and reduces the power consumption by stopping the decoding of the newly received second serial display data. consume.

On the other hand, after the driving device 100 enters the data maintaining mode, the timing controller 110 can continue to detect the changing state of the two serial display data DS continuously transmitted. If the timing controller 110 detects that the data contents of the two serial display data DS that are continuously transmitted are different, the timing controller 110 can clear the second power saving flag, so that the second power saving flag is at the second logic level (eg logic low level), and release the data retention mode to return to the normal mode. When it is detected that the second power saving flag is cleared, the source driving circuit 120 resumes decoding the newly received serial display data DS to maintain the correctness of the data.

It should be noted that the above-mentioned four serial display data DS continuously transmitted are not actually transmitted to the source driving circuit 120 in the power saving mode. The above-mentioned four serial display data DS continuously transmitted are temporarily stored in a plurality of line buffers in the timing controller 110 . The timing controller 110 can set or clear the first power saving flag by comparing the data content of the serial display data DS stored in the line buffer.

In addition, the timing controller 110 will preferentially determine whether to set the first power saving flag, and when the first power saving flag needs to be set, the timing controller 110 does not need to set the second power saving flag icon to set. Of course, in other embodiments of the present invention, the timing controller 110 may also set the second power saving flag under the condition of setting the first power saving flag.

In this embodiment of the present invention, the serial display data DS of each group may include display data of a corresponding display column. Please refer to FIG. 2 , which shows a schematic diagram of the content of the serial display data DS according to an embodiment of the present invention. The serial display data DS may have a plurality of data fields 210-240. The data field 210 records the start signal SOL for indicating the start point of a display column of data. The data field 220 records the command signal CMD, which is used to represent the command sent by the timing controller 110 . The data field 230 records the data signal DATA, and the data signal DATA is the display data corresponding to the display column. The data field 240 records the end signal EOL to indicate the end point of displaying column data. The above-mentioned second power saving flag can be located in the data field 220 as a type of the command signal CMD.

When the driving device 100 enters the power saving mode, the timing controller 110 can stop the data transmission operation of the serial display data DS of the data transmission circuit 111 , and the source driver 120 can stop the serial display data of the data receiving circuit 121 of the source driver 120 . Data reception action of DS.

Taking the data transmission circuit 111 to transmit the serial display data DS through a differential signal pair as an example, the data transmission circuit 111 can perform the serial display data DS through the first signal and the second signal which are differential signals with each other. transmission. When the driving device 100 enters the power saving mode, the timing controller 110 can make the voltage values of the first signal and the second signal sent by the data transmission circuit 111 be the same reference voltage value (for example, the reference ground voltage), And the circuit operation of the data transmission circuit 111 is stopped to save power consumption. On the other hand, when the data receiving circuit 121 of the source driver 120 receives the first signal and the second signal which are both reference voltage values, it can be known that the driving device 100 has entered the power saving mode, and the data receiving circuit 121 can be stopped action to further reduce power consumption. In addition, by keeping the voltage values of the first signal and the second signal constant and not performing state transitions, power consumption can also be effectively reduced.

It should be particularly noted that the first power saving flag and the second power saving flag in the present invention can be set separately. For example, when the data contents of consecutive P serial display data to be transmitted are the same, and P is greater than or equal to N and less than M, the timing controller 110 may set the second power saving flag. When the above-mentioned P is greater than or equal to M, the timing controller 110 may only set the first power saving flag. Alternatively, when the aforementioned P is greater than or equal to M, the timing controller 110 may simultaneously set the first power saving flag and the second power saving flag. Of course, when the above-mentioned P is less than N, the timing controller 110 can make both the first power saving flag and the second power saving flag be cleared.

It should be noted that more power can be saved based on the power saving mode corresponding to the first power saving flag. In the embodiment of the present invention, when P is greater than or equal to M, the timing controller 110 can also only target the first power saving It is enough to set the flag and make the driving device 100 enter the power saving mode, and it is not necessary to set the second power saving flag.

Please refer to FIG. 3 below. FIG. 3 is a schematic diagram of a part of a circuit of a timing controller according to an embodiment of the present invention. The timing controller 300 includes a plurality of line buffers 311 to 31A and a comparator 320 . The line buffers 311 - 31A are used for temporarily storing the serial display data DS1 - DSA transmitted previously. The line buffers 311 - 31A store the serial display data DS1 - DSA according to a first in first out (FIFO) mechanism.

The comparator 320 is coupled to the line buffers 311 ˜ 31A, and compares the serial display data DS1 ˜DSA stored in the line buffers 311 ˜ 31A. The first power saving flag FG1 and the second power saving flag FG2 are set or cleared accordingly.

Taking the aforementioned N setting as 2 as an example, the comparator 320 can compare the serial display data DS1 and DS2 temporarily stored in the line buffers 311 and 312 of the first two stages (to perform serial display data transmission operation), And when the data content of the serial display data DS2 and the serial display data DS1 are the same, the comparator 320 can set the power saving flag FG1 and make the driving device enter the data retention mode.

In the data hold mode, the source driving circuit does not decode the serial display data DS2 sent by the timing controller 300, thereby saving power. In the next sequence, the line buffers 311-31A receive the serial display data DS according to the FIFO mechanism, and make the line buffers 311-312 store the serial display data DS1' and DS2' respectively, wherein the serial display data DS1' and DS2' are stored in the line buffers 311-312 respectively DS1' may be equal to the serial display data DS2. The comparator 320 compares the serial display data DS1', DS2' stored in the line buffers 311-312, and clears the second power saving under the condition that the serial display data DS1', DS2' are different Flag FG2.

In addition, taking M as 3 as an example, when the comparator 320 compares the data contents of the serial display data DS1 to the serial display data DS3 are the same, the comparator 320 can set the first power saving flag FG1 , and put the drive into power saving mode. In the power saving mode, the timing controller 300 and the source driver circuit stop transmitting and receiving serial display data.

It should be noted that in the power saving mode, the FIFO mechanism of the line buffers 311 - 31A continues, and in the next timing sequence, the comparator 320 can display the new serial data DS1 in the line buffers 311 - 313 ', DS2' and DS3' are compared, and when the serial display data DS1', DS2' and DS3' are not identical, the first power saving flag FG1 is cleared, and the driving device returns to the normal mode.

In this embodiment, the hardware structure of the line buffers 311 - 31A may be line buffer circuits commonly used in the field of display devices. The comparator 320 can be a comparator circuit well known to those skilled in the art.

Please refer to FIG. 4 below. FIG. 4 shows a schematic diagram of a data receiving circuit of a source driver according to an embodiment of the present invention. The data receiving circuit 400 includes a clock data recovery circuit 410 , a deserialization circuit 420 , a shift buffer circuit 430 and a latch circuit 440 . A clock and data recovery (CDR) circuit 410 is coupled to the deserialization circuit 420 and receives the serial data signal DS. The clock data recovery circuit 410 is used for generating a corresponding clock signal CK according to the received serial data signal DS, and transmitting the clock signal CK and the data signal RDS generated according to the serial data signal DS to the deserializer circuit 420.

In this embodiment, the deserialization circuit 420 performs a serial-to-parallel operation (deserialization operation) on the data signal RDS according to the clock signal CK, and obtains the parallel display data PD. The deserialization circuit 420 is further coupled to the shift register 430 and causes the parallel display data PD to be stored in the shift register 430 . The latch circuit 440 is coupled to the shift register 430 for latching the parallel display data PD, and generating the output display data DOUT according to the parallel display data PD.

Please note here that the data receiving circuit 400 also receives the power saving flag FG1. When the power saving flag FG2 is set, the data receiving circuit 400 can stop the decoding (deserializing) operation of the deserialization circuit 420 according to the power saving flag FG2, and stop the shift register 430 and the latch The circuit of the locker circuit 440 operates to save power consumption. Furthermore, when the power saving flag FG1 is set, the data receiving circuit 400 can stop the operation of the clock data recovery circuit 410 according to the power saving flag FG1 to save more power.

Please refer to FIG. 5A below. FIG. 5A shows a schematic diagram of an implementation manner of a data transmission circuit of a timing controller according to an embodiment of the present invention. The data transmission circuit 510 includes a plurality of transmitters TX1 to TXA. The transmission buffers TX1 and TXA respectively transmit the signals DP1 and DN1 and the signals DPA and DNA. When the driving device is in the normal mode, the signals DP1 and DN1 are differential signals with each other, and the signals DPA and DNA are differential signals with each other.

On the other hand, the transmitters TX1-TXA can jointly receive the power-saving flag FG1, and when the power-saving flag FG1 is in the set state (indicating that the driving device is in the power-saving mode), the actions of the transmitters TX1-TXA can be is stopped and in an unpowered state. The transmitters TX1 to TXA make the voltage values of the signals DP1 and DN1 and the signals DPA and DNA to be the same reference voltage value respectively, so as to indicate that the driving device has entered the power saving mode.

By powering off the transmitters TX1 ˜TXA, and making the voltage values of the signals DP1 and DN1 and the signals DPA and DNA to be the same reference voltage value, the power can be effectively saved.

Please refer to FIG. 5B below. FIG. 5B shows a schematic diagram of an implementation manner of a data receiving circuit of a source driver according to an embodiment of the present invention. The data receiving circuit 520 includes a plurality of receivers RX1 to RXA. In addition, the receiver RX1 is coupled to the equalizer 521 and the clock data recovery circuit (CDR) 522 , and the receiver RXA is coupled to the equalizer 523 and the clock data recovery circuit (CDR) 524 . The clock data recovery circuits 522 and 524 can receive clock signals provided by a clock detection circuit (not shown). The equalizers 521 and 523 may be decision feedback equalizers (Decision Feedback Equalizer, DFE). The receiving buffer RX1 is used for receiving the signals DP1 and DN1, and the receiving buffer RXA is used for receiving the signals DPA and DNA. In this embodiment, the equalizers 521 and 523 and the clock data recovery circuit (CDR) 522 and 524 can be implemented by using circuits well known to those skilled in the art.

When the driving device is in a normal state, the signals DP1 and DN1 are differential signals with each other, and the signals DPA and DNA are also differential signals with each other. On the contrary, when the voltage value of at least one of the signals DP1, DN1, DPA, and DNA is equal to the reference voltage value, it means that the driving device is in the power saving mode, and the source driver can correspondingly close the circuit action of the receivers RX1 to RXA, to save power consumption.

Please refer to FIG. 6 . FIG. 6 is a schematic diagram of signals transmitted by a data transmission circuit according to an embodiment of the present invention. Taking the signal DP1 in the embodiment of FIG. 5B as an example, when the driving device is not in the power saving mode RS, the voltage value of the signal DP1 can transition between the voltage value V1 and the voltage value V2. On the contrary, in this state, the voltage value of the signal DN1 corresponding to the signal DP1 can be switched between the voltage value V2 and the voltage value V1 (when the voltage value of the signal DP1 is V1, the voltage value of the signal DN1 is V2; when the signal The voltage value of DP1 is V2, and the voltage value of signal DN1 is V1).

On the other hand, when the driving device is in the power saving mode RS, the voltage values of the signals DP1 and DN1 can also be set equal to the reference voltage value VREF. In this embodiment, the reference voltage value VREF can be smaller than the voltage value V1 and V2. For example, the reference voltage value VREF may be 0 volts. In other embodiments of the present invention, the reference voltage value VREF may not necessarily be smaller than the voltage values V1 and V2, nor may it be equal to 0 volts. The reference voltage value VREF may be any voltage value not equal to the voltage values V1 and V2.

Please refer to FIG. 7 . FIG. 7 shows a flowchart of a method for transmitting display data according to an embodiment of the present invention. In FIG. 7, in step S710, a data transmission circuit of the timing controller is provided to transmit a plurality of serial display data in sequence, and whether to set the first serial display data is determined according to the changing state of a plurality of serial display data. a power-saving flag and a second power-saving flag; in step S720, a data receiving circuit of the source driver circuit is provided to receive serial display data in sequence, and perform decoding for each serial display data to generate output display data; In step S730, the first power saving flag can be detected first. If it is detected that the first power saving flag is set, the data transmission circuit and the data receiving circuit stop transmitting and receiving serial display data; in step S740, if the first power saving flag is not set, the When it is detected that the second power saving flag is set, the source driving circuit stops decoding.

The implementation details of the above steps have been described in detail in the foregoing embodiments, and will not be repeated here.

To sum up, the present invention sets the power saving flag according to the changing state of the data content of a plurality of consecutive serial display data, and stops decoding performed for each serial display data according to the power saving flag. In this way, when the display data continues to not change, the drive device saves power for decoding that does not need to be performed, thereby effectively reducing waste of power. In the embodiment of the present invention, when the display data does not change for a longer time, the driving device can further turn off the data transmission operations of the data transmission circuit and the data reception circuit to further save power consumption.

Although the present invention has been disclosed above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be subject to what is defined in the claims.

Claims (26)

1. A driving device, suitable for a display device, is characterized in that, comprising: a timing controller having a data transmission circuit to transmit a plurality of serial display data in sequence, the timing controller determines whether to set a first power saving flag according to the changing state of a plurality of serial display data in the plurality of serial display data target; and A source driver circuit having a data receiving circuit to receive the plurality of serial display data in sequence, the data receiving circuit and decoding each of the serial display data to generate output display data, wherein when the first display data is detected The power saving flag is set, and the data transmission circuit and the data reception circuit stop transmitting and receiving the plurality of serial display data. 2 . The driving device according to claim 1 , wherein the timing controller sets the first power saving flag when detecting that M consecutive data contents of the plurality of serial display data are the same, wherein M is a positive integer greater than 1. 3 . The driving device according to claim 1 , wherein the timing controller detects and determines whether to set the second power saving flag according to the change states of consecutive N pieces of the plurality of serial display data, wherein the The source driving circuit stops decoding each of the serial display data when the second power saving flag is set, wherein M is an integer greater than N. 4 . The driving device according to claim 3 , wherein the timing controller sets the second power saving when detecting that the data contents of the plurality of consecutive N pieces of the plurality of serial display data are the same. 5 . flag. 5 . The driving device of claim 4 , wherein the timing controller comprises a plurality of line buffers for storing the plurality of serial display data respectively, and the plurality of line buffers use a first-in, first-out mechanism to store the data. 6 . The plurality of serial display data. 6 . The driving device according to claim 5 , wherein the timing controller is based on when the data contents of the plurality of serial display data in the line buffers of the first N stages of the plurality of line buffers are the same when the data content is the same. 7 . Set the second power saving flag. 7 . The driving device according to claim 5 , wherein the timing controller is based on the data content of the plurality of serial display data in the line buffers of the first N stages of the plurality of line buffers being different from each other. 8 . At the same time, the second power saving flag is cleared. 8 . The driving device according to claim 5 , wherein the timing controller is based on when the data contents of the plurality of serial display data in the line buffers of the first M stages of the plurality of line buffers are the same when the data content is the same. Set the first power saving flag. 9 . The driving device according to claim 5 , wherein the timing controller is based on data contents of the plurality of serial display data in the line buffers of the first M stages of the plurality of line buffers differing from each other. 10 . At the same time, the first power saving flag is cleared. 10. The driving device according to claim 5, wherein the timing controller comprises: the plurality of line buffers; and The comparator, coupled to the plurality of line buffers, is used for determining the changing state of a plurality of consecutive ones of the plurality of serial display data. 11. The driving device according to claim 5, wherein the data receiving circuit comprises: a deserialization circuit, based on receiving the plurality of serial display data, and deserializing each of the serial display data to generate parallel display data; a shift register circuit that receives and temporarily stores the parallel display data; and A latch circuit latches the parallel display data and provides the output display data. 12 . The driving device of claim 11 , wherein when the source driving circuit stops decoding, the source driving circuit stops deserialization, so that the latch circuit and the shift register circuit are disabled. 13 . The side-by-side display data and the output display data in remain unchanged. 13. The driving device according to claim 11, wherein the data receiving circuit further comprises a clock data recovery circuit for generating a clock signal corresponding to each of the serial display data, The size of N is determined according to the clock data recovery capability of the clock data recovery circuit. 14. The driving device according to claim 1, wherein the data transmission circuit of the timing controller transmits each of the serial display data to the data receiving circuit of the source driving circuit through a differential signal pair . 15. The driving device of claim 14, wherein when the first power saving flag is set, the timing controller makes the first signal and the second signal of the differential signal pair both one reference voltage value. 16. The driving device according to claim 15, wherein when the data receiving circuit of the source driving circuit determines that both the first signal and the second signal are the reference voltage value, it stops receiving The plurality of serial display data. 17. A method for transmitting display data, comprising: providing a data transmission circuit of the timing controller to transmit a plurality of serial display data in sequence, and determining whether to set a first power saving flag according to the change state of a plurality of consecutive serial display data; a data receiving circuit providing a source driver circuit to receive the plurality of serial display data in sequence, and perform decoding on each of the serial display data to generate output display data; and When it is detected that the first power saving flag is set, the data transmission circuit and the data reception circuit stop transmitting and receiving the plurality of serial display data. 18. The transmission method according to claim 17, wherein the data transmission circuit of the timing controller is provided to transmit the plurality of serial display data in sequence, and according to the data of the plurality of serial display data The step of determining whether to set the first power-saving flag from a plurality of consecutive changing states includes: When the timing controller detects that the data contents of consecutive M pieces of the plurality of serial display data are the same, the first power saving flag is set, wherein M is an integer greater than 1. 19. The transmission method of claim 18, further comprising: determining whether to set the second power saving flag according to the changing state of N consecutive ones of the plurality of serial display data; and When the second power saving flag is set, the source driving circuit stops decoding each of the serial display data, wherein M is an integer greater than N. 20. The transmission method according to claim 19, wherein the step of determining whether to set the second power saving flag according to the changing state of N consecutive pieces of the plurality of serial display data comprises: The second power saving flag is set when the timing controller detects that N consecutive data contents of the plurality of serial display data are the same. 21. The transmission method of claim 20, further comprising: The timing controller is caused to provide a plurality of line buffers to store the plurality of serial display data respectively, and to provide the plurality of line buffers to store the plurality of serial display data with a FIFO mechanism. 22. The transmission method of claim 21, further comprising: In the plurality of line buffers, the second power saving flag is set when the data contents of the plurality of serial display data in the line buffers of the first N stages are the same. 23. The transmission method of claim 21, further comprising: In the plurality of line buffers, the second power saving flag is cleared when the data contents of the plurality of serial display data in the line buffers of the first N stages are different. 24. The transmission method of claim 21, further comprising: Among the plurality of line buffers, the first power saving flag is set when the data contents of the plurality of serial display data in the line buffers of the first M stages are the same. 25. The transmission method of claim 21, further comprising: In the plurality of line buffers, the first power saving flag is cleared when the data contents of the plurality of serial display data in the line buffers of the first M stages are different. 26. The transmission method according to claim 21, wherein the size of N is determined according to the clock data recovery capability of the clock data recovery circuit of the source driver circuit.

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