CN114374631B

CN114374631B - Test system for testing multiple DUTs

Info

Publication number: CN114374631B
Application number: CN202210010573.7A
Authority: CN
Inventors: 唐锋; 张华峰; 徐素珍
Original assignee: Anbofu Electronics Suzhou Co ltd
Current assignee: Anbofu Electronics Suzhou Co ltd
Priority date: 2022-01-05
Filing date: 2022-01-05
Publication date: 2024-11-22
Anticipated expiration: 2042-01-05
Also published as: CN114374631A

Abstract

The present invention provides a test system for testing multiple devices under test, comprising: at least one test subsystem coupled to a host computer in parallel, each of the test subsystems comprising a communication device coupled to the host computer and at least one test device, and configured to be coupled to one of the multiple devices under test, wherein the host computer assigns a different first address to the at least one test subsystem, and wherein in each of the test subsystems, a different second address is assigned to the at least one test device and the device under test.

Description

Test system for testing a plurality of devices under test

Technical Field

The present invention relates to a test system for testing a plurality of devices under test.

Background

With the development of technology, electronic components and the like on various electronic devices are increasing, and the integration level is also increasing, so that the complexity of the electronic devices is increasing. The reliability of these electronic components is important and directly determines the safety and operational reliability of the electronic device and even the entire system (such as vehicles, machines, equipment, etc. that use the electronic device). Various harsh environmental conditions (e.g., shipping, storage, in-service, climate, etc.) and the like are under test for the reliability of electronic devices.

According to the related studies, in the field of electronic device product testing, most failures are caused by fatigue. All suppliers wish to pass laboratory tests to accelerate the simulation of the entire life cycle of the product under climatic/electrical load pressure, discover defects in the product in advance, and ensure the reliability of the product over the design life. The simulated life test is an acceleration test based on field data simulating actual use, which is used to reduce the time required to test the reliability of electronic components. Among them, the international organization for standardization (International Standardization Organization; ISO) has established test standards. Various relevant test parameters can be determined based on the mathematical model for testing to shorten the time and expense of verification. In general, laboratory tests are used for accelerating the simulation of the conditions under the climate/electrical load pressure in the whole life cycle of the product, finding defects of the product in advance and ensuring the reliability of the product in the design life.

For example, taking the electronic equipment of a vehicle as an example, according to the general provision of the iso_16750-1CN standard: in addition to the environmental load, the electronic equipment products used on vehicles are also subjected to loads generated by their own functions, hereinafter referred to as functional loads. Life tests generally simulate a combination of functional loads and the associated environmental loads that are present at the same time. The life test aims are generally to: 1. determining that the electronic equipment product meets the specification; 2. potential design flaws were found. Typically, design defects can be found by testing functional loads in combination with more environmental loads using real time life tests or accelerated life tests (increased loads). The requirements are generally met with only a small number of devices under test (Device Under Test; DUTs). This situation was previously common. But the number of DUTs is too small to describe the reliability statistically correctly.

With the development of technology, most test plans for body control modules (Body Control Module; BCM) require more data to be obtained at a faster sampling rate, with the expectation that the communication sampling rate for all Input/outputs (I/Os) of all DUTs be <250ms, and that a snapshot of all product I/O states and fault codes be recorded when a product fault is detected. Currently, a so-called time division multiplexing-based monitoring method, which is a method of switching to each test product one by one through a relay and collecting required data from the evaluated product, is commonly adopted by some companies. Because the time division multiplexing adopts the components of mechanical switching, the problems of low testing speed, large volume, high manufacturing cost and the like are necessarily existed. Such an approach may meet the requirements for some less demanding test scenarios (e.g., parametric testing on production lines), but for continuous testing and multiple sample, multi-I/O high power testing requirements, current solutions cannot meet the requirements in terms of speed, cost, space, development cycle, reliability at the same time. For continuous monitoring and testing requirements of BCM products defined in the ISO standard, it is obvious that the previous generation of testing systems has not completely satisfied the current customer requirements.

The prior art published so far only considers the isolated performance test of products, and no systematic testing method is involved, especially the design of a testing system aiming at the ISO standard. Some of the prior art, although using multi-machine testing, are essentially single product based switching tests, which have the following drawbacks if applied to environmental continuous testing conforming to the ISO standard:

1. The multiplexing of resources between test modules results in the inability to work simultaneously during multiple sample testing and also requires that the samples or I/O be powered down during testing. While the standard requires continuous operation, i.e. no power outage at any time.

2. Some existing test methods, multiple machine testing, require DUT software to support address assignment, while the addresses for general diagnostics are the same, require custom product software that is not suitable for general BCM testing.

3. The prior art is designed based on the mode of the external expansion test board card resource of the upper computer, and the direct application of the method to the multi-machine test has the defects of high manufacturing cost, large volume, complex construction and the like.

4. In the prior art, a test system is commonly used between samples, and the environment test requirement of multiple samples for parallel I/O continuous operation cannot be verified when multiple-machine test is realized through switching.

5. Switching current with a host computer cannot be used for function test in multi-machine test because the number of boards for function test is large and the connection between boards is complex. When the single board card expansion adopting the upper computer is applied to the test of the multi-machine BCM, the number of the board cards is increased due to the increase of the IO number, and the connection of the wire harness is complex and the cost is high. If applied to multi-machine testing, the erection is affected by volume and cost limitations.

Disclosure of Invention

Technical problem to be solved by the invention

The present invention has been made in view of the above circumstances, and an object thereof is to provide a test system for testing a plurality of devices under test, which can be adapted to various complex scenarios, can realize multi-machine parallel testing, can form a single system integration, can have a plurality of test parameters, can realize environment synchronous testing, and can realize continuous monitoring.

Technical proposal for solving the technical problems

In one embodiment of the present invention which solves the above-mentioned problems, there is provided a test system for testing a plurality of devices under test, comprising: at least one test subsystem coupled in parallel to a host computer, each of the test subsystems comprising a communication device and at least one test device coupled to the host computer and configured for coupling to one device under test of the plurality of devices under test, wherein the host computer assigns a different first address to the at least one test subsystem, and wherein the at least one test device and the device under test are assigned different second addresses in each of the test subsystems.

According to an embodiment of the invention, the upper computer is configured for assigning the first address to each of the test subsystems based on a unique identifier of the communication device of said each of the test subsystems.

According to an embodiment of the invention, in each of the test subsystems, the at least one test device occupies a first type of frame and the device under test occupies a second type of frame different from the first type, and the at least one test device and the device under test are assigned the second address based on the type of frame.

According to an embodiment of the present invention, the frame of the first type is one of a standard frame and an extended frame, and the frame of the second type is the other of the standard frame and the extended frame.

According to an embodiment of the invention, the at least one test device is connected to the communication device via a dial switch.

According to an embodiment of the invention, the at least one test subsystem is coupled to the upper computer via a Controller Area Network (CAN) and/or the one device under test is coupled to the corresponding test subsystem via the controller area network.

Effects of the invention

According to the present invention, at least the following effects can be achieved:

1. The system CAN support a single bus protocol, and CAN integrate different devices with Controller Area Network (CAN) addresses into a unified communication interface through solidified software and an open interface;

2. The parallel distributed structure can be realized, low-precision sampling resources are built in to perform independent sampling (not based on matrix switching), and high-precision sampling adopts a high-speed electronic switch to replace mechanical switching, so that the occupied space is small (three-dimensional stacked structure).

Drawings

So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings, wherein like reference numerals have been used, to facilitate an understanding, to identify identical elements that are common to the various figures. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments, and that:

FIG. 1 is a schematic block diagram of a test system according to one embodiment of the invention.

FIG. 2 is a schematic diagram of a relationship of a test system and a device under test according to one embodiment of the invention.

It is contemplated that elements of one embodiment of the present invention may be beneficially employed in other embodiments without further recitation.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, technical solutions of the present application according to some embodiments of the present application will be described in detail below. It will be apparent that the described embodiments are only some, but not all, of the embodiments encompassed by the present application. All other embodiments, based on the examples herein, which are within the scope of the application as defined by the claims, will be within the scope of the application as defined by the claims.

Hereinafter, specific embodiments of the present invention will be described in detail based on the drawings. The drawings are for simplicity and are not drawn to scale, and the actual dimensions of the structures are not shown. For ease of understanding, the same reference numbers are used in the various figures to denote the same elements in common in the figures. The drawings are not to scale and may be simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation.

The terms "test," "measurement" are used interchangeably herein.

As one example, a test system (TEST SYSTEM; TS) 100 for testing a plurality of Devices Under Test (DUTs) according to the present invention may include at least one test subsystem 110, at least one test subsystem 110 being coupled in parallel to a host computer 120. Each test subsystem 110 may include a communication device 111 and at least one test device 112. The communication device 111 may be coupled to the host computer 120. Each test subsystem 110 may be configured for coupling to one device under test 130 of the plurality of devices under test 130. As a non-limiting example, as shown in fig. 1, test subsystem 110 may include a test device 112 (such as one or more load boards), and a communication device 111. The upper computer 120 may be configured to assign a first address (e.g., addresses CAN1 through CANn shown in FIG. 1) to each test subsystem 110 based on the unique identifier of the communication device 111 of each test subsystem 110.

Alternatively, in each test subsystem 120, at least one test device 112 may occupy a frame of a first type (e.g., one of a standard frame and an extended frame), and the device under test 130 may occupy a frame of a second type (e.g., the other of the standard frame and the extended frame) different from the first type, and the at least one test device 112 and the device under test 130 may be assigned a second address based on the type of the frame.

Alternatively, at least one test device 112 may be connected to the communication device 111 by a dial switch. The binary combination may be read as an address after power-on, and n Input Output (IO) addresses may be allocated 2 ⁿ addresses.

Optionally, at least one test subsystem 110 may be coupled to the upper computer 120 via a controller area network (Controller Area Network; CAN). Alternatively or additionally, one device under test 130 may be coupled to each test subsystem 110 via a controller area network.

As one example, the test system to which the present invention relates may specifically include: the system comprises an upper computer management system, a CAN communication module, a signal conditioning adapter module, a signal card (comprising an input card and an output card), a test bed, a load, a product adapter and the like.

To achieve the platform test, the applicant has studied the characteristics of the test object sufficiently. They can be classified into several categories according to their generality, as shown in fig. 2. Due to the large number of IOs, the signal types and the testing methods are different, and reasonable classification is an important component of testing work. In actual terms, more than 95% of the test terms are DI/DO, but some test methods can be used to cover 100% of the test requirements. To test these several special test items, the applicant has also devised a flexible hardware-configurable FPGA (Field Programmable GATE ARRAY: field programmable gate array) to meet different requirements.

The premise that a DUT can be automatically tested is based on known test methods, i.e., conventional signals with predictable execution results, and that the critical parameters can be evaluated using logic values. For signals that cannot be evaluated, various test equipment or instrumentation may be used for analysis. The test conditions of the test system are different DUT modes, climates, chemistries, vibrations and other loads. These conditions are factors that cause the system output to deviate from range or fail. When fault alarm occurs, manual intervention is needed, and the fault position is switched to be subjected to full-parameter analysis through a high-precision instrument. In the applicant's design, any channel can be switched to a third party instrument by an electronic analog switch, taking this into account. It can also cooperate with computer instruction to make it run in automatic scanning and single-step mode to implement diagnosis.

Prior to testing, debugging operations may be performed. By means of manual mode, the characteristics of the DUT output and excitation signals can be analyzed by means of instruments and tools, a test method is proposed that enables automation. Thus, in automated test systems, applicants' DUT software is special software developed for testing purposes, including diagnostic UDS (Universal DATA SYSTEM: universal data System)/other protocols and software that enables special modes of operation. Testing can be divided into two parts, one part is that the DUT outputs specific signals to the signal card for collection and calculation, and the other part is that the signal card outputs excitation to the DUT for diagnosis.

DUT load loading can have several methods, such as actual load loading, electronic load loading, and equivalent resistive load loading. The technique may be tested based on an equivalent resistive load. The equivalent resistance is easy to manufacture and integrate on a large scale compared to the actual load. The corresponding load may be defined according to dds_01_29 specification requirements and design files.

For simultaneous testing of multiple samples (e.g., DUTs), there are many limitations in design if multiple superordinated computers are employed. Applicants have found that a center-plus-distribution architecture can be employed: 1. the dependence on the upper computer can be removed after the combination of the buses, most of the tests are completed on the lower computer, and the upper computer can only be responsible for summarizing the test data and storing the results of different test subsystems; 2. the test subsystems are completely independent, different addresses are identified by using the unique serial numbers of the communication tools, and communication bus multiplexing among different test subsystems is avoided; 3. different test devices in the test subsystem are subjected to bus multiplexing, different interfaces are fused by software in the test subsystem, interaction with different test objects can be performed through protocol routing, and only one communication interface for diagnosis is reserved. Such a design allows the systems to operate completely independently of each other to facilitate parallel testing.

In addition to requiring host software to address the assignment of multiple communication addresses, simultaneous testing of multiple samples also requires addressing the problem of CAN network address assignment within a single test subsystem (e.g., a test subsystem may contain a communication device and at least one test device, where the communication device may be coupled to a host computer and each test subsystem may be configured to be coupled to a DUT). The multi-machine communication address allocation is identified through different CAN equipment serial numbers, equipment is powered on manually one by one, the equipment serial numbers are acquired and recorded in a software configuration table, and the corresponding relation between the DUT and the CAN equipment is established.

CAN bus multiplexing CAN be realized in the test subsystem, and each CAN, the lower computer and the DUT are connected in parallel. The CAN bus in the test subsystem avoids the address allocation process between devices by a method of combining static and dynamic allocation addresses. When two devices are in the CAN network address allocation process, the CAN has two address types, so that the address allocation is not needed, and the design of the applicant ensures that the addresses cannot conflict by using the mutual staggering of the standard frame and the extended frame ID, and the addresses of the two devices are statically allocated, thereby avoiding the CAN network address allocation process.

When multiple devices are present, the DUT occupies a single type of address (standard or extended frame) and the other test devices together occupy a single type of address, which continues to be assigned different CAN addresses. Most of the current designs are to distribute CAN network addresses through the cooperation of upper computer software and DUT software, and the testing method increases the workload of the software.

An exemplary allocation procedure for the CAN network address of the present invention is as follows: before no allocation, the CAN addresses are the same in the two device initialization states; the power supply is controlled by the mechanical switch, one device is electrified, addresses are allocated to the other device, and different addresses are allocated to the other device until the allocation is completed. For example, the applicant adopts a dial switch to read addresses, and reads binary combinations as addresses after power-on, for example, 3 IOs can be allocated 8 addresses. Because the CAN bus is responsible for testing, interfaces such as Ethernet CAN be used for network synchronization and status monitoring. Theoretically, the more samples, the more test time such a design would save compared to a center design. The test speed of actually testing six samples is many times that of the original.

The invention can distinguish between different systems in multi-machine communication by adopting independent communication cards. The test subsystem adopts a method of distinguishing different equipment addresses by a dial switch, thereby realizing real multi-machine parallel test. Each module is grouped by an I/O multiple of 64 and with a unique network address, can cover different sample I/O numbers. Such designs are based on the number of I/os of most existing BCMs. If the number of single groups is too small, buses and boards become more, otherwise, if the number of single groups is too large, wiring is complex, the area of a single circuit is large, and processing cost is high. The test time of the invention does not increase with the number of I/Os, and a single IO is less than 250ms, and the total time required for completing all the tests only needs tens of seconds.

The applicant adopts a comprehensive scheme, and uses a powerful upper computer for data communication and real-time display of the current card of the lower computer real-time system added with NI to record and store data in real time. The lower computer can be used for I/O expansion, logic control and parameter collection and function test. Thus, the method can solve the problems of a large number of I/O functions, large current and synchronous sleep current test of multiple machines and environments. According to the invention, different technologies can be complemented by adopting the structural design of the upper computer and the lower computer expansion board card.

The voltage measuring module is designed, and can be configured to enable the voltage of the output signal of the DUT to be between 0 and 24V, the voltage at the front end of acquisition is firstly subjected to signal conditioning and then is attenuated by a high-precision resistor and then enters the emitter and follower to be switched by an analog switch, so that the voltage range of the analog signal to be measured, which is input into the AD chip, is between 0 and 5V. And, the frequency test may be to select 1 via the analog switch 128 before entering signal conditioning and sampling. The multi-path analog switch can be adopted for switching, 16 paths of AI input are changed through grouping, specifically, 2 groups of 64 paths, namely 2 groups of 16-piece 8-selection analog switches are adopted to be changed into 28 paths of AI, and the multi-path analog switch can be realized by only two pieces of 8-channel AD chips, and can realize simultaneous acquisition of 16 paths of input. With regard to the address, a simultaneous control method may be adopted, so that the address and a large amount of switching time may be saved, and the speed of the electronic switch is very fast, so that the factor affecting the maximum test speed is not a definite measure of the voltage, and thus the design is reasonable.

The environmental conditions, sleep current, DI/DO electrical parameters, and other measured data can be integrated together, recorded in TDMS format, and thus displayed in a table and graphic, viewable in single and multiple channels with dedicated software.

In addition to the lower computer test, higher accuracy measurements can be made via the third party meter, taking into account the measurements of the external third party meter. The design can realize the measurement of an external third-party instrument, and can be matched with a multi-way switching card so as to support the development of other platforms, such as an NI/vector system. Therefore, the device is convenient to develop and debug, and can be separated from a lower computer to test by an upper computer.

In view of the multiple CAN/LIN, the cost, wiring, software development and channel configuration required by the external communication tool extension approach CAN be employed. The applicant designs an analog switch, so that signal multiplexing expansion CAN be realized, and expansion of a plurality of paths of CAN/LINs CAN be realized. The design can realize integrated design in the signal card without configuring a channel, the reliability of the intra-board switching measurement loop is higher, and the software development and hardware cost is better.

Compared with the prior art, according to one or more embodiments of the present invention, at least the following advantages can be achieved:

1. The optimization is realized on the communication mode of the system. In the communication structure of the multi-machine parallel test system, the prior art adopts multiple devices, so that different communication interfaces (such as upper computer input, PXI (PCI eXtensions for Instrumentation: peripheral device interconnection bus), serial ports, 485, networks, LIN, CAN and the like) of different manufacturers exist, and different communication protocols need to be developed. The invention adopts a special lower computer test system with simple structure, different test interfaces required by test can be integrated through one system, and the internal communication gateway can realize a single test interface by forwarding.

2. Optimization is achieved on the test mode of the system. For the traditional time division multiplexing method, a single BCM has 130 IOs, and if 6 samples are tested for one round of inspection, the test needs to be repeated many times. According to the invention, a parallel distributed architecture of the lower computer can be adopted, so that all IO can be tested at one time, and the efficiency is improved.

3. An integrated scheme is realized. The invention can be solved by an integrated special scheme, and unnecessary components can be removed by integrating all the test resources into the system, so that intermediate links are avoided, and the interactive process and development of different devices are reduced.

4. Optimization is achieved on the test capacity of the system. The original design requires cumbersome channel configuration. Compared with an external communication module, the novel design realizes multi-path expansion through the analog change-over switch, has low cost, solves the problem in one system, and does not need complex software configuration.

5. Different numbers of DUT tests can be accommodated by flexible combinations. Each module in the invention can be grouped according to multiples of 128 and is allocated with a network address, and can cover different sample IO numbers. No redesign is required to add samples, as long as the same hardware is modified and installed on the configuration software.

The foregoing describes in detail alternative embodiments of the present application. It will be appreciated that various embodiments and modifications may be resorted to without departing from the broad spirit and scope of the application. Many modifications and variations will be apparent to those of ordinary skill in the art in light of the concepts of the application without undue burden. As non-limiting examples, one skilled in the art may omit or add one or more of the various components of the systems or structures described above, or replace some or all of the various structures or systems involved in the present embodiments with other components having the same or similar functionality. Therefore, all technical solutions which can be obtained by logic analysis, reasoning or limited experiments based on the prior art by a person skilled in the art according to the inventive concept shall fall within the scope of protection defined by the claims of the present application.

Claims

1. A test system for testing a plurality of devices under test, comprising:

at least one test subsystem coupled in parallel to the host computer, each of the test subsystems comprising a communication device coupled to the host computer and at least one test device, and configured to be coupled to one of the plurality of devices under test,

The host computer assigns a different first address to the at least one test subsystem, and

Wherein, in each of the test subsystems, different second addresses are allocated to the at least one test device and the device under test,

Wherein, in each of the test subsystems,

The at least one test device occupies a first type of frame, and the device under test occupies a second type of frame different from the first type, the first type of frame being one of a standard frame and an extended frame, the second type of frame being the other of the standard frame and the extended frame, and

The second address is assigned to the at least one testing device and the device under test based on the type of the frame.

2 . The test system according to claim 1 , wherein the host computer is configured to allocate the first address to each of the test subsystems based on a unique identifier of a communication device of each of the test subsystems. 3 .

3. The test system according to claim 1, wherein the at least one test device is connected to the communication device via a dip switch.

4. The test system as claimed in claim 1, characterized in that the at least one test subsystem is coupled to the host computer via a controller area network, and/or the one device under test is coupled to the corresponding test subsystem via the controller area network.