CN108594106A - System level chip assessment device and method - Google Patents

Abstract

The invention relates to a system-level chip evaluation device and method. Including ATE test board, SoC system verification board and controller. The controller controls the ATE test board to obtain the parameter-level data of the system-level chip to be tested, and controls the SoC system verification board to obtain the application-level data of the system-level chip to be tested. The parameter-level data and application-level data of the level chip are used to obtain the evaluation results of the system chip under test. It can not only realize the parameter-level test of the system-level chip to be tested, but also realize the application-level test of the system-level chip to be tested. It can perform performance tests on the SoC chip more comprehensively and systematically, so as to obtain more comprehensive evaluation results, which can reduce SoC. The dependence of chip testing on automated testing equipment can also greatly reduce the huge cost caused by hardware upgrades of automated testing equipment.

Description

System-level chip evaluation device and method

technical field

The invention relates to the technical field of chip testing, in particular to a system-level chip evaluation device and method.

Background technique

With the rapid development of integrated circuits, SoC (System on Chip, system-on-chip/system-on-chip) chips are increasingly widely used, especially in the fields of high performance, low power consumption and miniaturization of electronic consumer products. SoC technology integrates digital, analog, radio frequency and corresponding interface modules through IP (Intellectual Property, intellectual property) core multiplexing, making full use of existing design accumulation, and reducing power consumption, reducing area, and increasing system functions It has obvious advantages in terms of improving speed and saving costs.

In the manufacturing process of SoC chips, any slight process error and change will cause defects in the chip, making the chip unable to work normally. The test results of the chip can also reflect whether there are design defects and boundary problems that have not been considered in the chip design process. Therefore, it is necessary to test the produced SoC chips.

The SoC chip is composed of millions or even hundreds of millions of components, with a system clock frequency as high as hundreds of MHz or even GHz. The chip needs to realize a variety of functions, and there are intricate timing relationships within and between modules. Most of them use deep Sub-micron process technology, these characteristics of SoC chips have brought challenges to its testing work. Traditional SoC chip testing is limited by hardware conditions, and the chip testing carried out on it has the problem of one-sided testing, which cannot well realize the chip testing of SoC chips.

Contents of the invention

Based on this, it is necessary to provide a system-level chip evaluation device and method capable of performing a complete test on the SoC chip to address the above problems.

A system-level chip evaluation device includes an ATE test board, a SoC system verification board and a controller, and the ATE test board and the SoC system verification board are respectively connected to the controller;

The controller controls the ATE test board to obtain the parameter-level data of the system-level chip to be tested, controls the SoC system verification board to obtain the application-level data of the system-level chip to be tested, and obtains the parameter-level data and application-level data of the system-level chip to be tested. The evaluation results of the SoC.

The above-mentioned system-level chip evaluation device includes an ATE test board, a SoC system verification board and a controller. The controller controls the ATE test board to obtain the parameter-level data of the system-level chip to be tested, and controls the SoC system verification board to obtain the application of the system-level chip to be tested. The ATE test board obtains the parameter-level data of the system-level chip to be tested, the SoC system verification board obtains the application-level data of the system-level chip to be tested, and the controller obtains the parameter-level data and application-level data of the system-level chip to be tested. Evaluation results of the SoC under test. The system-level chip evaluation device evaluates the system-level chip to be tested from two aspects: parameter-level data and application-level data of the system-level chip to be tested. It can not only realize the parameter-level test of the system-level chip to be tested, but also realize the The application-level testing of level chips can perform performance tests on SoC chips more comprehensively and systematically, so as to obtain more comprehensive evaluation results, and this can reduce the dependence of SoC chip testing on automated testing equipment, and can also greatly reduce the impact of automated testing equipment. Huge costs associated with hardware upgrades.

In one embodiment, the SoC evaluation device further includes a development board connected to the SoC system verification board.

In one embodiment, the SoC evaluation device further includes a signal generator connected to the SoC system verification board.

In one embodiment, the SoC evaluation device further includes an oscilloscope connected to the SoC system verification board.

In one embodiment, the SoC evaluation device further includes a host computer connected to the SoC system verification board.

In one embodiment, the SoC system verification board in the system-on-a-chip evaluation device includes a peripheral interface and a processor, the peripheral interface is connected to the processor, and the processor is connected to the system-on-chip to be tested.

In one embodiment, the SoC system verification board in the system-on-a-chip evaluation device further includes a SoC test socket, and the system-on-chip to be tested is connected to the processor through the SoC test socket.

In one embodiment, the SoC system verification board in the system-on-chip evaluation device further includes a memory interface, and the memory interface is connected to the processor.

A system-level chip evaluation method of the system-on-chip evaluation device described in any one of the above, comprising:

The system-level chip to be tested is tested through the ATE test board to obtain the parameter-level data of the system-level chip to be tested;

When the ATE test of the system-level chip to be tested is qualified, the system-level chip to be tested is subjected to a board-level test through the SoC system verification board, and the application-level data of the system-level chip to be tested is obtained;

According to the parameter-level data of the system-level chip to be tested and the application-level data of the system-level chip to be tested, an evaluation result of the system-level chip to be tested is obtained.

In one embodiment, in the system-level chip evaluation method, the system-level chip to be tested is subjected to an ATE test through an ATE test board, and after obtaining the parameter-level data of the system-level chip to be tested, it also includes:

When the ATE test of the system-on-chip to be tested is unqualified, a failure analysis is performed on the unqualified system-on-chip under the ATE test.

The above system-level chip evaluation method includes performing an ATE test on the system-level chip to be tested through an ATE test board to obtain parameter-level data of the system-level chip to be tested; when the system-level chip to be tested passes the ATE test, the system-level chip to be tested passes The SoC system verification board conducts board-level testing to obtain the application-level data of the system-level chip to be tested; according to the parameter-level data of the system-level chip to be tested and the application-level data of the system-level chip to be tested, the evaluation results of the system-level chip to be tested are obtained . The system-level chip evaluation method evaluates the system-level chip under test from two aspects: parameter-level data and application-level data of the system-level chip to be tested. The application-level testing of level chips can perform performance tests on SoC chips more comprehensively and systematically, so as to obtain more comprehensive evaluation results, and this can reduce the dependence of SoC chip testing on automated testing equipment, and can also greatly reduce the impact of automated testing equipment. Huge costs associated with hardware upgrades.

Description of drawings

Fig. 1 is a structural block diagram of a system-level chip evaluation device in an embodiment;

Fig. 2 is a schematic diagram of a SoC testing framework in an embodiment;

Fig. 3 is the schematic diagram of ATE test equipment in an embodiment;

Fig. 4 is a system architecture diagram of a SoC system verification board in an embodiment;

Fig. 5 is a schematic diagram of the SoC socket in one embodiment;

FIG. 6 is a schematic flowchart of a system-level chip evaluation method in an embodiment;

Fig. 7 is a flow chart of SoC chip comprehensive performance test and evaluation in one embodiment.

Detailed ways

A system level chip evaluation device, as shown in Figure 1, comprises ATE test board 100, SoC system verification board 200 and controller 300, and ATE test board 100 and SoC system verification board 200 are connected with controller 300 respectively; Controller 300 Control the ATE test board 100 to obtain the parameter-level data of the system-level chip to be tested, control the SoC system verification board 200 to obtain the application-level data of the system-level chip to be tested, and obtain the parameter-level data and application-level data of the system-level chip to be tested. The evaluation results of the SoC.

The ATE test board 100 is used to acquire parameter-level data of the SoC under test. Parameter-level data refers to the data obtained by testing parameters related to SoC chip interface characteristics, including DC parameters, AC parameters, etc., and specific tests are completed under different voltage, current, frequency and load conditions. The electrical test of the chip can be realized by ATE (Automatic Test Equipment, automated test equipment). The automated test equipment can apply a certain stimulus or test vector to the system-level chip to be tested, so that the system-level chip to be tested is in a certain state, so that the test Measure the electrical characteristics of the system-on-a-chip.

The automated test equipment includes a test head, which can be configured with multiple test cards. Each test card has a test probe. The test head can be connected to the ATE test board. When the test head applies stimulus or test vector to the ATE test board, the ATE The SoC under test on the test board will get the corresponding test stimulus and vector. The SoC under test gets the corresponding test stimulus and vector, and will output some responses to the ATE test board.

The SoC system verification board 200 is used to obtain application-level data of the SoC under test. Application-level data refers to the data obtained by placing the SoC chip in a real working environment for functional-level testing. The SoC chip to be tested executes the corresponding test program. The test program includes the functions that the SoC chip to be tested needs to be tested. class. For example, a test program use case library can be established for application-level test items such as operating performance, high-speed communication interface protocol, system-level average power consumption, and maximum operating frequency. On the SoC system verification board, after the SoC chip to be tested starts normally, load the test The application program in the program use case library realizes the application-level data test of the SoC chip to be tested through the output signal and indicator signal of the SoC chip to be tested when the program is running.

The controller 300 is used to control the ATE test board to obtain the parameter-level data of the system-level chip to be tested, and control the SoC system verification board to obtain the application-level data of the system-level chip to be tested. , to obtain the evaluation result of the system chip under test. The controller 300 receives the parameter-level data of the system-level chip under test acquired by the ATE test board and the application-level data of the system-level chip under test acquired by the SoC system verification board, and converts the acquired parameter-level data of the system-level chip under test into Compared with the preset parameter standards, it can be judged whether the system-level chip to be tested is a good chip or a defective chip, so as to achieve the purpose of screening out unqualified chips. Comparing the obtained application-level data of the SoC under test with the corresponding preset value, and further judging the performance of the SoC under test.

The above-mentioned system-level chip evaluation device includes an ATE test board, a SoC system verification board and a controller. The controller controls the ATE test board to obtain the parameter-level data of the system-level chip to be tested, and controls the SoC system verification board to obtain the application of the system-level chip to be tested. The ATE test board obtains the parameter-level data of the system-level chip to be tested, the SoC system verification board obtains the application-level data of the system-level chip to be tested, and the controller obtains the parameter-level data and application-level data of the system-level chip to be tested. Evaluation results of the SoC under test. The system-level chip evaluation device evaluates the system-level chip to be tested from two aspects: parameter-level data and application-level data of the system-level chip to be tested. It can not only realize the parameter-level test of the system-level chip to be tested, but also realize the The application-level testing of level chips can perform performance tests on SoC chips more comprehensively and systematically, so as to obtain more comprehensive evaluation results, and this can reduce the dependence of SoC chip testing on automated testing equipment, and can also greatly reduce the impact of automated testing equipment. Huge costs associated with hardware upgrades.

In one embodiment, the controller is also used to control the SoC system verification board to obtain limit test data, according to the parameter level data of the system level chip under test, the application level data of the system level chip under test and the limit test of the system level chip under test data to obtain the evaluation results of the SoC under test. The limit parameter test of the system-level chip to be tested is performed to obtain the limit test data of the system-level chip to be tested. The limit parameter refers to the limit value of each measurement parameter, such as the highest frequency and the highest voltage.

In one embodiment, the SoC evaluation device further includes a development board connected to the SoC system verification board. The development board can provide the input signal of the SoC system verification board or collect the output signal of the SoC system verification board. The development board is a circuit board used for embedded system development, including a central processing unit, a memory, an input device, an output device, and a data path. A series of hardware components such as / bus and external resource interface. Generally speaking, in the embedded system development process, the hardware is divided into two platforms, one is the development platform, and the other is the target platform, that is, the development board. The development platform refers to using a computer to connect to a target platform through a transmission interface, such as a serial port, USB (Universal Serial Bus, universal serial bus), parallel port, or a network. Specifically, the development board can be an FPGA development board, and FPGA (Field Programmable Gate Array, Field Programmable Gate Array), as a semi-custom circuit in the field of application-specific integrated circuits, not only solves the shortcomings of custom circuits, but also overcomes the limitations of original programmable devices. The disadvantage of the limited number of gate circuits.

In one embodiment, the SoC evaluation device further includes a signal generator connected to the SoC system verification board. The signal generator is used to generate electrical test signals of specific parameters required by the circuit under test. When testing the SoC chip to be tested, in order to measure some electrical parameters of the SoC chip to be tested, such as measuring frequency response, noise figure, etc., provide electrical signals that meet the specified technical conditions to simulate the SoC chip to be tested in actual work. motivating signal. Signal sources can be divided into four categories according to different output waveforms: sine wave signal generator, rectangular pulse signal generator, function signal generator and random signal generator. The function of the signal generator is the signal modulation function. Signal modulation refers to the amplitude, phase or frequency change of the modulated signal, which embeds low-frequency information into the high-frequency carrier signal. The obtained signal can be transmitted from voice, to data, to video. any signal.

In one embodiment, the SoC evaluation device further includes an oscilloscope connected to the SoC system verification board. An oscilloscope is an electronic measuring instrument that can convert electrical signals into images, which is convenient for studying the changing process of various electrical phenomena. The oscilloscope uses a narrow electron beam composed of high-speed electrons to hit a screen coated with fluorescent substances to produce tiny light spots. Under the action of the signal under test, the electron beam is like the tip of a pen, which can draw the change curve of the instantaneous value of the signal under test on the screen. The oscilloscope can be used to observe the waveform curves of various signal amplitudes changing with time, and can also test various electric quantities, such as voltage, current, frequency, phase difference, amplitude modulation, etc. The output signal of the SoC chip to be tested can be observed through an oscilloscope to judge its performance.

In one embodiment, the SoC evaluation device further includes a host computer connected to the SoC system verification board. The upper computer is responsible for data communication of the serial port and other network ports, and is connected to the SoC system verification board through a serial port cable or other ports, specifically, it may be a PC (Personal Computer, personal computer).

In one embodiment, the SoC system verification board in the system-on-a-chip evaluation device includes a peripheral interface and a processor, the peripheral interface is connected to the processor, and the processor is connected to the system-on-chip to be tested. The peripheral interface is used to connect external devices, the peripheral interface is connected with the processor, and the processor can read information of the external device.

In one embodiment, the SoC system verification board in the system-on-a-chip evaluation device further includes a SoC test socket, and the system-on-chip to be tested is connected to the processor through the SoC test socket. The electrical connection between the SoC chip and the SoC system verification board can be realized through the SoC test socket, so as to realize the replacement of the SoC chip sample.

In one embodiment, the SoC system verification board in the system-on-chip evaluation device further includes a memory interface, and the memory interface is connected to the processor. According to the basic performance requirements of the SoC chip, the SoC system verification board includes modules such as processor, memory interface, peripheral interface, status indication, power management, power switch, etc., and has the ability to test the development environment and software support.

In one embodiment, a system-level chip evaluation device includes two parts: ATE test and board-level test, which respectively carry out basic function, structural test, interface characteristic-related parameter level test and operational performance, high-speed communication interface protocol, and test program Application-level tests such as use case verification, system-level average power consumption, and maximum operating frequency are shown in Figure 2.

The ATE test is based on the PER-PIN architecture and can complete the SoC chip interface characteristic-related parameter level test, including DC, AC and other parameters. ATE parameter testing includes: 1. Clear parameter definition and formulate test plan; 2. Design test board to ensure that the test board can realize this type of parameter test (for example, some parameters need to be added to special interface); 3. Make test for this type of parameter Test vectors; 4. Vector conversion; 5. Debug vectors on the machine, write test codes for parameter testing. In the ATE test, different voltage, current, frequency, load condition specific or multiple combination tests can be flexibly realized through the soft interactive programming interface, and the test accuracy is high, and microscopic measurements of nA, ns, uV levels can be realized. SoC chip Some parameters of the interface characteristics are listed in Table 1.

Table 1 Some parameters of the interface characteristics of the SoC chip

The ATE test equipment for SoC chips is shown in Figure 3. The left side of the figure is the overall picture. In the overall picture, the power supply and data lines are mainly placed in the cabinet. The inclined square part in the overall picture is the test head, and the test board is placed on it. The right picture is A close-up picture of the test board with the sockets that hold the SoC chip on the test board.

The system architecture of the SoC system verification board is shown in Figure 4. The upper computer is a PC, which is responsible for the data communication of the serial port and other network ports. The PC is connected to the SoC system verification board through a serial port line or other ports; The FPGA development board and the DC power supply are respectively connected to the SoC system verification board to provide the input signal of the SoC system verification board or collect and detect its output signal. For application-level test items such as operational performance, high-speed communication interface protocol, test program use case verification, system-level average power consumption, and maximum operating frequency, a test program use case library is established. Some test program use case libraries are shown in Table 2.

Table 2 Test program use case library

On the SoC system verification board, after the chip starts normally, the application programs in the test program use case library are loaded respectively, and the chip's output signal and indicator signal are judged when the program is running, and the application-level test verification of the chip is carried out.

The test boards in the SoC evaluation device are divided into two types: ATE test boards and SoC system verification boards. When testing a SoC chip with a high-speed interface on an ATE machine, many factors in the signal path will affect the quality of the signal, and even cause the test result to be invalid. The main principles of ATE test board design include that high-speed signal transmission needs to be based on signal integrity to carry out design simulation work and layout and wiring needs to be based on specific models of ATE. According to the basic performance requirements of the SoC chip, the board of the SoC system verification board includes the SoC chip under test, processor, external memory interface, peripheral interface, status indication, power management, power switch and other modules, with development environment and software support The test capability, the peripheral interface can be UART (Universal Asynchronous Receiver/Transmitter, Universal Asynchronous Receiver Transmitter), SPI (Serial Peripheral Interface, Serial Peripheral Interface), GPIO (General Purpose Input Output, general purpose input/output), I2C (Inter-Integrated Circuit), PWM (Pulse Width Modulation, pulse width modulation), CAN (Controller Area Network, controller area network), TIMER (timer), WATCHDOG (watchdog) and other interfaces. The SoC system verification board needs to use a special test socket to realize the electrical connection between the chip and the SoC system verification board, so as to realize the replacement of the SoC sample. The SoC test socket is shown in Figure 5.

In one embodiment, as shown in FIG. 6, a system-on-chip evaluation method of the system-on-chip evaluation device described in any one of the above, including:

Step 602 , performing ATE test on the SoC under test through the ATE test board to obtain parameter level data of the SoC under test.

The ATE test board is used to obtain parameter-level data of the SoC under test. Parameter-level data refers to the data obtained by testing parameters related to SoC chip interface characteristics, including DC parameters, AC parameters, etc., and specific tests are completed under different voltage, current, frequency and load conditions. The electrical test of the chip can be realized by ATE (Automatic Test Equipment, automated test equipment). The automated test equipment can apply a certain stimulus or test vector to the system-level chip to be tested, so that the system-level chip to be tested is in a certain state, so that the test Measure the electrical characteristics of the system-on-a-chip.

Specifically, the ATE test needs to be tested at three different temperatures, which are room temperature, high temperature and low temperature in sequence. In the chip specification, the maximum temperature and the minimum temperature of the chip are defined, which are the two extreme temperatures that need to be detected in the chip test. In addition, since most chips work at room temperature, testing at room temperature can make chip testing more comprehensive. In some tests, the worst case of chips occurs at low temperature, while the worst case of other chips may appear at high temperature. Through high temperature testing, chips that fail at high temperatures can be screened.

Step 604 , when the ATE test of the SoC under test is qualified, perform a board-level test on the SoC system verification board to obtain application-level data of the SoC under test.

The obtained parameter-level data of the system-level chip under test is compared with the preset standard, and when the obtained parameter-level data is within the range of the preset standard, it means that the ATE test of the system-level chip under test is qualified. When the ATE test of the system-level chip to be tested is qualified, the system-level chip to be tested is subjected to a board-level test through the SoC system verification board to obtain application-level data of the system-level chip to be tested. Application-level data refers to the data obtained by placing the SoC chip in a real working environment for functional-level testing. The SoC chip to be tested executes the corresponding test program. The test program includes the functions that the SoC chip to be tested needs to be tested. class. For example, a test program use case library can be established for application-level test items such as operating performance, high-speed communication interface protocol, system-level average power consumption, and maximum operating frequency. On the SoC system verification board, after the SoC chip to be tested starts normally, load the test The application program in the program use case library realizes the application-level data test of the SoC chip to be tested through the output signal and indicator signal of the SoC chip to be tested when the program is running.

Step 606: Obtain an evaluation result of the SoC under test according to the parameter level data of the SoC under test and the application level data of the SoC under test.

The parameter-level data of the SoC under test is compared with the preset standard parameter data to obtain the ATE test result of the SoC under test. The application-level data of the system-level chip to be tested is compared with the preset standard application data to obtain a board-level test result of the system-level chip to be tested. According to the ATE test results of the system-level chip to be tested and the board-level test results, analysis and sorting are carried out to obtain the evaluation results of the system-level chip to be tested.

The above system-level chip evaluation method includes performing an ATE test on the system-level chip to be tested through an ATE test board to obtain parameter-level data of the system-level chip to be tested; when the system-level chip to be tested passes the ATE test, the system-level chip to be tested passes The SoC system verification board conducts board-level testing to obtain the application-level data of the system-level chip to be tested; according to the parameter-level data of the system-level chip to be tested and the application-level data of the system-level chip to be tested, the evaluation results of the system-level chip to be tested are obtained . The system-level chip evaluation method evaluates the system-level chip under test from two aspects: parameter-level data and application-level data of the system-level chip to be tested. The application-level testing of level chips can perform performance tests on SoC chips more comprehensively and systematically, so as to obtain more comprehensive evaluation results, and this can reduce the dependence of SoC chip testing on automated testing equipment, and can also greatly reduce the impact of automated testing equipment. Huge costs associated with hardware upgrades.

In one embodiment, in the system-on-chip evaluation method, the system-on-chip to be tested is subjected to ATE testing through an ATE test board, and after obtaining the parameter-level data of the system-on-chip to be tested, it further includes: when the ATE test of the system-on-chip to be tested fails When qualified, failure analysis is performed on the SoCs under test that fail the ATE test. Perform failure analysis on the system-level chips under test that fail the ATE test. For example, you can first classify the failure types, such as analog signals, audio signals, video signals, and peripheral interfaces.

In one embodiment, in the system-level chip evaluation method, when the ATE test of the system-level chip to be tested is qualified, the system-level chip to be tested is subjected to a board-level test through the SoC system verification board, and the application-level data of the system-level chip to be tested is obtained. Afterwards, it also includes: when the board-level test of the system-level chip to be tested is qualified, the limit parameter test is performed on the system-level chip to be tested to obtain the limit test data of the system-level chip to be tested; according to the parameter-level data of the system-level chip to be tested and the The application-level data of the system-level chip under test is obtained to obtain the evaluation results of the system-level chip under test, including: based on the parameter-level data of the system-level chip under test, the application-level data of the system-level chip under test, and the limit test of the system-level chip under test data to obtain the evaluation results of the SoC under test. The obtained application-level data of the system-level chip under test is compared with the preset standard, and when the obtained application-level data is within the range of the preset standard, it means that the board-level test of the system-level chip under test is qualified. When the board-level test of the system-level chip to be tested is qualified, the limit parameter test is performed on the system-level chip to be tested to obtain limit test data of the system-level chip to be tested. The limit parameter refers to the limit value of each measurement parameter, such as the highest frequency, the highest voltage and so on.

In one embodiment, the comprehensive performance test and evaluation process of the SoC chip is shown in FIG. 7 . Firstly, the ATE test is carried out at a normal temperature of 25° C., and the product parameter index performance optimization test is completed. At the same time, according to the requirements of the chip product grade, high and low temperature tests are carried out respectively, and the temperature value is set according to the need. If necessary, conduct failure analysis for chips that fail the ATE test. Then carry out the SoC system function verification test, first conduct application-level tests such as operating performance at room temperature at 25°C, high-speed communication interface protocol, test program use case verification, system-level average power consumption, and then conduct high and low temperature tests according to the requirements of the chip product level. Test (set the temperature value as needed). After completion, carry out limit parameter tests (such as maximum frequency, maximum voltage, etc.), and carry out tests under temperature conditions as needed. After completing all the projects, organize the data.

The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, all possible combinations of the technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the present invention, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the patent scope of the invention. It should be pointed out that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent for the present invention should be based on the appended claims.

Claims (10)

1. A system-level chip evaluation device, characterized in that, comprises an ATE test board, a SoC system verification board and a controller, and the ATE test board and the SoC system verification board are respectively connected to the controller; The controller controls the ATE test board to obtain parameter-level data of the system-level chip to be tested, controls the SoC system verification board to obtain application-level data of the system-level chip to be tested, and according to the system-level chip to be tested Parameter-level data and application-level data to obtain the evaluation results of the system chip under test. 2. The system-on-a-chip evaluation device according to claim 1, further comprising a development board connected to the SoC system verification board. 3. The SoC evaluation device according to claim 1, further comprising a signal generator connected to the SoC system verification board. 4. The SoC evaluation device according to claim 1, further comprising an oscilloscope connected to the SoC system verification board. 5. The system-on-a-chip evaluation device according to claim 1, further comprising a host computer connected to the SoC system verification board. 6. The system-level chip evaluation device according to claim 1, wherein the SoC system verification board includes a peripheral interface and a processor, the peripheral interface is connected to the processor, and the processor is connected to the processor System-on-chip connections under test. 7. The system-on-a-chip evaluation device according to claim 6, wherein the SoC system verification board further comprises a SoC test socket, and the system-on-chip to be tested is connected to the processor through the SoC test socket . 8. The system-on-a-chip evaluation device according to claim 6, wherein the SoC system verification board further comprises a memory interface, and the memory interface is connected to the processor. 9. A system-on-chip evaluation method of the system-on-chip evaluation device according to any one of claims 1-8, characterized in that it comprises the steps of: Performing an ATE test on the system-level chip to be tested through the ATE test board to obtain parameter-level data of the system-level chip to be tested; When the ATE test of the system-level chip to be tested is qualified, a board-level test is performed on the system-level chip to be tested through a SoC system verification board to obtain application-level data of the system-level chip to be tested; An evaluation result of the SoC under test is obtained according to the parameter level data of the SoC under test and the application level data of the SoC under test. 10. The system-level chip evaluation method according to claim 9, wherein the system-level chip to be tested is subjected to an ATE test through the ATE test board to obtain the parameter level of the system-level chip to be tested. After the data also include: When the ATE test of the system-on-a-chip under test fails, a failure analysis is performed on the system-on-chip under test that fails the ATE test.